From: Havard Skinnemoen
This allows use to add block diagrams in documentations,
such as the block diagram in docs/specs/impi.rst.
Signed-off-by: Havard Skinnemoen
Signed-off-by: Hao Wu
---
docs/conf.py | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/docs/conf.py b
From: Havard Skinnemoen
This document is an attempt to briefly document the existing IPMI
emulation support on the main processor. It provides the necessary
background for the BMC-side IPMI emulation proposed by the next patch.
Signed-off-by: Havard Skinnemoen
Signed-off-by: Hao Wu
---
docs
Addressed other comments from Corey in the original
patch set.
Hao Wu (4):
hw/ipmi: Refactor IPMI interface
hw/ipmi: Take out common from ipmi_bmc_extern.c
hw/ipmi: Add an IPMI external host device
hw/ipmi: Add a KCS Module for NPCM7XX
Havard Skinnemoen (3):
docs: enable sphinx
: Havard Skinnemoen
Signed-off-by: Hao Wu
---
docs/specs/ipmi.rst | 70 +
1 file changed, 70 insertions(+)
diff --git a/docs/specs/ipmi.rst b/docs/specs/ipmi.rst
index e0badc7f15..b06ad74728 100644
--- a/docs/specs/ipmi.rst
+++ b/docs/specs/ipmi.rst
with device ipmi-bmc-extern.
For more details of IPMI host device in BMC emulation, see
docs/specs/ipmi.rst.
Signed-off-by: Hao Wu
---
configs/devices/arm-softmmu/default.mak | 2 +
hw/ipmi/Kconfig | 4 +
hw/ipmi/ipmi_extern.c | 18 ++-
hw/ipmi
ent representing BMC side simulation.
(6) Appy the changes to the entire IPMI library.
Signed-off-by: Hao Wu
---
hw/acpi/ipmi.c | 4 +-
hw/ipmi/ipmi.c | 60 +
hw/ipmi/ipmi_bmc_extern.c | 67 ++
hw/ipmi/ipmi_bmc_sim.c |
.
Basically most of the message transaction are moved. The stuff remained
are basically hardware operations like handle_reset and handle_hw_op.
These stuff have different behaviors in core-side and BMC-side
emulation.
Signed-off-by: Hao Wu
---
hw/ipmi/ipmi_bmc_extern.c | 420
READ_STATE, ipmi_kcs.c (core
side emulation) reads a message from BMC while npcm7xx_kcs.c
(BMC-side emulation) sends a message to the core.
Signed-off-by: Hao Wu
Reviewed-by: Tyrone Ting
---
docs/system/arm/nuvoton.rst | 1 -
hw/arm/npcm7xx.c | 10 +-
hw/ipmi/meson.build
s the best
here. Maybe Corey can shed some light on this one? Thank you!
Best Regards,
On Mon, Mar 27, 2023 at 5:34 AM Cédric Le Goater wrote:
> Hello Hao,
>
> On 3/25/23 00:09, Hao Wu wrote:
> > This patch refactors the IPMI interface so that it can be used by both
> > t
Thank you. I'll include the change in the next patch set when I refactor
patch v4 (which might take a while.)
On Sat, Mar 25, 2023 at 4:56 PM Corey Minyard wrote:
> On Fri, Mar 24, 2023 at 04:08:59PM -0700, Hao Wu wrote:
> > From: Havard Skinnemoen
> >
> > This
; &error_abort);
> > }
> >
> > -static void sdhci_attach_drive(SDHCIState *sdhci)
> > +static void sdhci_attach_drive(SDHCIState *sdhci, int unit)
> > {
> > -DriveInfo *di = drive_get_next(IF_SD);
> > +Drive
ably avoids the
issue.
On Tue, Feb 22, 2022 at 5:28 PM Patrick Venture wrote:
>
>
> On Mon, Feb 21, 2022 at 5:30 AM Peter Maydell
> wrote:
>
>> On Wed, 16 Feb 2022 at 17:30, Peter Maydell
>> wrote:
>> >
>> > On Tue, 8 Feb 2022 at 18:18, Patrick Ventur
From: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Signed-off-by: Shengtan Mao
Signed-off-by: Patrick Venture
Signed-off-by: Hao Wu
---
v4:
* use strncmp to compare fixed length strings
v3:
* fixup compilation from missing macro value
v2:
* update copyright year
* check
I have sent an updated version that uses memcmp()
On Fri, Feb 25, 2022 at 3:44 AM Peter Maydell
wrote:
> On Thu, 24 Feb 2022 at 19:03, Hao Wu wrote:
> >
> > From: Shengtan Mao
> >
> > Reviewed-by: Hao Wu
> > Reviewed-by: Chris Rauer
> > Signed-
From: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Signed-off-by: Shengtan Mao
Signed-off-by: Patrick Venture
---
v5
* use memcmp to compare whether strings are expected
v4
* use strncmp instead of strcmp
v3:
* fixup compilation from missing macro value
v2:
* update
256 */
> >257 case 0x02:
> >258 retval = 0xf0;
> >259 break;
> >
> > For QEMU the AER915 is a very simple sensor model.
> >
> > [*] https://www.bealecorner.org/best/measure/z2/index.html
> >
> > Signed-off-by: Ph
ncluding PMBus devices or devices which need GPIO lines to be
> connected).
>
> Signed-off-by: Peter Maydell
>
Reviewed-by: Hao Wu
> ---
> Feel free to suggest other i2c devices that should be marked
> as in the group; as I say, I erred on the side of not putting
>
On Tue, Feb 8, 2022 at 9:23 AM Peter Maydell
wrote:
> For arm boards with an i2c bus which a user could reasonably
> want to plug arbitrary devices, add 'imply I2C_DEVICES' to the
> Kconfig stanza.
>
> Signed-off-by: Peter Maydell
>
Reviewed-by: Hao Wu
> ---
2 at 9:10 AM Patrick Venture wrote:
>
>
> On Mon, Jan 17, 2022 at 6:05 AM Corey Minyard wrote:
>
>> On Sun, Jan 09, 2022 at 06:17:34PM -0800, Patrick Venture wrote:
>> > On Fri, Jan 7, 2022 at 7:04 PM Patrick Venture
>> wrote:
>> >
>> > > From:
On Thu, Jan 27, 2022 at 6:55 AM Corey Minyard wrote:
> On Wed, Jan 26, 2022 at 04:09:03PM -0800, Hao Wu wrote:
> > Hi,
> >
> > Sorry for the late reply. I'm not sure what "auto-increment" means here.
>
> The question is: When a value is read, does t
Is this reply to a wrong thread? I thought it was applied a long time ago.
Thanks,
On Mon, Nov 1, 2021 at 10:33 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On Thu, 11 Mar 2021 at 13:11, Hao Wu wrote:
> >
> > This patch set implements the Tachometer (a
On Mon, Nov 1, 2021 at 10:41 AM Peter Maydell
wrote:
> On Thu, 21 Oct 2021 at 19:40, Hao Wu wrote:
> >
> > We made 3 changes to the at24c_eeprom_init function in
> > npcm7xx_boards.c:
> >
> > 1. We allow the function to take a I2CBus* as parameter. This all
I was trying to allow attaching a device using "-device xxx,bus=smbus[0]"
Maybe there's a better way to allow that?
I guess I can drop this one from the patch set.
On Mon, Nov 1, 2021 at 10:33 AM Peter Maydell
wrote:
> On Thu, 21 Oct 2021 at 19:40, Hao Wu wrote:
> >
&
style.
3. Squash patch 7 into patch 5 to make it compile.
4. Add a new patch 7.
Hao Wu (5):
hw/i2c: Clear ACK bit in NPCM7xx SMBus module
hw/i2c: Read FIFO during RXF_CTL change in NPCM7XX SMBus
hw/adc: Fix CONV bit in NPCM7XX ADC CON register
hw/adc: Make adci[*] R/W in NPCM7XX ADC
hw/
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed-by
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 82 -
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of write only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file ch
with the same unit number,
the following error will occur: `Device with id 'none85' exists`.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index
This patch set implements the Nuvoton MMC device
for NPCM7XX boards.
The MMC device is compatible with the SDHCI interface
in QEMU. It allows the user to attach an SD card image
to it.
Changes since v2:
1. Fix an error use of strcmp in qtest.
Changes since v1:
1. Rearrange the "add SDHCI command
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
hw/sd/meson.build | 1 +
hw/sd/npcm7xx_sdhci.c | 182 ++
include
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
tests/qtest/libqos/meson.build | 1 +
tests/qtest/libqos/sdhci-cmd.c | 116 +
tests
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
hw/arm/npcm7xx.c | 12 +++-
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 13 insertions(+), 1
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
tests/qtest/meson.build | 1 +
tests/qtest/npcm7xx_sdhci-test.c | 209 +++
2
From: Shengtan Mao
Signed-off-by: Shengtan Mao
Reviewed-by: Hao Wu
Reviewed-by: Tyrone Ting
Signed-off-by: Hao Wu
Reviewed-by: Peter Maydell
---
hw/arm/npcm7xx_boards.c | 20
1 file changed, 20 insertions(+)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm
Hi,
I've sent a new patch set which uses memcpy here. Thank you!
On Tue, Nov 2, 2021 at 11:25 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> From: Shengtan Mao
>
> Signed-off-by: Shengtan Mao
> Signed-off-by: Hao Wu
> Reviewed-by: Hao Wu
s Huth wrote:
> On 01/11/2021 18.47, Hao Wu wrote:
> >
> >
> > On Mon, Nov 1, 2021 at 10:41 AM Peter Maydell > <mailto:peter.mayd...@linaro.org>> wrote:
> >
> > On Thu, 21 Oct 2021 at 19:40, Hao Wu > <mailto:wuhao...@google.com>
ement the function in NPCM7xx board file instead
of the EEPROM device file.
2. Slightly modify patch 6 to adapt to the changes and QEMU comment style.
3. Squash patch 7 into patch 5 to make it compile.
4. Add a new patch 7.
Hao Wu (6):
hw/i2c: Clear ACK bit in NPCM7xx SMBus module
hw/i2c: Read
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed-by
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1
with the same unit number,
the following error will occur: `Device with id 'none85' exists`.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 82 -
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of write only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file ch
This type is used to represent block devs that are not suitable to
be represented by other existing types.
Signed-of-by: Hao Wu
---
blockdev.c| 3 ++-
include/sysemu/blockdev.h | 1 +
meson | 2 +-
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 82 -
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
ly modify patch 6 to adapt to the changes and QEMU comment style.
3. Squash patch 7 into patch 5 to make it compile.
4. Add a new patch 7.
Hao Wu (6):
hw/i2c: Clear ACK bit in NPCM7xx SMBus module
hw/i2c: Read FIFO during RXF_CTL change in NPCM7XX SMBus
hw/adc: Fix CONV bit in NPCM7XX ADC CO
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed-by
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i2c
with the same unit number,
the following error will occur: `Device with id 'none85' exists`.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
---
hw/adc/npcm7xx_adc.c | 2 +-
tests
The ID can be used to indicate SMBus modules when adding
dynamic devices to them.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index 2ab0080e0b..72953d65ef 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of read only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file changed, 1 insertion(+), 1 del
Add cortex A35 core and enable it for virt board.
Signed-off-by: Hao Wu
Reviewed-by: Joe Komlodi
---
docs/system/arm/virt.rst | 1 +
hw/arm/virt.c| 1 +
target/arm/cpu64.c | 69
3 files changed, 71 insertions(+)
diff --git a/docs
Hi,
This is used by a new series of Nuvoton SoC (NPCM8XX) which contains 4
Cortex A-35 cores.
I'll update the missing fields in a follow-up patch set.
On Thu, Aug 18, 2022 at 7:59 AM Peter Maydell
wrote:
> On Mon, 15 Aug 2022 at 22:35, Hao Wu wrote:
> >
> > Add cortex A3
Add cortex A35 core and enable it for virt board.
Signed-off-by: Hao Wu
Reviewed-by: Joe Komlodi
---
docs/system/arm/virt.rst | 1 +
hw/arm/virt.c| 1 +
target/arm/cpu64.c | 80
3 files changed, 82 insertions(+)
diff --git a/docs
On Wed, Aug 24, 2022 at 3:35 AM Bin Meng wrote:
> From: Bin Meng
>
> The test cases 'test_{tx,rx}' call socketpair() which does not exist
> on win32. Exclude them.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Hao Wu
> ---
>
> tests/qtest/npcm7xx_emc-
On Mon, Oct 3, 2022 at 10:01 PM Joel Stanley wrote:
> openpower.xyz was retired some time ago. The OpenBMC Jenkins is where
> images can be found these days.
>
> Signed-off-by: Joel Stanley
>
Reviewed-by: Hao Wu
> ---
> docs/system/arm/nuvoton.rst | 4 ++--
> 1 fi
;
> On Thu, May 26, 2022 at 8:54 AM Peter Maydell
> wrote:
>
>> On Fri, 25 Feb 2022 at 17:45, Hao Wu wrote:
>> >
>> > From: Shengtan Mao
>> >
>> > Reviewed-by: Hao Wu
>> > Reviewed-by: Chris Rauer
>> > Signed-off-by: Shengtan
Creating 1GB image for a simple qtest is unnecessary
and could lead to failures. We reduce the image size
to 1MB to reduce the test overhead.
Signed-off-by: Hao Wu
---
tests/qtest/npcm7xx_sdhci-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/npcm7xx_sdhci
Hi,
It seems like this patch set is reviewed but never merged. Who should take
this patch set? What are our next steps for them?
Thanks!
On Mon, Jan 31, 2022 at 2:29 PM Patrick Venture wrote:
> From: Hao Wu
>
> SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible
> in
Havard is no longer working on the Nuvoton systems for a while
and won't be able to do any work on it in the future. So I'll
take over maintaining the Nuvoton system from him.
Signed-off-by: Hao Wu
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAI
Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices.
Signed-off-by: Hao Wu
Reviewed-by: Chris Rauer
---
MAINTAINERS| 6 +-
hw/ssi/meson.build | 2 +-
hw/ssi/npcm_pspi.c
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
---
docs/system/arm/nuvoton.rst | 2 +-
hw/arm/npcm7xx.c| 25 +++--
include/hw/arm/npcm7xx.h| 2 ++
3 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/docs/system/arm/nuvoton.rst b/docs/system
This patch set adds peripheral SPI (PSPI) modules
to NPCM7XX SoCs. These modules can be used to
connect any SPI peripheral devices to the SoC.
This module will also be used in the next generation
NPCM8XX SoCs which haven't been merged yet.
Thanks!
Hao Wu (3):
MAINTAINERS: Add myse
Thanks for your review!
On Mon, Feb 6, 2023 at 11:13 PM Philippe Mathieu-Daudé
wrote:
> On 7/2/23 00:34, Hao Wu wrote:
> > Nuvoton's PSPI is a general purpose SPI module which enables
> > connections to SPI-based peripheral devices.
> >
> > Signed-off-by: Hao
On Tue, Feb 7, 2023 at 10:46 AM Hao Wu wrote:
> Thanks for your review!
>
> On Mon, Feb 6, 2023 at 11:13 PM Philippe Mathieu-Daudé
> wrote:
>
>> On 7/2/23 00:34, Hao Wu wrote:
>> > Nuvoton's PSPI is a general purpose SPI module which enables
>> >
Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices.
Signed-off-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Philippe Mathieu-Daude
---
MAINTAINERS| 6 +-
hw/ssi/meson.build | 2 +-
hw/ssi/npcm_p
npcm-pspi.c according to
Phillipe Mathieu-Daude's review.
Thanks!
Hao Wu (3):
MAINTAINERS: Add myself to maintainers and remove Havard
hw/ssi: Add Nuvoton PSPI Module
hw/arm: Attach PSPI module to NPCM7XX SoC
MAINTAINERS | 8 +-
docs/system/arm/nuvoton.rst | 2
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Philippe Mathieu-Daude
---
docs/system/arm/nuvoton.rst | 2 +-
hw/arm/npcm7xx.c| 25 +++--
include/hw/arm/npcm7xx.h| 2 ++
3 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/docs
Havard is no longer working on the Nuvoton systems for a while
and won't be able to do any work on it in the future. So I'll
take over maintaining the Nuvoton system from him.
Signed-off-by: Hao Wu
Acked-by: Havard Skinnemoen
Reviewed-by: Philippe Mathieu-Daude
---
MAINTAINERS | 2
Thanks for pointing that out. I'll send another version to fix that.
On Tue, Feb 7, 2023 at 11:48 PM Philippe Mathieu-Daudé
wrote:
> On 7/2/23 20:45, Hao Wu wrote:
> > Nuvoton's PSPI is a general purpose SPI module which enables
> > connections to SPI-based periphera
2 to match the datasheet.
-- Changes from v1 --
A few minor updates for npcm-pspi.c according to
Phillipe Mathieu-Daude's review.
Thanks!
Hao Wu (3):
MAINTAINERS: Add myself to maintainers and remove Havard
hw/ssi: Add Nuvoton PSPI Module
hw/arm: Attach PSPI module to NPCM7XX SoC
M
Havard is no longer working on the Nuvoton systems for a while
and won't be able to do any work on it in the future. So I'll
take over maintaining the Nuvoton system from him.
Signed-off-by: Hao Wu
Acked-by: Havard Skinnemoen
Reviewed-by: Philippe Mathieu-Daude
---
MAINTAINERS | 2
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Philippe Mathieu-Daude
---
docs/system/arm/nuvoton.rst | 2 +-
hw/arm/npcm7xx.c| 25 +++--
include/hw/arm/npcm7xx.h| 2 ++
3 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/docs
Nuvoton's PSPI is a general purpose SPI module which enables
connections to SPI-based peripheral devices.
Signed-off-by: Hao Wu
Reviewed-by: Chris Rauer
Reviewed-by: Philippe Mathieu-Daude
---
MAINTAINERS| 6 +-
hw/ssi/meson.build | 2 +-
hw/ssi/npcm_p
gt; > (Detected with the clang leak sanitizer.)
> >
> > Signed-off-by: Peter Maydell
> > ---
> > hw/misc/npcm7xx_clk.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Reviewed-by: Richard Henderson
>
> Reviewed-by: Hao Wu
> r~
>
>
p an extra variable in patch 5.
-- Changes since v1:
1. Rewrote patch 5 to implement the function in NPCM7xx board file instead
of the EEPROM device file.
2. Slightly modify patch 6 to adapt to the changes and QEMU comment style.
3. Squash patch 7 into patch 5 to make it compile.
4. Add a new pat
This type is used to represent block devs that are not suitable to
be represented by other existing types.
A sample use is to represent an at24c eeprom device defined in
hw/nvram/eeprom_at24c.c. The block device can be used to contain the
content of the said eeprom device.
Signed-off-by: Hao Wu
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed-by
We allow at24c_eeprom_init to take a I2CBus* as parameter. This allows
us to attach an EEPROM device behind an I2C mux which is not
possible with the old method.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of write only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file ch
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1
This patch allows the user to attach an external drive as a property
for an onboard at24c eeprom device. It uses an unit number to
distinguish different devices.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 82 -
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
p an extra variable in patch 5.
-- Changes since v1:
1. Rewrote patch 5 to implement the function in NPCM7xx board file instead
of the EEPROM device file.
2. Slightly modify patch 6 to adapt to the changes and QEMU comment style.
3. Squash patch 7 into patch 5 to make it compile.
4. Add a new pat
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed-by
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of write only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file ch
This type is used to represent block devs that are not suitable to
be represented by other existing types.
A sample use is to represent an at24c eeprom device defined in
hw/nvram/eeprom_at24c.c. The block device can be used to contain the
content of the said eeprom device.
Signed-off-by: Hao Wu
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c
p an extra variable in patch 5.
-- Changes since v1:
1. Rewrote patch 5 to implement the function in NPCM7xx board file instead
of the EEPROM device file.
2. Slightly modify patch 6 to adapt to the changes and QEMU comment style.
3. Squash patch 7 into patch 5 to make it compile.
4. Add a new pat
This type is used to represent block devs that are not suitable to
be represented by other existing types.
A sample use is to represent an at24c eeprom device defined in
hw/nvram/eeprom_at24c.c. The block device can be used to contain the
content of the said eeprom device.
Signed-off-by: Hao Wu
The ACK bit in NPCM7XX SMBus module should be cleared each time it
sends out a NACK signal. This patch fixes the bug that it fails to
do so.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/i2c/npcm7xx_smbus.c | 2 +-
1 file changed, 1 insertion(+), 1
From: Patrick Venture
Adds supported i2c devices to the quanta-gbc-bmc board.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 82 -
1 file changed, 49 insertions(+), 33 deletions(-)
diff --git a/hw/arm/npcm7xx_boards.c
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu
Reviewed-by: Patrick Venture
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c
Originally we read in from SMBus when RXF_STS is cleared. However,
the driver clears RXF_STS before setting RXF_CTL, causing the SM bus
module to read incorrect amount of bytes in FIFO mode when the number
of bytes read changed. This patch fixes this issue.
Signed-off-by: Hao Wu
Reviewed-by
Our sensor test requires both reading and writing from a sensor's
QOM property. So we need to make the input of ADC module R/W instead
of write only for that to work.
Signed-off-by: Hao Wu
Reviewed-by: Titus Rwantare
Reviewed-by: Peter Maydell
---
hw/adc/npcm7xx_adc.c | 2 +-
1 file ch
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