Hi,
This is used by a new series of Nuvoton SoC (NPCM8XX) which contains 4
Cortex A-35 cores.
I'll update the missing fields in a follow-up patch set.
On Thu, Aug 18, 2022 at 7:59 AM Peter Maydell <peter.mayd...@linaro.org>
wrote:
> On Mon, 15 Aug 2022 at 22:35, Hao Wu <wuhao...@google.com> wrote:
> >
> > Add cortex A35 core and enable it for virt board.
> >
> > Signed-off-by: Hao Wu <wuhao...@google.com>
> > Reviewed-by: Joe Komlodi <koml...@google.com>
>
> > +static void aarch64_a35_initfn(Object *obj)
> > +{
> > + ARMCPU *cpu = ARM_CPU(obj);
> > +
> > + cpu->dtb_compatible = "arm,cortex-a35";
> > + set_feature(&cpu->env, ARM_FEATURE_V8);
> > + set_feature(&cpu->env, ARM_FEATURE_NEON);
> > + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> > + set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> > + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> > + set_feature(&cpu->env, ARM_FEATURE_EL2);
> > + set_feature(&cpu->env, ARM_FEATURE_EL3);
> > + set_feature(&cpu->env, ARM_FEATURE_PMU);
> > +
> > + /* From B2.2 AArch64 identification registers. */
> > + cpu->midr = 0x410fd042;
>
> The r1p0 TRM is out, so we might as well emulate that: 0x411FD040
>
> A few fields are missing:
>
> cpu->isar.dbgdidr
> cpu->isar.dbgdevid
> cpu->isar.dbgdevid1
> cpu->isar.reset_pmcr_el0
> cpu->gic_pribits
>
> (these probably landed after you wrote these patch).
>
> Otherwise looks OK.
>
> Remind me, what did you want the Cortex-A35 in particular for ?
>
> thanks
> -- PMM
>
