Re: [RFC v2 59/76] target/riscv: rvv-0.9: floating-point slide instructions

7;re no redundant logic to be redefined. However, this still require to declare *vfslide1up'*s helper function explicitly as its function prototype is different with *vslide1up*. Any suggestions to this issue? Thanks Frank Chang

Re: [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions

On Fri, Jul 31, 2020 at 5:24 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 7/22/20 2:16 AM, frank.ch...@sifive.com wrote: > > From: Frank Chang > > > > Sign-extend vsaddu.vi immediate value. > > > > Signed-off-by: Frank Chan

[RFC v3 09/71] target/riscv: rvv-1.0: add vlenb register

From: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7afdd4814bb

[RFC v3 00/71] target/riscv: support vector extension v1.0

From: Frank Chang This patchset implements the vector extension v1.0 for RISC-V on QEMU. This patchset is sent as RFC because RVV v1.0 is still in draft state. v2 patchset was sent for RVV v0.9. However, in order to relieve the burden for the community to maintain multi-version of vector drafts

[RFC v3 08/71] target/riscv: rvv-1.0: add vcsr register

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c | 21 + 2 files changed, 28 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h

[RFC v3 03/71] target/riscv: rvv-1.0: add mstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.h| 6 ++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 16 +++- target/riscv/csr.c| 25 - 4 files

[RFC v3 01/71] target/riscv: drop vector 0.7.1 and add 1.0 support

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 10 +- target/riscv/cpu.h | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[RFC v3 15/71] target/riscv: introduce more imm value modes in translator functions

From: Frank Chang Immediate value in translator function is extended not only zero-extended and sign-extended but with more modes to be applicable with multiple formats of vector instructions. * IMM_ZX: Zero-extended * IMM_SX: Sign-extended * IMM_TRUNC_SEW: Truncate to log(SEW

[RFC v3 25/71] target/riscv: rvv-1.0: load/store whole register instructions

From: Frank Chang Add the following instructions: * vlre.v * vsr.v Signed-off-by: Frank Chang --- target/riscv/helper.h | 21 +++ target/riscv/insn32.decode | 22 target/riscv/insn_trans/trans_rvv.inc.c | 74 + target/riscv

[RFC v3 06/71] target/riscv: rvv-1.0: add translation-time vector context status

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.inc.c | 69 - target/riscv/translate.c| 33 2 files changed, 90 insertions(+), 12 deletions(-) diff

[RFC v3 11/71] target/riscv: rvv-1.0: remove MLEN calculations

From: Frank Chang As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5). Thus, remove all MLEN related calculations. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.inc.c | 35 +--- target/riscv/internals.h| 9

[RFC v3 02/71] target/riscv: Use FIELD_EX32() to extract wd field

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 793af990673..43ba272c09b 100644 --- a/target/riscv

[RFC v3 17/71] target/riscv: rvv:1.0: add translation-time nan-box helper function

From: Frank Chang Add do_nanbox() helper function to utilize gen_check_nanbox_X() to generate the NaN-boxed floating-point values based on SEW setting. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 27 + 1 file changed, 27 insertions(+) diff

[RFC v3 28/71] target/riscv: rvv-1.0: floating-point square-root instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c99575d1360..f142aa5d073 100644 --- a/target/riscv

[RFC v3 04/71] target/riscv: rvv-1.0: add sstatus VS field

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index

[RFC v3 10/71] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers

From: Frank Chang If VS field is off, accessing vector csr registers should raise an illegal-instruction exception. Signed-off-by: Frank Chang --- target/riscv/csr.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 11ce6d4576a..50a178a60d0

[RFC v3 29/71] target/riscv: rvv-1.0: floating-point classify instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f142aa5d073..a800c989050 100644 --- a/target/riscv

[RFC v3 05/71] target/riscv: rvv-1.0: introduce writable misa.v field

From: Frank Chang Implementations may have a writable misa.v field. Analogous to the way in which the floating-point unit is handled, the mstatus.vs field may exist even if misa.v is clear. Signed-off-by: Frank Chang --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

[RFC v3 20/71] target/riscv: rvv-1.0: stride load and store instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 129 +++--- target/riscv/insn32.decode | 43 +++-- target/riscv/insn_trans/trans_rvv.inc.c | 221 +++- target/riscv/vector_helper.c| 188

[RFC v3 12/71] target/riscv: rvv-1.0: add fractional LMUL

From: Frank Chang Introduce the concepts of fractional LMUL for RVV 1.0. In RVV 1.0, LMUL bits are contiguous in vtype register. Signed-off-by: Frank Chang --- target/riscv/cpu.h | 15 --- target/riscv/insn_trans/trans_rvv.inc.c | 9 ++--- target/riscv

[RFC v3 07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields from fcsr register

From: Frank Chang Remove VXRM and VXSAT fields from FCSR register as they are only presented in VCSR register. Signed-off-by: Frank Chang --- target/riscv/csr.c | 9 - 1 file changed, 9 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7f937e5b9c8..34c951d5d4b

[RFC v3 32/71] target/riscv: rvv-1.0: set-X-first mask bit instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 +++--- target/riscv/insn_trans/trans_rvv.inc.c | 5 - target/riscv/vector_helper.c| 4 3 files changed, 7 insertions(+), 8 deletions(-) diff --git

[RFC v3 14/71] target/riscv: rvv-1.0: update check functions

From: Frank Chang Update check functions with RVV 0.9 rules. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 706 1 file changed, 474 insertions(+), 232 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv

[RFC v3 22/71] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns

From: Frank Chang Replace ETYPE from signed int to unsigned int to prevent index overflow issue, which would lead to wrong index address. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv

[RFC v3 34/71] target/riscv: rvv-1.0: element index instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 7a10fc27c5f..15afc469cb0 100644 --- a/target/riscv

[RFC v3 19/71] target/riscv: rvv-1.0: configure instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 12 target/riscv/vector_helper.c| 14 +- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv

[RFC v3 16/71] target/riscv: add fp16 nan-box check generator function

From: Frank Chang If a 16-bit input is not properly nanboxed, then the input is replaced with the default qnan. Signed-off-by: Frank Chang --- target/riscv/translate.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index

[RFC v3 24/71] target/riscv: rvv-1.0: amo operations

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 100 +++--- target/riscv/insn32-64.decode | 18 +- target/riscv/insn32.decode | 36 +++- target/riscv/insn_trans/trans_rvv.inc.c | 220 ++ target/riscv

[RFC v3 35/71] target/riscv: rvv-1.0: allow load element with sign-extended

From: Frank Chang For some vector instructions (e.g. vmv.s.x), the element is loaded with sign-extended. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.inc.c | 26 ++--- 1 file changed, 19 insertions(+), 7 deletions

[RFC v3 26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns

From: Frank Chang Unlike other vector instructions, load/store vector instructions return the maximum vector size calculated with EMUL. For other vector instructions, return VLMAX as the maximum vector size. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 10

[RFC v3 40/71] target/riscv: rvv-1.0: whole register move instructions

From: Frank Chang Add the following instructions: * vmv1r.v * vmv2r.v * vmv4r.v * vmv8r.v Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvv.inc.c | 25 + 2 files changed, 29 insertions(+) diff --git a

[RFC v3 36/71] target/riscv: rvv-1.0: register gather instructions

From: Frank Chang * Add vrgatherei16.vv instruction. Signed-off-by: Frank Chang --- target/riscv/helper.h | 4 ++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvv.inc.c | 21 -- target/riscv/vector_helper.c| 53

[RFC v3 42/71] target/riscv: rvv-1.0: single-width averaging add and subtract instructions

From: Frank Chang Add the following instructions: * vaaddu.vv * vaaddu.vx * vasubu.vv * vasubu.vx Remove the following instructions: * vadd.vi Signed-off-by: Frank Chang --- target/riscv/helper.h | 16 ++ target/riscv/insn32.decode | 13 +++-- target

[RFC v3 27/71] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation

From: Frank Chang Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 1.0. Signed-off-by: Frank Chang --- target/riscv/cpu.h | 44 ++--- target/riscv/insn_trans/trans_rvv.inc.c | 11 ++- 2 files changed, 42

[RFC v3 39/71] target/riscv: rvv-1.0: floating-point scalar move instructions

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 +-- target/riscv/insn_trans/trans_rvv.inc.c | 46 ++--- 2 files changed, 27 insertions(+), 23 dele

[RFC v3 18/71] target/riscv: rvv-1.0: apply nanbox helper in opfvf_trans

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 525aff06815..8a6050f6b32 100644 --- a

[RFC v3 45/71] target/riscv: rvv-1.0: narrowing integer right shift instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 ++-- target/riscv/insn32.decode | 12 +- target/riscv/insn_trans/trans_rvv.inc.c | 30 - target/riscv

[RFC v3 30/71] target/riscv: rvv-1.0: mask population count instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.inc.c | 7 --- target/riscv/vector_helper.c| 6 +++--- 4 files

[RFC v3 41/71] target/riscv: rvv-1.0: integer extension instructions

From: Frank Chang Add the following instructions: * vzext.vf2 * vzext.vf4 * vzext.vf8 * vsext.vf2 * vsext.vf4 * vsext.vf8 Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 14 target/riscv/insn32.decode | 8 +++ target

[RFC v3 31/71] target/riscv: rvv-1.0: find-first-set mask bit instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.inc.c | 4 ++-- target/riscv/vector_helper.c| 6 +++--- 4 files changed

[RFC v3 21/71] target/riscv: rvv-1.0: index load and store instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 67 target/riscv/insn32.decode | 21 ++- target/riscv/insn_trans/trans_rvv.inc.c | 193 target/riscv/vector_helper.c| 89 ++- 4 files

[RFC v3 48/71] target/riscv: rvv-1.0: quad-widening integer multiply-add instructions

From: Frank Chang Add the following instructions: * vqmaccu.vv * vqmaccu.vx * vqmacc.vv * vqmacc.vx * vqmaccsu.vv * vqmaccsu.vx * vqmaccus.vx Signed-off-by: Frank Chang --- target/riscv/helper.h | 15 target/riscv/insn32.decode | 7 ++ target/riscv

[RFC v3 23/71] target/riscv: rvv-1.0: fault-only-first unit stride load

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 27 +++- target/riscv/insn32.decode | 14 +++ target/riscv/insn_trans/trans_rvv.inc.c | 31 -- target/riscv/vector_helper.c| 56

[RFC v3 43/71] target/riscv: rvv-1.0: single-width bit shift instructions

From: Frank Chang Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvv.inc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_

[RFC v3 33/71] target/riscv: rvv-1.0: iota instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0992d6ac86d..7a10fc27c5f 100644 --- a/target/riscv

[RFC v3 38/71] target/riscv: rvv-1.0: floating-point move instruction

From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/t

[RFC v3 50/71] target/riscv: rvv-1.0: integer comparison instructions

From: Frank Chang * Sign-extend vmselu.vi and vmsgtu.vi immediate values. * Remove "set tail elements to zeros" as tail elements can be unchanged for either VTA to have undisturbed or agnostic setting. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 4 ++

[RFC v3 37/71] target/riscv: rvv-1.0: integer scalar move instructions

From: Frank Chang * Remove "vmv.s.x: dothing if rs1 == 0" constraint. * Add vmv.x.s instruction. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvv.inc.c | 45

[RFC v3 51/71] target/riscv: use softfloat lib float16 comparison functions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/vector_helper.c | 19 --- 1 file changed, 19 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 32bcee0f380..ffcf8d2df99 100644 --- a/target

[RFC v3 62/71] target/riscv: rvv-1.0: remove integer extract instruction

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 1 - target/riscv/insn_trans/trans_rvv.inc.c | 23 --- 2 files changed, 24 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32

[RFC v3 57/71] target/riscv: rvv-1.0: single-width floating-point reduction

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a3679f79d0a..543d94ba6a8 100644 --- a/target/riscv/vector_helper.c

[RFC v3 47/71] target/riscv: rvv-1.0: add Zvqmac extension

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/translate.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 085381fee00..8844975bf94 100644 --- a/target/riscv

[RFC v3 63/71] target/riscv: rvv-1.0: floating-point min/max instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 359ed6605c6..10b99113712 100644 --- a/target/riscv

[RFC v3 44/71] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow

From: Frank Chang Clear tail elements only if VTA is agnostic. Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 20 ++--- target/riscv/insn_trans/trans_rvv.inc.c | 2 +- target/riscv/vector_helper.c| 40 +++-- 3 files changed

[RFC v3 53/71] target/riscv: rvv-1.0: mask-register logical instructions

From: Frank Chang Clear tail elements only if VTA is agnostic. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 3 ++- target/riscv/vector_helper.c| 4 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans

[RFC v3 64/71] target/riscv: introduce floating-point rounding mode enum

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/fpu_helper.c | 12 ++-- target/riscv/insn_trans/trans_rvv.inc.c | 18 +- target/riscv/internals.h| 9 + 3 files changed, 24 insertions(+), 15 deletions(-) diff --git a

[RFC v3 58/71] target/riscv: rvv-1.0: widening floating-point reduction instructions

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 9e8798902a3..64bd4aa239d 100644 --- a/target

[RFC v3 46/71] target/riscv: rvv-1.0: widening integer multiply-add instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index c4fe9767585..2e305d492d8 100644 --- a/target/riscv

[RFC v3 54/71] target/riscv: rvv-1.0: slide instructions

From: Frank Chang * Remove clear function from helper functions as the tail elements are unchanged in RVV 1.0. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/target/riscv/vector_helper.c b

[RFC v3 49/71] target/riscv: rvv-1.0: single-width saturating add and subtract instructions

From: Frank Chang Sign-extend vsaddu.vi immediate value. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index

[RFC v3 66/71] target/riscv: rvv-1.0: widening floating-point/integer type-convert

From: Frank Chang Add the following instructions: * vfwcvt.rtz.xu.f.v * vfwcvt.rtz.x.f.v Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang --- target/riscv/helper.h | 6 +++ target/riscv/insn32.decode

[RFC v3 65/71] target/riscv: rvv-1.0: floating-point/integer type-convert instructions

From: Frank Chang Add the following instructions: * vfcvt.rtz.xu.f.v * vfcvt.rtz.x.f.v Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding modes. Signed-off-by: Frank Chang --- target/riscv/helper.h | 6 ++ target/riscv/insn32.decode

[RFC v3 55/71] target/riscv: rvv-1.0: floating-point slide instructions

From: Frank Chang Add the following instructions: * vfslide1up.vf * vfslide1down.vf Signed-off-by: Frank Chang --- target/riscv/helper.h | 7 ++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 4 + target/riscv/vector_helper.c

[RFC v3 69/71] target/riscv: gdb: modify gdb csr xml file to align with csr register map

From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Frank Chang --- gdb-xml/riscv-32bit-csr.xml | 11 ++- gdb-xml/riscv-64bit-csr.xml | 11 ++- target/riscv/gdbstub.c | 4 ++-- 3 files changed, 14 insertions(+), 12 deletions(-) diff --git a/gdb-xml/riscv

[RFC v3 52/71] target/riscv: rvv-1.0: floating-point compare instructions

From: Frank Chang Clear tail elements only if VTA is agnostic. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 42 +++- 1 file changed, 17 insertions(+), 25 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c

[RFC v3 68/71] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 30 ++ target/riscv/insn32.decode | 15 +++-- target/riscv/insn_trans/trans_rvv.inc.c | 52 ++--- target/riscv/vector_helper.c| 76

[RFC v3 56/71] target/riscv: rvv-1.0: narrowing fixed-point clip instructions

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 ++-- target/riscv/insn32.decode | 12 +++--- target/riscv/insn_trans/trans_rvv.inc.c | 12 +++--- target/riscv/vector_helper.c| 52

[RFC v3 71/71] target/riscv: gdb: support vector registers for rv32

From: Greentime Hu This patch adds vector support for rv32 gdb. It allows gdb client to access vector registers correctly. Signed-off-by: Greentime Hu Signed-off-by: Frank Chang --- gdb-xml/riscv-32bit-csr.xml | 7 +++ 1 file changed, 7 insertions(+) diff --git a/gdb-xml/riscv-32bit

[RFC v3 59/71] target/riscv: rvv-1.0: single-width scaling shift instructions

From: Frank Chang log(SEW) truncate vssra.vi immediate value. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index

[RFC v3 60/71] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 22 --- target/riscv/insn32.decode | 7 - target/riscv/insn_trans/trans_rvv.inc.c | 9 -- target/riscv/vector_helper.c| 205

[RFC v3 61/71] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 6 -- target/riscv/insn32.decode | 2 -- target/riscv/insn_trans/trans_rvv.inc.c | 2 -- target/riscv/vector_helper.c| 13 - 4

[RFC v3 67/71] target/riscv: add "set round to odd" rounding mode helper function

From: Frank Chang helper_set_rounding_mode() is responsible for SIGILL, and "round to odd" should be an interface private to translation, so add a new independent helper_set_rod_rounding_mode(). Signed-off-by: Frank Chang --- target/riscv/fpu_helper.c | 5 + target/riscv/helper

[RFC v3 70/71] target/riscv: gdb: support vector registers for rv64

From: Hsiangkai Wang Signed-off-by: Hsiangkai Wang Signed-off-by: Frank Chang --- gdb-xml/riscv-64bit-csr.xml | 7 ++ target/riscv/cpu.c | 1 + target/riscv/cpu.h | 25 +++ target/riscv/gdbstub.c | 126 +++- 4 files changed, 157

Re: [RFC 0/1] target/riscv: add RNMI support

On Fri, Mar 19, 2021 at 9:30 PM Alistair Francis wrote: > On Tue, Mar 9, 2021 at 2:31 AM wrote: > > > > From: Frank Chang > > > > This patchset add suport of Resumable NMI (RNMI) in RISC-V. > > > > There are four new CSRs and one new instruction added to

Re: [RFC 1/1] target/riscv: add support of RNMI

On Fri, Mar 19, 2021 at 9:29 PM Alistair Francis wrote: > On Tue, Mar 9, 2021 at 2:30 AM wrote: > > > > From: Frank Chang > > > > Signed-off-by: Frank Chang > > I had a quick look and this looks fine. I haven't compared it to the > spec yet though.

[RFC v2 1/4] target/riscv: add RNMI cpu feature

From: Frank Chang Signed-off-by: Frank Chang --- hw/riscv/riscv_hart.c | 8 +++ include/hw/riscv/riscv_hart.h | 2 ++ target/riscv/cpu.c| 40 +++ target/riscv/cpu.h| 12 ++- target/riscv/cpu_bits.h | 6

[RFC v2 2/4] target/riscv: add RNMI CSRs

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/cpu.h | 4 +++ target/riscv/cpu_bits.h | 9 +++ target/riscv/csr.c | 59 + 3 files changed, 72 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[RFC v2 3/4] target/riscv: handle RNMI interrupt and exception

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/cpu_bits.h | 4 target/riscv/cpu_helper.c | 49 +++ 2 files changed, 49 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a376ede0cc5

[RFC v2 0/4] target/riscv: add RNMI support

From: Frank Chang This patchset add suport of Resumable NMI (RNMI) in RISC-V. There are four new CSRs and one new instruction added to allow NMI to be resumable in RISC-V, which are: = * mnscratch (0x350) * mnepc (0x351

[RFC v2 4/4] target/riscv: add RNMI mnret instruction

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 1 + target/riscv/insn32.decode| 3 ++ .../riscv/insn_trans/trans_privileged.c.inc | 13 target/riscv/op_helper.c | 31 +++ 4

Re: [RFC v2 0/4] target/riscv: add RNMI support

於 2021年4月1日 週四 下午5:27寫道： > From: Frank Chang > > This patchset add suport of Resumable NMI (RNMI) in RISC-V. > > There are four new CSRs and one new instruction added to allow NMI to be > resumable in

[Bug 1923629] Re: RISC-V Vector Instruction vssub.vv not saturating

This should be a quick fix, we will run couple tests again to ensure the fix doesn't break anything. Thanks~ ** Changed in: qemu Assignee: (unassigned) => Frank Chang (frankchang0125) -- You received this bug notification because you are a member of qemu- devel-ml, which is subsc

[RFC 1/1] target/riscv: add support of RNMI

From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/cpu.c| 40 + target/riscv/cpu.h| 16 - target/riscv/cpu_bits.h | 19 ++ target/riscv/cpu_helper.c | 47

[RFC 0/1] target/riscv: add RNMI support

From: Frank Chang This patchset add suport of Resumable NMI (RNMI) in RISC-V. There are four new CSRs and one new instruction added to allow NMI to be resumable in RISC-V, which are: = * mnscratch (0x350) * mnepc (0x351

[PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

From: Frank Chang In IEEE 754-2008 spec: Invalid operation exception is signaled when doing: fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c) unless c is a quiet NaN; if c is a quiet NaN then it is implementation defined whether the invalid operation exception is signaled

[PATCH] target/riscv: fix vssub.vv saturation bug

From: Frank Chang Doing a negate (0x0 – 0x8000) using vssub.vv produces an incorrect result of 0x8000 (should saturate to 0x7fff) Fix this bug by treating zero as a positive number. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 8 1 file changed, 4

[PATCH] target/riscv: fix vrgather macro index variable type bug

From: Frank Chang ETYPE may be type of uint64_t, thus index variable has to be declared as type of uint64_t, too. Otherwise the value read from vs1 register may be truncated to type of uint32_t. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 6 -- 1 file changed, 4

Re: [PATCH] target/riscv: fix vssub.vv saturation bug

Alistair Francis 於 2021年4月19日 週一 下午2:28寫道： > On Mon, Apr 19, 2021 at 4:02 PM wrote: > > > > From: Frank Chang > > > > Doing a negate (0x0 – 0x8000) using vssub.vv produces > > an incorrect result of 0x8000 (should saturate to 0x7fff) > >

Re: [PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

; this is unused (and overridden in pick_nan_muladd). > > I think for avoidance of confusion, you should use > > if (infzero) { > float_raise(float_flag_invalid, status); > } > return 3; /* default nan */ > > > r~ > Sure, I'll update my patch and resend again. Thanks Frank Chang

[PATCH v2] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

From: Frank Chang In IEEE 754-2008 spec: Invalid operation exception is signaled when doing: fusedMultiplyAdd(0, Inf, c) or fusedMultiplyAdd(Inf, 0, c) unless c is a quiet NaN; if c is a quiet NaN then it is implementation defined whether the invalid operation exception is signaled

[PATCH v5 00/17] support subsets of bitmanip extension

From: Frank Chang This patchset implements RISC-V B-extension v0.93 version Zba, Zbb and Zbs subset instructions. Some Zbp instructions are also implemented as they have similar behavior with their Zba-, Zbb- and Zbs-family instructions or for Zbb pseudo instructions (e.g. rev8, orc.b

[PATCH v5 01/17] target/riscv: reformat @sh format encoding for B-extension

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn32.decode | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32

[PATCH v5 02/17] target/riscv: rvb: count leading/trailing zeros

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32-64.decode | 4 +++ target/riscv/insn32.decode | 7 +++- target/riscv/insn_trans/trans_rvb.c.inc | 47 + target/riscv

[PATCH v5 09/17] target/riscv: rvb: single-bit instructions

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32-64.decode | 8 +++ target/riscv/insn32.decode | 9 +++ target/riscv/insn_trans/trans_rvb.c.inc | 90 + target/riscv

[PATCH v5 04/17] target/riscv: rvb: logic-with-negate

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvb.c.inc | 18 ++ 2 files changed, 22 insertions(+) diff --git a/target/riscv/insn32

[PATCH v5 05/17] target/riscv: rvb: pack two words into one register

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32-64.decode | 3 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvb.c.inc | 30 +++ target/riscv

[PATCH v5 11/17] target/riscv: rvb: rotate (left/right)

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32-64.decode | 3 +++ target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvb.c.inc | 36 + target/riscv

[PATCH v5 03/17] target/riscv: rvb: count bits set

From: Frank Chang Signed-off-by: Kito Cheng Reviewed-by: Richard Henderson Signed-off-by: Frank Chang --- target/riscv/insn32-64.decode | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvb.c.inc | 12 target/riscv/translate.c

[PATCH v5 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions

From: Frank Chang Add gen_shifti() and gen_shiftiw() helper functions to reuse the same interfaces for immediate shift instructions. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 54 ++--- target/riscv/translate.c

[PATCH v5 06/17] target/riscv: rvb: min/max instructions

From: Kito Cheng Signed-off-by: Kito Cheng Reviewed-by: Richard Henderson Signed-off-by: Frank Chang --- target/riscv/insn32.decode | 4 target/riscv/insn_trans/trans_rvb.c.inc | 24 2 files changed, 28 insertions(+) diff --git a/target/riscv

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