<frank.ch...@sifive.com> 於 2021年4月1日 週四 下午5:27寫道：
> From: Frank Chang <frank.ch...@sifive.com> > > This patchset add suport of Resumable NMI (RNMI) in RISC-V. > > There are four new CSRs and one new instruction added to allow NMI to be > resumable in RISC-V, which are: > > ============================================================= > * mnscratch (0x350) > * mnepc (0x351) > * mncause (0x352) > * mnstatus (0x353) > ============================================================= > * mnret: To return from RNMI interrupt/exception handler. > ============================================================= > > RNMI also has higher priority than any other interrupts or exceptions > and cannot be disable by software. > > RNMI may be used to route to other devices such as Bus Error Unit or > Watchdog Timer in the future. > > The interrupt/exception trap handler addresses of RNMI are > implementation defined. > > The technical proposal of RNMI can be found: > https://lists.riscv.org/g/tech-privileged/message/421 > > The port is available here: > https://github.com/sifive/qemu/tree/nmi-upstream-v2 > > To test RNMI, we have created another QEMU branch to have > RNMI feature enabled and also both SiFive Bus Error Unit and > Error Device included on sifive_e machine. > > Bus Error Unit (BEU) is routed to RNMI with mncause value set to 3. > When any reads or writes to Error Device, it will drive BEU RNMI. > A freedom-e-sdk RNMI example is also provided for testing. > (We will also upstream BEU and Error Device in the near future.) > > Two -cpu options are added for RNMI and BEU: > * rnmi=true to enable RNMI feature > * beu=true to enable BEU feature > > Download and build freedom-e-sdk rnmi example: > > 1. git clone g...@github.com:sifive/freedom-e-sdk.git > 2. cd freedom-e-sdk > 3. git checkout origin/dev/yihaoc/nmi -b nmi > 4. git submodule init > 5. git submodule update --recursive > 6. Follow freedom-e-sdk guide to install freedom-e-sdk: > https://sifive.github.io/freedom-e-sdk-docs/index.html > 7. make PROGRAM=example-rnmi TARGET=qemu-sifive-e31 \ > CONFIGURATION=release software > freedom-e-sdk RNMI example code is available at: https://github.com/sifive/freedom-e-sdk/tree/dev/yihaoc/nmi/software/example-rnmi > > Download, build and run freedom-e-sdk RNMI example on QEMU: > > 1. git clone g...@github.com:sifive/qemu.git > 2. cd qemu > 3. git checkout origin/upstream-nmi-beu-error-device -b > nmi-beu-error-device > 4. git submodule init > 5. git submodule update --recursive > 6. ./configure --target-list=riscv32-softmmu > 7. make -j > 8. <path to qemu-system-riscv32> -nographic -M sifive_e \ > -cpu rv32,rnmi=true,beu=true \ > --bios none -kernel <path to example-rnmi.elf> > > Output example: > > RNMI Driver Example. > Cleared accrued bus error > Enter RNMI interrupt ISR. > mnscratch: 0x00000000 > mnepc: 0x20401178 > mncause: 0x00000003 > mnstatus: 0x00001800 > Try to trigger illegal instruction exception. > Enter RNMI exception ISR. > mscratch: 0x00000000 > mepc: 0x20401208 > mcause: 0x00000002 > mstatus: 0x80007800 > Return from RNMI exception ISR. > Handled TileLink bus error > Return from RNMI interrupt ISR. > Test passed!! > > Changelog: > > v2 > * split up the series into more commits for convenience of review. > * add missing rnmi_irqvec and rnmi_excpvec properties to riscv_harts. > > Frank Chang (4): > target/riscv: add RNMI cpu feature > target/riscv: add RNMI CSRs > target/riscv: handle RNMI interrupt and exception > target/riscv: add RNMI mnret instruction > > hw/riscv/riscv_hart.c | 8 +++ > include/hw/riscv/riscv_hart.h | 2 + > target/riscv/cpu.c | 40 +++++++++++++ > target/riscv/cpu.h | 16 ++++- > target/riscv/cpu_bits.h | 19 ++++++ > target/riscv/cpu_helper.c | 49 +++++++++++++-- > target/riscv/csr.c | 59 +++++++++++++++++++ > target/riscv/helper.h | 1 + > target/riscv/insn32.decode | 3 + > .../riscv/insn_trans/trans_privileged.c.inc | 13 ++++ > target/riscv/op_helper.c | 31 ++++++++++ > 11 files changed, 236 insertions(+), 5 deletions(-) > > -- > 2.17.1 > > >
