Re: [PATCH] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions

[Frank Chang]

On Mon, Apr 19, 2021 at 11:28 PM Richard Henderson <
richard.hender...@linaro.org> wrote:

> On 4/18/21 10:56 PM, frank.ch...@sifive.com wrote:
> > +#elif defined(TARGET_RISCV)
> > +    /*
> > +     * For RISC-V, InvalidOp is set when multiplicands are Inf and zero
> > +     * and returns default NaN.
> > +     */
> > +    if (infzero) {
> > +        float_raise(float_flag_invalid, status);
> > +        return 3;
> > +    }
> > +
> > +    if (is_nan(a_cls)) {
> > +        return 0;
> > +    } else if (is_nan(b_cls)) {
> > +        return 1;
> > +    } else {
> > +        return 2;
> > +    }
>
> This second half of the function made me go look into the spec to make
> sure you
> had got that selection right.  But RISCV is always in default_nan mode, so
> all
> this is unused (and overridden in pick_nan_muladd).
>
> I think for avoidance of confusion, you should use
>
>      if (infzero) {
>          float_raise(float_flag_invalid, status);
>      }
>      return 3; /* default nan */
>
>
> r~
>

Sure, I'll update my patch and resend again.

Thanks
Frank Chang