: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 35 ---
include/hw/ssi/xilinx_spips.h | 34 ++
2 files changed, 34 insertions(+), 35 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index ef56d35
Don't set TX FIFO UNDERFLOW interrupt after done transmiting the commands.
Also update interrupts after reading out the interrupt status.
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c
Add support for zero pumping according to the transfer size register.
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 47 ---
include/hw/ssi/xilinx_spips.h | 2 ++
2 files changed, 42 insertions(+), 7 deletions(-)
diff --git a/hw
: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 559fa79..7accf5d 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -208,14 +208,14 @@ static void
Add support for the Zynq Ultrascale MPSoc Generic QSPI.
Signed-off-by: Francisco Iglesias
---
default-configs/arm-softmmu.mak | 1 +
hw/ssi/xilinx_spips.c | 574
include/hw/ssi/xilinx_spips.h | 32 ++-
3 files changed, 559 insertions
Add support for the bank address register access commands (BRRD/BRWR) and
the BULK_ERASE (0x60) command.
Signed-off-by: Francisco Iglesias
Acked-by: Marcin Krzemiński
---
hw/block/m25p80.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index
On 1 November 2017 at 20:20, mar.krzeminski
wrote:
> Hi Francisco,
>
> W dniu 01.11.2017 o 08:16, Francisco Iglesias pisze:
>
> Add support for continuous read out of the RDSR and READ_FSR status
>> registers until the chip select is deasserted. This feature is supported
&
Add support for zero pumping according to the transfer size register.
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 47 ---
include/hw/ssi/xilinx_spips.h | 2 ++
2 files changed, 42 insertions(+), 7 deletions(-)
diff --git a/hw
Add support for continuous read out of the RDSR and READ_FSR status
registers until the chip select is deasserted. This feature is supported
by amongst others 1 or more flashtypes manufactured by Numonyx (Micron),
Windbond, SST, Gigadevice, Eon and Macronix.
Signed-off-by: Francisco Iglesias
Add support for the bank address register access commands (BRRD/BRWR) and
the BULK_ERASE (0x60) command.
Signed-off-by: Francisco Iglesias
Acked-by: Marcin Krzemiński
---
hw/block/m25p80.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index
pumping according transfer register and 4
byte LQSPI addresses. Finally it adds support for the ZynqMP Generic QSPI and
adds the ZynqMP QSPI to the xlnx-zcu102 board.
Best regards,
Francisco Iglesias
Changelog:
v6 -> v7
* Moved data_read_loop into a vmstate subsection in patch 'm25
Add support for SST READ ID 0x90/0xAB commands for reading out the flash
manufacuter ID and device ID.
Signed-off-by: Francisco Iglesias
Acked-by: Alistair Francis
Acked-by: Marcin Krzemiński
---
hw/block/m25p80.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw
Add support for Micron (Numonyx) n25q512a11 and n25q512a13 flashes.
Signed-off-by: Francisco Iglesias
Acked-by: Marcin Krzemiński
Reviewed-by: Alistair Francis
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 1d0aa1d
Don't set TX FIFO UNDERFLOW interrupt after done transmiting the commands.
Also update interrupts after reading out the interrupt status.
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c
: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 35 ---
include/hw/ssi/xilinx_spips.h | 34 ++
2 files changed, 34 insertions(+), 35 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index ef56d35
Make tx/rx_data_bytes more generic so they can be reused (when adding
support for the Zynqmp Generic QSPI).
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 64 +--
1 file changed, 37 insertions(+), 27 deletions(-)
diff --git a/hw
: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 559fa79..7accf5d 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -208,14 +208,14 @@ static void
Add support for the ZynqMP QSPI (consisting of the Generic QSPI and Legacy
QSPI) and connect Numonyx n25q512a11 flashes to it.
Signed-off-by: Francisco Iglesias
Reviewed-by: Alistair Francis
---
hw/arm/xlnx-zcu102.c | 23 +++
hw/arm/xlnx-zynqmp.c | 26
Add support for the RX discard and RX drain functionality. Also transmit
one byte per dummy cycle (to the flash memories) with commands that require
these.
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 167 +-
include/hw/ssi
Add support for the Zynq Ultrascale MPSoc Generic QSPI.
Signed-off-by: Francisco Iglesias
---
default-configs/arm-softmmu.mak | 1 +
hw/ssi/xilinx_spips.c | 579
include/hw/ssi/xilinx_spips.h | 32 ++-
3 files changed, 564 insertions
Add support for 4 byte addresses in the LQSPI and correct LQSPI_CFG_SEP_BUS.
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 3a98799..7f0f317 100644
--- a/hw
Add support for zero pumping according to the transfer size register.
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 47 ---
include/hw/ssi/xilinx_spips.h | 2 ++
2 files changed, 42 insertions(+), 7 deletions(-)
diff --git a/hw
Hi Marcin,
Huge thank you once again! This time not only for reviewing but also for
having this patience with me!
I wish you a great wekeend!
Best regards,
Francisco Iglesias
On 3 Nov 2017 17:18, "mar.krzeminski" wrote:
>
>
> W dniu 03.11.2017 o 01:00, Francisco Igle
e more than necessary? (Should give the same result when
num_effective_busses == 1)
-} else if (s->snoop_state == SNOOP_STRIPING) {
+} else if (s->snoop_state == SNOOP_STRIPING ||
+ s->snoop_state == SNOOP_NONE) {
Thank you!
Best regards,
Francisco Iglesias
> for (i = 0; i < num_effective_busses(s); ++i) {
> --
> 2.7.4
>
>
S
> *s)
> for (i = 0; i < num_effective_busses(s); ++i) {
> tx_rx[i] = tx;
> }
> -} else {
> +} else if (s->cmd_dummies > 0) {
>
The variable snoop_state already keeps track of the dummy cycles, the same
the &#x
the QSPI).
Best regards,
Francisco Iglesias
Francisco Iglesias (2):
xilinx_spips: Enable only two slaves when reading/writing with stripe
xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
hw/ssi/xilinx_spips.c | 44 +++-
1 file changed, 39
Use 8 dummy cycles (4 dummy bytes) with the QIOR/QIOR4 commands in legacy mode
for matching what is expected by Micron (Numonyx) flashes (the default target
flash type of the QSPI).
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses and
chip selects are enabled (e.g reading/writing with stripe).
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 42 ++
1 file changed, 38 insertions(+), 4 deletions
On 22 February 2018 at 23:38, Alistair Francis wrote:
> On Thu, Feb 22, 2018 at 2:28 PM, Francisco Iglesias
> wrote:
> > Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses
> and
> > chip selects are enabled (e.g reading/writing with stripe).
> >
&
Use 8 dummy cycles (4 dummy bytes) with the QIOR/QIOR4 commands in legacy mode
for matching what is expected by Micron (Numonyx) flashes (the default target
flash type of the QSPI).
Signed-off-by: Francisco Iglesias
Tested-by: Alistair Francis
Reviewed-by: Alistair Francis
---
hw/ssi
the QSPI).
Best regards,
Francisco Iglesias
Changelog:
v1 -> v2
* Attempted to improve readability in the patch 'xilinx_spips: Enable only
two slaves when reading/writing with stripe' when selecting chip selects.
Francisco Iglesias (2):
xilinx_spips: Enable only two slaves
Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses and
chip selects are enabled (e.g reading/writing with stripe).
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spips.c | 41 +
1 file changed, 37 insertions(+), 4 deletions
On Tuesday, 27 February 2018, Alistair Francis wrote:
> On Fri, Feb 23, 2018 at 3:22 PM, Francisco Iglesias
> wrote:
> > Assert only the lower cs on bus 0 and upper cs on bus 1 when both buses
> and
> > chip selects are enabled (e.g reading/writing with stripe).
> >
&
On Tuesday, 27 February 2018, Peter Maydell
wrote:
> On 23 February 2018 at 23:22, Francisco Iglesias
> wrote:
> > Hi,
> >
> > The first patch in this series attempts to correct the slave selection
> when
> > using the striping functionality in the QSPI.
On 30 April 2018 at 15:27, Sai Pavan Boddu
wrote:
> Hi Francisco,
>
> On Sun, Apr 29, 2018 at 02:43:28AM +0200, Francisco Iglesias wrote:
> > Add a model of the generic DMA found on Xilinx ZynqMP.
> >
> > Signed-off-by: Francisco Iglesias
> > Signed-off-by: E
On 30 April 2018 at 15:42, Edgar E. Iglesias
wrote:
> On Sun, Apr 29, 2018 at 02:43:28AM +0200, Francisco Iglesias wrote:
> > Add a model of the generic DMA found on Xilinx ZynqMP.
>
>
> Hi Francisco,
>
> I think we need to look at the VMStateDescription, some sta
The ZynqMP contains two instances of a generic DMA, the GDMA, located in the
FPD (full power domain), and the ADMA, located in LPD (low power domain). This
patch adds these two DMAs to the ZynqMP board.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-zynqmp.c | 53
patch in the series
adds a model of the ZynqMP generic DMA (the ZDMA). The second patch in the
series connects the two instances of the ZDMA, the GDMA and the ADMA, to the
ZynqMP board.
Best regards,
Francisco Iglesias
Changelog:
v1 -> v2
* Don't unpause the DMA channel if CONT is zero a
Add a model of the generic DMA found on Xilinx ZynqMP.
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/dma/Makefile.objs | 1 +
hw/dma/xlnx-zdma.c | 835 +
include/hw/dma/xlnx-zdma.h | 84 +
3 files
On 3 May 2018 at 08:28, Edgar E. Iglesias wrote:
> On Wed, May 02, 2018 at 10:06:39PM +0200, Francisco Iglesias wrote:
> > Add a model of the generic DMA found on Xilinx ZynqMP.
>
>
> Hi Francisco,
>
>
Hi Edgar,
Thank you for reviewing again! I'll modify the patch
Add a model of the generic DMA found on Xilinx ZynqMP.
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/dma/Makefile.objs | 1 +
hw/dma/xlnx-zdma.c | 832 +
include/hw/dma/xlnx-zdma.h | 84 +
3 files
The ZynqMP contains two instances of a generic DMA, the GDMA, located in the
FPD (full power domain), and the ADMA, located in LPD (low power domain). This
patch adds these two DMAs to the ZynqMP board.
Signed-off-by: Francisco Iglesias
Reviewed-by: Alistair Francis
Reviewed-by: Edgar E
patch in the series
adds a model of the ZynqMP generic DMA (the ZDMA). The second patch in the
series connects the two instances of the ZDMA, the GDMA and the ADMA, to the
ZynqMP board.
Best regards,
Francisco Iglesias
Changelog:
v2 -> v3
* Use sizeof(s->dsc_dst) as the memcpy length when l
On [2020 Apr 02] Thu 15:47:17, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Remove comment.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> hw/dma/xlnx-zdma.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff
On [2020 Apr 02] Thu 15:47:19, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Clear DMA_DONE when halting the DMA channel.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> hw/dma/xlnx-zdma.c | 1 +
> 1 file changed, 1
On [2020 Apr 02] Thu 15:47:18, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Populate DBG0.CMN_BUF_FREE so that SW can see some free space.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> hw/dma/xlnx-zdma.c | 6 ++
On [2020 Apr 02] Thu 15:47:20, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Advance the descriptor address when stopping the channel.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> hw/dma/xlnx-zdma.c | 1 -
> 1 fil
On [2020 Apr 02] Thu 15:47:21, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Reorganize the descriptor handling so that CUR_DSCR always
> points to the next descriptor to be processed.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Igl
on the host machine, please check the QEMU CAN docs:
> https://github.com/qemu/qemu/blob/master/docs/can.txt
>
> Signed-off-by: Vikram Garhwal
Reviewed-by: Francisco Iglesias
> ---
> hw/net/can/Makefile.objs |1 +
> hw/net/can/xlnx-zynqmp-can.c | 1165
> ++
Hi Vikram,
A couple of more comments:
On the git summary:
s/controller/controllers/
On [2020 Apr 22] Wed 17:56:07, Vikram Garhwal wrote:
> Connect CAN0 and CAN1 to ZCU102 board.
Perhaps also:
s/to ZCU102 board/on the ZynqMP/
(even though zcu102 is the only board using it at the moment).
Best
.pre_write = can_filter_mask_pre_write,
> +},{ .name = "AFIR3", .addr = A_AFIR3,
> +.pre_write = can_filter_id_pre_write,
> +},{ .name = "AFMR4", .addr = A_AFMR4,
> +.pre_write = can_filter_mask_pre_write,
> + },{ .name = "AFIR4", .addr =
On [2020 Apr 30] Thu 18:24:31, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Auto-clear PHY CR Autoneg bits. This makes this model
> work with recent Linux kernels.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> hw/
On [2020 Apr 30] Thu 18:24:32, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Split the shared stream_class_init function to assign
> stream->push with better type-safety.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> -
On [2020 Apr 30] Thu 18:24:33, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Remove unncessary cast, buf is already uint8_t *.
> No functional change.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> hw/net/xilinx_axi
On [2020 Apr 30] Thu 18:24:34, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add DMA memory-region property to externally control what
> address-space this DMA operates on.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> +
> +qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0xF);
> +
> +send_data(qts, CAN0_BASE_ADDR, buf_tx);
> +
> +read_data(qts, CAN1_BASE_ADDR, buf_rx);
> +match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
> +
> +qtest_quit(qts);
> +}
> +
> +/* Testing sl
On Tue, Aug 04, 2020 at 02:11:43PM -0700, Vikram Garhwal wrote:
> Connect CAN0 and CAN1 on the ZynqMP.
>
> Signed-off-by: Vikram Garhwal
Reviewed-by: Francisco Iglesias
> ---
> hw/arm/xlnx-zcu102.c | 20
> hw/arm/xlnx-zyn
> +} else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) {
> +ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1);
> +} else {
> + /*
> + * If all bits are zero then XlnxZynqMPCAN is set in normal mode.
> + */
> +ARRAY_FIELD_D
, "can[*]", &s->can[i],
> + TYPE_XLNX_ZYNQMP_CAN);
Above line needs a minor indentation fix (a couple of extra whitespaces),
after adding those:
Reviewed-by: Francisco Iglesias
Best regards,
Francisco Iglesias
> +}
> +
> object_i
from CAN0 and CAN1 through canbus.
> CAN0
> + * initiate the data transfer to can-bus, CAN1 receives the data. Test
> compares
> + * the data sent from CAN0 with received on CAN1.
> + */
> +static void test_can_bus(void)
> +{
> +uint32_t buf_tx[4] = { 0xFF, 0x8000,
Hello Cedric!
On Wed, Apr 07, 2021 at 07:16:34PM +0200, Cédric Le Goater wrote:
> The Micron mt25qu02g is a 3V 2Gb serial NOR flash memory supporting
> dual I/O and quad I/O, 4KB, 32KB, 64KB sector erase. It also supports
> 4B opcodes.
>
> Cc: Alistair Francis
> Cc: Francisco
Hi Cedric,
On [2021 Apr 08] Thu 10:40:18, Cédric Le Goater wrote:
> On 4/8/21 10:00 AM, Francisco Iglesias wrote:
> > Hello Cedric!
> >
> > On Wed, Apr 07, 2021 at 07:16:34PM +0200, Cédric Le Goater wrote:
> >> The Micron mt25qu02g is a 3V 2Gb serial NOR flash memor
On [2021 Apr 27] Tue 15:56:10, Alistair Francis wrote:
> On Fri, Apr 23, 2021 at 4:46 PM Bin Meng wrote:
> >
> > On Mon, Feb 8, 2021 at 10:41 PM Bin Meng wrote:
> > >
> > > On Thu, Jan 21, 2021 at 10:18 PM Francisco Iglesias
> > > wrote:
> > >
xF) {
switch(s->cmd_in_progress){
case QOR:
case QOR4
case QIOR:
case QIOR4:
n_dummies = 10;
break;
default:
n_dummies = 8;
break;
}
}
return n_dummies;
Best regards,
Francisco Iglesias
> +num_dummies = 10;
>
Hi Bin,
On [2021 Jan 21] Thu 16:59:51, Bin Meng wrote:
> Hi Francisco,
>
> On Thu, Jan 21, 2021 at 4:50 PM Francisco Iglesias
> wrote:
> >
> > Dear Bin,
> >
> > On [2021 Jan 20] Wed 22:20:25, Bin Meng wrote:
> > > Hi Francisco,
> > >
&g
Hello Edgar,
On [2021 Feb 08] Mon 16:30:00, Edgar E. Iglesias wrote:
>On Mon, Feb 8, 2021 at 3:42 PM Bin Meng wrote:
>
> On Thu, Jan 21, 2021 at 10:18 PM Francisco Iglesias
> wrote:
> >
> > Hi Bin,
> >
> > On [2021
(get_man(s)) {
> > /* Dummy cycles - modeled with bytes writes instead of bits */
> > +case MAN_SST:
> > +s->needed_bytes += 1;
1 dummy clk cycle is modelled as 1 byte write (see the comment above), so 1
dummy byte (8 dummy clk cycles) will need +8 above.
seful here also:
} else {
qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %s"
(get_man(s) == MAN_SST) ? "AAI_WP with write protect" :
"Unknown CMD: 0xAD\n");
Lastly, [1] also says that the address shouldn't wrapp around when in AAI mode,
so we need a check before doing that also I think.
Best regards,
Francisco Iglesias
[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
> +}
> +break;
> default:
> s->pos = 0;
> s->len = 1;
> --
> 2.25.1
>
>
Hello Bin,
On [2020 Dec 04] Fri 15:52:12, Bin Meng wrote:
> Hi Francisco,
>
> On Thu, Dec 3, 2020 at 4:38 PM Francisco Iglesias
> wrote:
> >
> > Hi Bin and Alistair,
> >
> > On [2020 Dec 02] Wed 11:40:11, Alistair Francis wrote:
> > > On
Hello Bin,
On [2020 Dec 04] Fri 18:52:50, Bin Meng wrote:
> Hi Francisco,
>
> On Fri, Dec 4, 2020 at 6:46 PM Francisco Iglesias
> wrote:
> >
> > Hello Bin,
> >
> > On [2020 Dec 04] Fri 15:52:12, Bin Meng wrote:
> > > Hi Francisco,
> > >
&
Hello Bin,
On [2020 Dec 11] Fri 14:07:21, Bin Meng wrote:
> Hi Francisco,
>
> On Fri, Dec 4, 2020 at 7:28 PM Francisco Iglesias
> wrote:
> >
> > Hello Bin,
> >
> > On [2020 Dec 04] Fri 18:52:50, Bin Meng wrote:
> > > Hi Francisco,
> > >
&
Hello Bin,
On [2020 Dec 11] Fri 23:29:16, Bin Meng wrote:
> Hi Francisco,
>
> On Fri, Dec 11, 2020 at 11:16 PM Francisco Iglesias
> wrote:
> >
> > Hello Bin,
> >
> > On [2020 Dec 11] Fri 14:07:21, Bin Meng wrote:
> > > Hi Francisco,
> > >
&
Hi bin,
On [2020 Dec 12] Sat 16:16:59, Bin Meng wrote:
> Hi Francisco,
>
> On Sat, Dec 12, 2020 at 12:11 AM Francisco Iglesias
> wrote:
> >
> > Hello Bin,
> >
> > On [2020 Dec 11] Fri 23:29:16, Bin Meng wrote:
> > > Hi Francisco,
> > >
>
ands or when in QIO mode, and otherwise
> > > 8 for
> > > the currently supported fast read commands. [1]
> > >
> > > [1]
> > > https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_02g_cbb_0.pdf?
Hello Bin,
On [2020 Dec 12] Sat 17:44:27, Bin Meng wrote:
> Hi Francisco,
>
> On Sat, Dec 12, 2020 at 5:24 PM Francisco Iglesias
> wrote:
> >
> > Hi bin,
> >
> > On [2020 Dec 12] Sat 16:16:59, Bin Meng wrote:
> > > Hi Francisco,
> > >
>
qemu_log_mask(LOG_GUEST_ERROR,
> + "M25P80: AAI highest memory address reached");
> + s->write_enable = false;
> +s->aai_enable = false;
> +}
> +
> break;
>
> case ST
aborts.
> + */
> +qemu_log_mask(LOG_GUEST_ERROR,
> + "M25P80: AAI highest memory address reached");
Above message will be printed after writing the highest addressed byte but
before trying to write a byte after wrapping. Since it wouldn'
On [2020 Dec 22] Tue 14:45:19, Bin Meng wrote:
> From: Bin Meng
>
> When write is disabled, the write to flash should be avoided
> in flash_write8().
>
> Fixes: 82a2499011a7 ("m25p80: Initial implementation of SPI flash device")
> Signed-off-by: Bin Meng
Signed-off-by: Xuzhou Cheng
> Signed-off-by: Bin Meng
Reviewed-by: Francisco Iglesias
>
> ---
>
> Changes in v5:
> - remove the guest error logging when address wrap is detected in AAI
> - change to return s->aai_enable in m25p80_aai_enable_needed()
>
> Chang
byte from a txfifo on four lines (Quad command) it generates 2 dummy clock
cycles since it takes two cycles to transfer 8 bits).
Best regards,
Francisco Iglesias
> followed by fixes to 3 known SPI controller models that fall into
> the 2nd case above.
>
> Please note, I have no way t
Hi Bin,
On [2021 Jan 15] Fri 10:07:52, Bin Meng wrote:
> Hi Francisco,
>
> On Fri, Jan 15, 2021 at 2:13 AM Francisco Iglesias
> wrote:
> >
> > Hi Bin,
> >
> > On [2021 Jan 14] Thu 23:08:53, Bin Meng wrote:
> > > From: Bin Meng
> > >
>
Hi Bin,
On [2021 Jan 15] Fri 22:38:18, Bin Meng wrote:
> Hi Francisco,
>
> On Fri, Jan 15, 2021 at 8:26 PM Francisco Iglesias
> wrote:
> >
> > Hi Bin,
> >
> > On [2021 Jan 15] Fri 10:07:52, Bin Meng wrote:
> > > Hi Francisco,
> > >
&g
Hi Bin,
On [2021 Jan 18] Mon 20:32:19, Bin Meng wrote:
> Hi Francisco,
>
> On Mon, Jan 18, 2021 at 6:06 PM Francisco Iglesias
> wrote:
> >
> > Hi Bin,
> >
> > On [2021 Jan 15] Fri 22:38:18, Bin Meng wrote:
> > > Hi Francisco,
> > >
&g
This patch adds support to toggle the accuracy in m25p80 between dummy
clock cycle to dummy byte. By being able to do this the SPI controllers
transfering through a txfifo will be able to support commands with dummy
clock cycles.
Signed-off-by: Francisco Iglesias
---
hw/block/m25p80.c | 112
register)
the Xilinx ZynqMP GQSPI has been used and all works equally well as previously
with the controller.
Best regards,
Francisco Iglesias
Francisco Iglesias (3):
hw: ssi: Introduce ssi_txfifo_transfer
hw: block: m25p80: Support dummy byte accuracy
hw: ssi: xilinx_spi: Change to use
support for the commands requiring those.
Signed-off-by: Francisco Iglesias
---
hw/ssi/ssi.c | 22 ++
include/hw/ssi/ssi.h | 3 +++
2 files changed, 25 insertions(+)
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
index e5d7ce9523..b87628ea0c 100644
--- a/hw/ssi/ssi.c
+++ b
This patch changes the SPI controller to use the ssi_txfifo_transfer for
being able to support SPI flash commands requiring dummy clock cycles.
Signed-off-by: Francisco Iglesias
---
hw/ssi/xilinx_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ssi/xilinx_spi.c b/hw
Dear Bin,
On [2021 Jan 20] Wed 22:20:25, Bin Meng wrote:
> Hi Francisco,
>
> On Tue, Jan 19, 2021 at 9:01 PM Francisco Iglesias
> wrote:
> >
> > Hi Bin,
> >
> > On [2021 Jan 18] Mon 20:32:19, Bin Meng wrote:
> > > Hi Francisco,
> > >
&g
Dear Bin,
On [2021 Jan 21] Thu 16:59:51, Bin Meng wrote:
> Hi Francisco,
>
> On Thu, Jan 21, 2021 at 4:50 PM Francisco Iglesias
> wrote:
> >
> > Dear Bin,
> >
> > On [2021 Jan 20] Wed 22:20:25, Bin Meng wrote:
> > > Hi Francisco,
> > >
&g
y: Francisco Iglesias
Tested-by: Francisco Iglesias
Best regards,
Francisco Iglesias
> ---
>
> Changes for V2:
> Just skip update of spips cs and fifos
> Update commit message accordingly
> Changes for V4:
> Avoid checking for zynqmp qspi
> Skip spi
On [2020 Apr 04] Sat 14:27:18, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Fix descriptor loading from registers wrt host endianness.
>
> Reported-by: Peter Maydell
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
>
On [2020 Apr 04] Sat 14:27:17, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Fix descriptor loading from memory wrt host endianness.
>
> Reported-by: Peter Maydell
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
>
> last beat of a transfer.
>
> This adds an end-of-packet flag to the push interface.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> include/hw/stream.h | 5 +++--
> hw/core/stream.c| 4 ++--
> hw/dma/xilinx_axidm
On [2020 Apr 30] Thu 18:24:36, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add support for fragmented packets from the DMA.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> hw/net/xilinx_axienet.c | 31 ++
On Tue, May 12, 2020 at 01:15:50PM -0700, Vikram Garhwal wrote:
> Connect CAN0 and CAN1 on the ZynqMP.
>
> Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Vikram Garhwal
Reviewed-by: Francisco Iglesias
> ---
> hw/arm/xlnx-zynqmp.c | 26 ++
On Tue, May 12, 2020 at 01:15:52PM -0700, Vikram Garhwal wrote:
> Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Vikram Garhwal
Reviewed-by: Francisco Iglesias
> ---
> MAINTAINERS | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTA
MPCANState is in sleep mode. Any data on bus will bring it
> + * to wake up state.
> + */
> +can_exit_sleep_mode(s);
> +update_rx_fifo(s, frame);
> +} else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) == 0) {
> +update_rx
s[3], ZDMA_CH_DST_DSCR_WORD3,
> ^ ~~~
>
> Reported-by: Euler Robot
> Signed-off-by: Chen Qun
Reviewed-by: Francisco Iglesias
> ---
> Cc: Alistair Francis
> Cc: "Edgar E. Iglesias"
> Cc: Pete
On [2020 Feb 27] Thu 16:44:23, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add support for the Versal LPD ADMAs.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> hw/arm/xlnx-versal.c | 24
On [2020 Feb 27] Thu 16:44:24, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Generate xlnx-versal-virt zdma FDT nodes.
>
> Signed-off-by: Edgar E. Iglesias
Reviewed-by: Francisco Iglesias
> ---
> hw/arm/xlnx-versal-virt.c | 28 +++
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