Solicitation of paid services or employment is absolutely not
appropriate on the vger.kernel.org mailing lists.
Please do not do this ever again.
From: Jason Wang
Date: Wed, 28 Mar 2012 13:44:28 +0800
> As hypervior does not have the knowledge of guest network configuration, it's
> better to ask guest to send gratuitous packets when needed.
>
> Guest tests VIRTIO_NET_S_ANNOUNCE bit during config change interrupt and when
> it
> is set, a
From: David Woodhouse
Date: Sun, 01 Feb 2015 13:33:50 +
> Of course, now I'm looking closely at the path these packets take to
> leave the box, it starts to offend me that they're being passed up to
> userspace just to encrypt them (as DTLS or ESP) and then send them back
> down to the kernel
From: David Woodhouse
Date: Sun, 01 Feb 2015 21:29:43 +
> I really was looking for some way to push down something like an XFRM
> state into the tun device and just say "shove them out here until I tell
> you otherwise".
People decided to use TUN and push VPN stuff back into userspace,
and t
From: David Woodhouse
Date: Mon, 02 Feb 2015 07:27:10 +
> I'm guessing you don't want to push the *whole* management of the TLS
> control connection *and* the UDP transport, and probing the latter with
> keepalives, into the kernel? I certainly don't :)
Whilst Herbert Xu and I have discussed
From: ak...@redhat.com
Date: Sun, 20 Jan 2013 10:43:08 +0800
> From: Stefan Hajnoczi
>
> When we set mac address, software mac address in system and hardware mac
> address all need to be updated. Current eth_mac_addr() doesn't allow
> callers to implement error handling nicely.
>
> This patch s
From: Amos Kong
Date: Mon, 21 Jan 2013 19:17:20 +0800
> Currenly mac is programmed byte by byte. This means that we
> have an intermediate step where mac is wrong.
>
> Third patch introduced a new vq control command to set mac
> address, it's atomic.
>
> V2: check return of sending command, de
From: Rob Landley
Date: Sun, 21 Feb 2010 10:25:09 -0600
> 085219f79cad89291699bd2bfb21c9fdabafe65f is first bad commit
> commit 085219f79cad89291699bd2bfb21c9fdabafe65f
> Author: Sam Ravnborg
> Date: Fri Jan 2 18:47:34 2009 -0800
>
> sparc32: use proper types in struct stat
>
> L
Here's the fix I'll use, thanks for the report Rob:
sparc32: Fix struct stat uid/gid types.
Commit 085219f79cad89291699bd2bfb21c9fdabafe65f
("sparc32: use proper types in struct stat")
Accidently changed the struct stat uid/gid members
to uid_t and gid_t, but those get set to
__kernel_uid32_t a
From: Herbert Xu
Date: Wed, 14 Apr 2010 08:58:22 +0800
> On Tue, Apr 13, 2010 at 08:31:03PM +0200, Eric Dumazet wrote:
>>
>> Herbert Acked your patch, so I guess its OK, but I think it can be
>> dangerous.
>
> The tun socket accounting was never designed to stop it from
> flooding another tun in
From: David Ahern
Date: Sun, 1 Dec 2019 09:39:54 -0700
> Below you just drop the packet which is going to be a bad user
> experience. A better user experience is to detect XDP return codes a
> program uses, catch those that are not supported for this use case and
> fail the install of the program
From: "Michael S. Tsirkin"
Date: Sun, 1 Dec 2019 16:40:22 -0500
> Right. But it is helpful to expose the supported functionality
> to guest in some way, if nothing else then so that
> guests can be moved between different hosts.
>
> Also, we need a way to report this kind of event to guest
> so
s tested, both gcc and clang assemble multiple 'asm' statements
into a single block as long as there are no C statements between.
I'm happy to change it.
On Wed, Feb 23, 2022 at 2:45 PM Richard Henderson
wrote:
>
> On 2/17/22 13:17, David Miller wrote:
> > +#
> Bit 0 controls this, and recall that IBM uses big-bit numbering, so "8".
> This stores the low part of r[23] in the high part of r1.
> You need to select the high part of r[23].
good catch, these are both fixed will update patch shortly.
Thanks for the review
- David Mil
Yes I'm adding to this patch, I haven't quite figured out where to
put them, they are inline to various things in the patch themselves
so I'm putting in the cover letter under the patch they go to.
I hope that's correct.
Thanks
- David Miller
On Wed, Feb 23, 2022
TCG implements everything we need to run basic z15 OS+software
Signed-off-by: David Miller
---
hw/s390x/s390-virtio-ccw.c | 3 +++
target/s390x/cpu_models.c | 6 +++---
target/s390x/gen-features.c | 7 +--
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/s390x/s390
d patches into series.
David Miller (4):
s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3
for the s390x
* Reviewed-by: David Hildenbrand
s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z15 GA1
* Reviewed-by: David Hildenbrand
tests/tcg/s390x: Te
tests/tcg/s390x/mie3-compl.c: [N]*K instructions
tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
tests/tcg/s390x/mie3-sel.c: SELECT instruction
Signed-off-by: David Miller
---
tests/tcg/s390x/Makefile.target | 5 ++-
tests/tcg/s390x/mie3-compl.c| 55
HIGH (SELFHR)
MOVE RIGHT TO LEFT(MVCRL)
POPULATION COUNT (POPCNT)
Signed-off-by: David Miller
---
target/s390x/gen-features.c| 1 +
target/s390x/helper.h | 1 +
target/s390x/tcg/insn-data.def | 30 +++--
target/s390x/tcg/mem_helper.c | 20
Signed-off-by: David Miller
---
tests/tcg/s390x/mie3-compl.c | 21 +++--
tests/tcg/s390x/mie3-mvcrl.c | 2 +-
tests/tcg/s390x/mie3-sel.c | 6 +++---
3 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/tests/tcg/s390x/mie3-compl.c b/tests/tcg/s390x/mie3-compl.c
Had it on my TODO list for this morning, thank you.
On Mon, Feb 28, 2022 at 12:59 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 2/28/22 00:14, Thomas Huth wrote:
> > Full patch can be seen here:
> >
> > https://gitlab.com/thuth/qemu/-/commit/38af118ea2fef0c473
>
>
> > static in
>On 28/02/2022 19.31, David Miller wrote:
> > Had it on my TODO list for this morning, thank you.
> Thanks! Please send it as additional patch on top of my s390x-next, since
I
> already sent a pull request for the other patches yesterday:
>
> https://gitlab.com/thuth/qemu
Adds clobbers and merges remaining separate asm statements.
Signed-off-by: David Miller
---
tests/tcg/s390x/mie3-compl.c | 42 +++-
tests/tcg/s390x/mie3-mvcrl.c | 12 +++
tests/tcg/s390x/mie3-sel.c | 40 ++
3 files
Adds clobbers and merges remaining separate asm statements.
v1 -> v2:
* Corrected side in rebase conflict, removing older code.
Signed-off-by: David Miller
---
tests/tcg/s390x/mie3-compl.c | 18 +++-
tests/tcg/s390x/mie3-mvcrl.c | 12 +++
tests/tcg/s390x/mie3-sel.c |
Please disregard, v2 sent.
On Tue, Mar 1, 2022 at 2:15 PM David Miller wrote:
> Adds clobbers and merges remaining separate asm statements.
>
> Signed-off-by: David Miller
> ---
> tests/tcg/s390x/mie3-compl.c | 42 +++-
> tests/tcg/s390x
I used
#define Fi3(S, ASM) uint64_t S(uint64_t a, uint64_t b, uint64_t c) \
{ \
uint64_t res = 0; \
asm volatile ( \
"ltgr %[c], %[c]\n" \
ASM \
"stg %[c], %[res] " \
: [res] "=&r" (res) \
: [a] "r" (a), \
[b] "r"
However the constraint must be wrong there.
Sorry about split message.
On Tue, Mar 1, 2022 at 3:21 PM David Miller wrote:
> I used
>
>
> #define Fi3(S, ASM) uint64_t S(uint64_t a, uint64_t b, uint64_t c) \
> { \
> uint64_t res = 0;
Adds clobbers and merges remaining separate asm statements.
v2 -> v3:
* Removed all direct memory references in mie3-sel.c
v1 -> v2:
* Corrected side in rebase conflict, removing older code.
Signed-off-by: David Miller
---
tests/tcg/s390x/mie3-compl.c | 18 -
tests/tcg
Extend s390x z15 to support and test Vector Enhancements Facility 2 (vxeh2)
David Miller (2):
s390x/tcg: Implement Vector-Enhancements Facility 2 for s390x
tests/tcg/s390x: Tests for Vector Enhancements Facility 2
include/qemu/bitops.h| 26 ++
target/s390x/gen-features.c
(VCLFP)
VECTOR SHIFT LEFT (VSL)
VECTOR SHIFT RIGHT ARITHMETIC (VSRA)
VECTOR SHIFT RIGHT LOGICAL (VSRL)
Signed-off-by: David Miller
---
include/qemu/bitops.h| 26 ++
target/s390x/gen-features.c | 2 +-
target/s390x
tests/tcg/s390x/vxeh2_vcvt.c
tests/tcg/s390x/vxeh2_vs.c
tests/tcg/s390x/vxeh2_vlstr.c
Signed-off-by: David Miller
---
tests/tcg/s390x/Makefile.target | 8 ++
tests/tcg/s390x/vxeh2_vcvt.c| 97 +
tests/tcg/s390x/vxeh2_vlstr.c | 146
st kept with the
existing code flow.
Thanks
- David Miller
On Thu, Mar 3, 2022 at 3:58 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 3/2/22 17:22, David Miller wrote:
> > resolves: https://gitlab.com/qemu-project/qemu/-/issues/738
> >
> > implements:
Makes sense, thanks for the quick reply.
Last question, the patches can depend on others in the same set right?
IE: all of the additions to insn-data.def in one, implementations in
separate patches.
Thanks
- David Miller
On Thu, Mar 3, 2022 at 12:42 PM Richard Henderson <
richard.hen
TCG implements everything we need to run basic z15 OS+software.
Signed-off-by: David Miller
---
hw/s390x/s390-virtio-ccw.c | 3 +++
target/s390x/cpu_models.c | 6 +++---
target/s390x/gen-features.c | 7 +--
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/s390x/s390
Add partial support for s390x z15 ga1 and specific tests for minste3
v2 -> v3:
* Moved tests to separate patch.
* Combined patches into series.
David Miller (3):
s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3
for the s390x
s390x/cpumodel: Bump up QEMU model t
tests/tcg/s390x/mie3-compl.c: [N]*K instructions
tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
tests/tcg/s390x/mie3-sel.c: SELECT instruction
Signed-off-by: David Miller
---
tests/tcg/s390x/Makefile.target | 2 +-
tests/tcg/s390x/mie3-compl.c| 56
HIGH (SELFHR)
MOVE RIGHT TO LEFT(MVCRL)
POPULATION COUNT (POPCNT)
Signed-off-by: David Miller
---
target/s390x/gen-features.c| 1 +
target/s390x/helper.h | 1 +
target/s390x/tcg/insn-data.def | 30 --
target/s390x/tcg/mem_helper.c | 20
HIGH (SELFHR)
MOVE RIGHT TO LEFT(MVCRL)
POPULATION COUNT (POPCNT)
Signed-off-by: David Miller
---
target/s390x/gen-features.c| 1 +
target/s390x/helper.h | 1 +
target/s390x/tcg/insn-data.def | 30 +--
target/s390x/tcg/mem_helper.c | 20
TCG implements everything we need to run basic z15 OS+software
Signed-off-by: David Miller
---
hw/s390x/s390-virtio-ccw.c | 3 +++
target/s390x/cpu_models.c | 6 +++---
target/s390x/gen-features.c | 7 +--
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/s390x/s390
/tests/tcg/s390x/Makefile.target
new file: ../tests/tcg/s390x/mie3-compl.c
new file: ../tests/tcg/s390x/mie3-mvcrl.c
new file: ../tests/tcg/s390x/mie3-sel.c
On Wed, Feb 16, 2022 at 3:13 PM David Hildenbrand wrote:
>
> On 16.02.22 21:03, David Miller wrote:
>
tests/tcg/s390x/mie3-compl.c: [N]*K instructions
tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
tests/tcg/s390x/mie3-sel.c: SELECT instruction
Signed-off-by: David Miller
---
tests/tcg/s390x/Makefile.target | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tests/tcg
into series.
David Miller (3):
s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3
for the s390x
s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z15 GA1
tests/tcg/s390x: Tests for Miscellaneous-Instruction-Extensions
Facility 3
hw/s390x/s390-virtio-ccw
et
v2 -> v3:
* Moved tests to separate patch.
* Combined patches into series.
David Miller (3):
s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3
for the s390x
s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z15 GA1
tests/tcg/s390x: Tests for Miscellane
tests/tcg/s390x/mie3-compl.c: [N]*K instructions
tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
tests/tcg/s390x/mie3-sel.c: SELECT instruction
Signed-off-by: David Miller
---
tests/tcg/s390x/Makefile.target | 5 ++-
tests/tcg/s390x/mie3-compl.c| 55
HIGH (SELFHR)
MOVE RIGHT TO LEFT(MVCRL)
POPULATION COUNT (POPCNT)
Signed-off-by: David Miller
---
target/s390x/gen-features.c| 1 +
target/s390x/helper.h | 1 +
target/s390x/tcg/insn-data.def | 30 +--
target/s390x/tcg/mem_helper.c | 20
TCG implements everything we need to run basic z15 OS+software
Signed-off-by: David Miller
---
hw/s390x/s390-virtio-ccw.c | 3 +++
target/s390x/cpu_models.c | 6 +++---
target/s390x/gen-features.c | 7 +--
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/s390x/s390
Will submit patch later today, thanks
dundant code op_sel -> op_loc
* Cleanup for checkpatch.pl
* Readded mie3-* to Makefile.target
v2 -> v3:
* Moved tests to separate patch.
* Combined patches into series.
David Miller (4):
s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3
for the s390x
s390x/cpum
TCG implements everything we need to run basic z15 OS+software
Signed-off-by: David Miller
---
hw/s390x/s390-virtio-ccw.c | 3 +++
target/s390x/cpu_models.c | 6 +++---
target/s390x/gen-features.c | 7 +--
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/hw/s390x/s390
HIGH (SELFHR)
MOVE RIGHT TO LEFT(MVCRL)
POPULATION COUNT (POPCNT)
Signed-off-by: David Miller
---
target/s390x/gen-features.c| 1 +
target/s390x/helper.h | 1 +
target/s390x/tcg/insn-data.def | 30 +--
target/s390x/tcg/mem_helper.c | 20
tests/tcg/s390x/mie3-compl.c: [N]*K instructions
tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction
tests/tcg/s390x/mie3-sel.c: SELECT instruction
Signed-off-by: David Miller
---
tests/tcg/s390x/Makefile.target | 5 ++-
tests/tcg/s390x/mie3-compl.c| 55
Signed-off-by: David Miller
---
tests/tcg/s390x/mie3-compl.c | 21 +++--
tests/tcg/s390x/mie3-mvcrl.c | 2 +-
tests/tcg/s390x/mie3-sel.c | 6 +++---
3 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/tests/tcg/s390x/mie3-compl.c b/tests/tcg/s390x/mie3-compl.c
I'm playing catch up a bit here, as I was out sick for a few days.
It would be very much appreciated if you could do so, as I'm not
familiar with what is required.
Thanks
- David Miller
On Mon, Apr 25, 2022 at 3:51 AM David Hildenbrand wrote:
>
> On 25.04.22 09:43, Christian B
There was also the patch that had them as .insn in the other series of emails.
On Mon, May 2, 2022 at 11:52 AM David Hildenbrand wrote:
>
> On 02.05.22 09:20, Thomas Huth wrote:
> > On 28/04/2022 11.46, David Hildenbrand wrote:
> >> Implement Vector-Enhancements Facility 2 for s390x
> >>
> >> res
k the other solution works just as well by ignoring if compiler
doesn't support z15.
I just thought I'd bring it back up as I saw discussion about it.
Thanks
- David Miller
On Tue, May 3, 2022 at 2:55 AM Thomas Huth wrote:
>
> Hi!
>
> On 02/05/2022 18.06, David Miller wr
May 3, 2022 at 10:42 AM David Miller wrote:
>
> Sorry, It was in the discussion for v4 patches, as an attachment .
> mail thread:
> [PATCH v4 10/11] tests/tcg/s390x: Tests for Vector Enhancements Facility 2
> So it likely never made it to the mailing list.
>
> I've
>From bb6bf2f9529c4d76db9a9eff2ff7fa1235657103 Mon Sep 17 00:00:00 2001
From: David Miller
Date: Mon, 21 Mar 2022 16:58:57 -0400
Subject: [PATCH v5 10/11] tests/tcg/s390x: Tests for Vector Enhancements
Facility 2
Signed-off-by: David Miller
---
tests/tcg/s390x/Makefile.target | 8 ++
te
after and the tests
failed.
I'm submitting the split patches with whitespace fixes.
I hope it's not a dealbreaker, seeing as it matches the rest of the file
this way anyhow.
If it is, I will spend some more time looking into it tomorrow.
Thanks,
- David Miller
On Thu, Mar 3, 2022 at 1:0
(VCFPL)
VECTOR FP CONVERT TO FIXED (VCSFP)
VECTOR FP CONVERT TO LOGICAL(VCLFP)
VECTOR SHIFT LEFT (VSL)
VECTOR SHIFT RIGHT ARITHMETIC (VSRA)
VECTOR SHIFT RIGHT LOGICAL (VSRL)
David
Signed-off-by: David Miller
---
target/s390x/helper.h| 1 +
target/s390x/tcg/insn-data.def | 2 +
target/s390x/tcg/translate.c | 3 +-
target/s390x/tcg/translate_vx.c.inc | 17
target/s390x/tcg/vec_string_helper.c | 65
5
Signed-off-by: David Miller
---
target/s390x/helper.h | 4 +++
target/s390x/tcg/translate_vx.c.inc | 44 ++---
target/s390x/tcg/vec_fpu_helper.c | 31
3 files changed, 75 insertions(+), 4 deletions(-)
diff --git a/target/s390x
Signed-off-by: David Miller
---
include/qemu/bitops.h | 25 +++
target/s390x/helper.h | 3 +
target/s390x/tcg/insn-data.def | 6 +-
target/s390x/tcg/translate_vx.c.inc | 108 ++--
target/s390x/tcg/vec_int_helper.c | 58
Signed-off-by: David Miller
---
target/s390x/helper.h | 4 ++-
target/s390x/tcg/insn-data.def | 4 +++
target/s390x/tcg/translate_vx.c.inc | 39 +
target/s390x/tcg/vec.h | 24 ++
target/s390x/tcg/vec_helper.c
Signed-off-by: David Miller
---
target/s390x/gen-features.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c
index 22846121c4..499a3b10a8 100644
--- a/target/s390x/gen-features.c
+++ b/target/s390x/gen-features.c
@@ -740,7 +740,9
Signed-off-by: David Miller
---
target/s390x/tcg/insn-data.def | 16 +++
target/s390x/tcg/translate_vx.c.inc | 161
2 files changed, 177 insertions(+)
diff --git a/target/s390x/tcg/insn-data.def b/target/s390x/tcg/insn-data.def
index 3a7f15a0b5..dc6daa6c10
* tests/tcg/s390x/vxeh2_vcvt.c : vector convert
* tests/tcg/s390x/vxeh2_vs.c: vector shift
* tests/tcg/s390x/vxeh2_vlstr.c : vector load/store reversed
Signed-off-by: David Miller
---
tests/tcg/s390x/Makefile.target | 8 ++
tests/tcg/s390x/vxeh2_vcvt.c| 97
I've reviewed all changes, looks good.
Ran all of my own tests including vstrs, all passed.
Thank you for all reviews and changes here.
- David Miller
On Mon, Mar 7, 2022 at 8:54 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Hi David,
>
> I've split u
Is this waiting on me for anything?
I wanted to ensure this is wrapped up before starting a new project.
Thanks,
- David Miller
On Mon, Mar 7, 2022 at 11:09 PM David Miller wrote:
>
>
> I've reviewed all changes, looks good.
> Ran all of my own tests including vstrs, all pass
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
Reviewed-by: David Hildenbrand
---
target/s390x/helper.h | 4 +++
target/s390x/tcg/translate_vx.c.inc | 44 ++---
target/s390x/tcg/vec_fpu_helper.c | 31
3 files changed
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: David Miller
Reviewed-by: David Hildenbrand
---
target/s390x/tcg/vec_helper.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/s390x/tcg/vec_helper.c b/target/s390x/tcg/vec_helper.c
index ededf13cf0..48d86722b2
(VCFPL)
VECTOR FP CONVERT TO FIXED (VCSFP)
VECTOR FP CONVERT TO LOGICAL(VCLFP)
VECTOR SHIFT LEFT (VSL)
VECTOR SHIFT RIGHT ARITHMETIC (VSRA)
VECTOR SHIFT RIGHT LOGICAL (VSRL)
David
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
---
target/s390x/tcg/insn-data.def | 6 +++-
target/s390x/tcg/translate_vx.c.inc | 55 +
2 files changed, 53 insertions(+), 8 deletions(-)
diff --git a/target/s390x/tcg/insn-data.def b/target/s390x
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
---
target/s390x/helper.h | 3 ++
target/s390x/tcg/insn-data.def | 12 ++---
target/s390x/tcg/translate_vx.c.inc | 75 -
target/s390x/tcg/vec_int_helper.c | 55 +
4
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
---
target/s390x/helper.h| 6 ++
target/s390x/tcg/insn-data.def | 2 +
target/s390x/tcg/translate.c | 3 +-
target/s390x/tcg/translate_vx.c.inc | 25 +++
target/s390x/tcg/vec_string_helper.c | 99
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
Reviewed-by: David Hildenbrand
---
target/s390x/tcg/insn-data.def | 12
target/s390x/tcg/translate_vx.c.inc | 85 +
2 files changed, 97 insertions(+)
diff --git a/target/s390x/tcg/insn-data.def
From: Richard Henderson
Swap half-words (16-bit) and words (32-bit) within a larger value.
Mirrors functions of the same names within include/qemu/bitops.h.
Signed-off-by: Richard Henderson
Reviewed-by: David Miller
Reviewed-by: David Hildenbrand
---
include/tcg/tcg-op.h | 6 ++
tcg
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
---
target/s390x/tcg/insn-data.def | 4 +
target/s390x/tcg/translate_vx.c.inc | 115
2 files changed, 119 insertions(+)
diff --git a/target/s390x/tcg/insn-data.def b/target/s390x/tcg/insn-data.def
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
Reviewed-by: David Hildenbrand
---
target/s390x/tcg/insn-data.def | 4 ++
target/s390x/tcg/translate_vx.c.inc | 84 +
2 files changed, 88 insertions(+)
diff --git a/target/s390x/tcg/insn-data.def b
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
---
tests/tcg/s390x/Makefile.target | 8 ++
tests/tcg/s390x/vxeh2_vcvt.c| 97 +
tests/tcg/s390x/vxeh2_vlstr.c | 146
tests/tcg/s390x/vxeh2_vs.c | 91
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
---
target/s390x/gen-features.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c
index 22846121c4..499a3b10a8 100644
--- a/target/s390x/gen-features.c
+++ b/target/s390x
I came to much the same conclusion
On Tue, Mar 22, 2022 at 10:42 AM Richard Henderson
wrote:
>
> On 3/21/22 03:31, David Hildenbrand wrote:
> >> +for (i = 0; i < nelem; i++) {
> >> +if (s390_vec_read_element(v3, i, es) == 0) {
> >> +break;
> >> +}
>
Signed-off-by: David Miller
Reviewed-by: David Hildenbrand
Signed-off-by: Richard Henderson
---
target/s390x/helper.h | 4 +++
target/s390x/tcg/translate_vx.c.inc | 44 ++---
target/s390x/tcg/vec_fpu_helper.c | 31
3 files changed
From: Richard Henderson
Swap half-words (16-bit) and words (32-bit) within a larger value.
Mirrors functions of the same names within include/qemu/bitops.h.
Signed-off-by: Richard Henderson
Reviewed-by: David Miller
Reviewed-by: David Hildenbrand
---
include/tcg/tcg-op.h | 6 ++
tcg
(VCFPL)
VECTOR FP CONVERT TO FIXED (VCSFP)
VECTOR FP CONVERT TO LOGICAL(VCLFP)
VECTOR SHIFT LEFT (VSL)
VECTOR SHIFT RIGHT ARITHMETIC (VSRA)
VECTOR SHIFT RIGHT LOGICAL (VSRL)
David
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
Reviewed-by: David Hildenbrand
---
target/s390x/helper.h| 6 ++
target/s390x/tcg/insn-data.def | 2 +
target/s390x/tcg/translate.c | 3 +-
target/s390x/tcg/translate_vx.c.inc | 25 +++
target
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
Reviewed-by: David Hildenbrand
---
target/s390x/helper.h | 3 ++
target/s390x/tcg/insn-data.def | 12 ++---
target/s390x/tcg/translate_vx.c.inc | 75 -
target/s390x/tcg/vec_int_helper.c
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
Reviewed-by: David Hildenbrand
---
target/s390x/tcg/insn-data.def | 4 ++
target/s390x/tcg/translate_vx.c.inc | 84 +
2 files changed, 88 insertions(+)
diff --git a/target/s390x/tcg/insn-data.def b
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
Reviewed-by: David Hildenbrand
---
target/s390x/tcg/insn-data.def | 12
target/s390x/tcg/translate_vx.c.inc | 85 +
2 files changed, 97 insertions(+)
diff --git a/target/s390x/tcg/insn-data.def
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
---
target/s390x/gen-features.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/s390x/gen-features.c b/target/s390x/gen-features.c
index 22846121c4..499a3b10a8 100644
--- a/target/s390x/gen-features.c
+++ b/target/s390x
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
---
tests/tcg/s390x/Makefile.target | 8 ++
tests/tcg/s390x/vx.h| 19 +
tests/tcg/s390x/vxeh2_vcvt.c| 88
tests/tcg/s390x/vxeh2_vlstr.c | 139
tests/tcg
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
---
target/s390x/tcg/insn-data.def | 6 +++-
target/s390x/tcg/translate_vx.c.inc | 55 +
2 files changed, 53 insertions(+), 8 deletions(-)
diff --git a/target/s390x/tcg/insn-data.def b/target/s390x
From: Richard Henderson
Fixes: 0e0a5b49ad58 ("s390x/tcg: Implement VECTOR STORE WITH LENGTH")
Signed-off-by: Richard Henderson
Reviewed-by: David Miller
Reviewed-by: David Hildenbrand
---
target/s390x/tcg/vec_helper.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target
Signed-off-by: David Miller
Signed-off-by: Richard Henderson
Reviewed-by: David Hildenbrand
---
target/s390x/tcg/insn-data.def | 4 +
target/s390x/tcg/translate_vx.c.inc | 113
2 files changed, 117 insertions(+)
diff --git a/target/s390x/tcg/insn-data.def b
I am sending v5 now as I'm away from my desk until Sunday.
As I'm unsure whether or not this just needs a V7_0 and the patch
shown as an example isn't a direct correlation : I've left it out for
now.
I will dig into it further Monday March 28th.
Thanks
- David Miller
On Wed,
Sorry,
Didn't notice this, as it was on v4 patch emails.
I assume since there is no other follow up after a week,
CI jobs are not being updated and I should change samples to use .insn.
I will try to get this out tomorrow.
Thanks,
- David Miller
On Wed, Mar 23, 2022 at 1:13 PM Thomas
insn vrr, 0xE786, %[v1], %[v2], %[v3], 0, %[I], 0\n"
: [v1] "=v" (v1->v)
: [v2] "v" (v2->v)
, [v3] "v" (v3->v)
, [I] "i" (I & 7));
Patch is attached
Thanks
- David Mil
On Thu, Mar 31, 2022 at 10:15 PM David Miller wrote:
>
> Hi,
>
> There is some issue with instruction sub/alt encodings not matching,
> but I worked around it easily.
>
> I'm dropping the updated patch for the tests in here.
> I know I should resend the entire pat
aeger
wrote:
>
>
>
> Am 01.04.22 um 04:15 schrieb David Miller:
> > Hi,
> >
> > There is some issue with instruction sub/alt encodings not matching,
> > but I worked around it easily.
> >
> > I'm dropping the updated patch for the tests in here.
>
David Hildenbrand wrote:
>
> On 01.04.22 17:25, Christian Borntraeger wrote:
> > Am 01.04.22 um 17:02 schrieb David Miller:
> >> vrr is almost a perfect match (it is for this, larger than imm4 would
> >> need to be split).
> >>
> >> .long : this wo
From: Russell King - ARM Linux
Date: Fri, 11 Nov 2016 22:33:08 +
> "The new buffer management algorithm provides capabilities of Microsoft
> Large-Send offload" and as yet I haven't found anything that describes
> what this is or how it works.
For once I will give Microsoft a big shout out h
1 - 100 of 105 matches
Mail list logo
