(!vq->event || (uint16_t)(idx-avail_event) < 1)) {
d->bus->virtqueue_kick(d, vq);
}
As a result the virtqueue is never kicked and we'll timeout waiting for it.
Fixes: 1053587c3f ("libqos: Added EVENT_IDX support")
Signed-off-by: Daniel Henrique Barboza
, TCG logic - }
}
into:
if (virt_aclint_allowed() && s->have_aclint) {
- aclint logic -
} else if (tcg_enabled()) {
- non-aclint, TCG logic -
}
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/virt.c | 52 +
1 file changed, 27 insertio
o in the past, figured you have some expertise to share
here.
Patches based on master.
Daniel Henrique Barboza (6):
libqos/virtio.c: init all elems in qvring_indirect_desc_setup()
libqos/virtio.c: fix 'avail_event' offset in qvring_init()
hw/riscv/virt.c: create '/soc/pci
e8 ("tests/qtest: properly initialise the vring used idx") fixed a
similar problem stating "It is probably not wise to assume guest memory
is zeroed anyway". I concur.
Initialize all elems in qvring_indirect_desc_setup().
Fixes: f294b029aa ("libqos: Added indirect descriptor
We want to add a RISC-V 'virt' libqos machine to increase our test
coverage. Some of the tests will try to plug a virtio-iommu-pci
device into the board and do some tests with it.
Enable virtio-iommu-pci in the 'virt' machine.
Signed-off-by: Daniel Henrique Barboza
---
ke ecam and pio_base addresses, so we'll add an extra step to
set its parameters after creating it.
Our command line is incremented with 'aclint' parameters to allow the
machine to run MSI tests.
Signed-off-by: Daniel Henrique Barboza
---
tests/qtest/libqos/meson.build |
Hotplugged FDT nodes will attempt to write this node that, at this
moment, is being created only in create_fdt_pcie() during
finalize_fdt().
Create it earlier.
Signed-off-by: Daniel Henrique Barboza
---
hw/riscv/virt.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a
On 2/7/24 08:59, Christoph Müllner wrote:
Upstream Linux recently added many additional keys to the hwprobe API.
This patch adds support for all of them with the exception of Ztso,
which is currently not supported in QEMU.
Signed-off-by: Christoph Müllner
---
Reviewed-by: Daniel Henrique
On 2/7/24 08:59, Christoph Müllner wrote:
Upstream Linux recently added RISC-V Zicboz support to the hwprobe API.
This patch introduces this for QEMU's user space emulator.
Signed-off-by: Christoph Müllner
---
Reviewed-by: Daniel Henrique Barboza
linux-user/syscall.c | 3 +++
1
On 2/7/24 09:22, Christoph Müllner wrote:
This patch exposes Ztso via hwprobe in QEMU's user space emulator.
Signed-off-by: Christoph Müllner
---
Reviewed-by: Daniel Henrique Barboza
linux-user/syscall.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/syscal
On 2/7/24 09:22, Christoph Müllner wrote:
The first patch of this series picks up an earlier v2 Ztso patch from Palmer,
which can be found here:
https://patchwork.kernel.org/project/qemu-devel/patch/20220917072635.11616-1-pal...@rivosinc.com/
This patch did not apply cleanly but the necess
dt, name, "interrupts", IOPMP_IRQ, 0x4);
+}
+}
+
+static void create_fdt_iopmp2(RISCVVirtState *s, const MemMapEntry *memmap,
+ uint32_t irq_mmio_phandle) {
+g_autofree char *name;
I believe we need to always initialize g_autofree variables. Please i
On 2/14/24 10:38, Christoph Müllner wrote:
On Wed, Feb 14, 2024 at 2:35 PM Daniel Henrique Barboza
wrote:
On 2/7/24 09:22, Christoph Müllner wrote:
The first patch of this series picks up an earlier v2 Ztso patch from Palmer,
which can be found here:
https://patchwork.kernel.org
On 2/7/24 06:34, Ethan Chen wrote:
Support specification Version 1.0.0-draft4 rapid-k model.
The specification url:
https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf
The memory transaction from source devices connected to IOPMP will be
checked by IOPMP rule.
On 2/15/24 06:53, Christoph Müllner wrote:
On Wed, Feb 14, 2024 at 5:25 PM Andrew Jones wrote:
On Wed, Feb 14, 2024 at 02:38:34PM +0100, Christoph Müllner wrote:
On Wed, Feb 14, 2024 at 2:35 PM Daniel Henrique Barboza
wrote:
On 2/7/24 09:22, Christoph Müllner wrote:
The first patch
On 2/15/24 10:33, Conor Dooley wrote:
On Fri, Feb 02, 2024 at 12:21:51PM -0300, Daniel Henrique Barboza wrote:
The RVA22U64 and RVA22S64 profiles mandates certain extensions that,
until now, we were implying that they were available.
We can't do this anymore since named features also
On 2/15/24 16:28, Max Chou wrote:
If there are not any QEMU plugin memory callback functions, checking
before calling the qemu_plugin_vcpu_mem_cb function can reduce the
function call overhead.
Signed-off-by: Max Chou
---
This was in my TODO list for some time. Thanks for looking it up.
C
On 2/15/24 16:28, Max Chou wrote:
In the vector unit-stride load/store helper functions. the vext_ldst_us
function corresponding most of the execution time. Inline the functions
can avoid the function call overhead to imperove the helper function
performance.
Signed-off-by: Max Chou
---
Th
On 2/15/24 06:52, Alistair Francis wrote:
On Sat, Feb 3, 2024 at 1:23 AM Daniel Henrique Barboza
wrote:
Hi,
In this new version we changed patch 3 as suggested by Alistair in v1
[1]. Instead of creating individual always-true bool for each named
feature, create a bool flag will be always
7;rva22s64' CPU:
# cat /proc/device-tree/cpus/cpu@0/riscv,isa
rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_
zicntr_zicsr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zca_zcd_zba_zbb_
zbs_zkt_ssccptr_sscounterenw_sstvala_sstvecd_svade_svinval_svpbmt#
Signed-off-by: Daniel Henrique Barboza
R
("target/riscv: Add *envcfg.HADE related check in address
translation")
Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension")
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Andrew Jones
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 3
7;mmu' in this case.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/tcg/tcg-cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index dd5228c288..ee4c349972 100644
--- a/target/riscv/tcg/tc
d
priv_spec versions;
- skip name feature check in cpu_bump_multi_ext_priv_ver(). Now that
named features have a riscv,isa and an entry in isa_edata_arr[] we
don't need to gate the call to cpu_cfg_ext_get_min_version() anymore.
[1] https://github.com/riscv/riscv-profiles/issues/121
[2] ht
ch to hardware updating
(this behavior change fixes [2])
Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address
translation") [1]
Fixes: 48531f5adb2a ("target/riscv: implement svade") [2]
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Andrew
Jones (3):
target/riscv: Reset henvcfg to zero
target/riscv: Gate hardware A/D PTE bit updating
target/riscv: Promote svade to a normal extension
Daniel Henrique Barboza (3):
target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()
target/riscv: add riscv,i
for the max
cpu type, since QEMU has always implemented hardware A/D PTE bit
updating, so users must opt into svade (or get it from a CPU type
which enables it by default).
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Andrew Jones
Reviewed-by: Alistair Francis
---
target/riscv/cp
fb57 ("target/riscv: rvv-1.0: add translation-time vector context
status")
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rv
is zeroed and
set vstart_eq_zero accordingly.
Patches based on alistair/riscv-to-apply.next. It can also be fetched
here:
https://gitlab.com/danielhb/qemu/-/tree/vstart_bug1976_v1
Daniel Henrique Barboza (3):
trans_rvv.c.inc: write CSRs must call mark_vs_dirty() too
trans_rvv.c.inc: remove
place to update 'vstart_eq_zero'.
Fixes: 8e1ee1fb57 ("target/riscv: rvv-1.0: add translation-time vector context
status")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/translate.c | 22 ++
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/
On 2/16/24 03:13, Alvin Chang wrote:
The RISC-V debug specification defines an optional CSR "tcontrol" within
the trigger module. This commit adds its read/write operations and
related bit-field definitions.
Signed-off-by: Alvin Chang
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_b
into
riscv_cpu_do_interrupt().
Signed-off-by: Alvin Chang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu_helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d462d95ee1..037ae21062 100644
--- a/target/riscv
On 2/16/24 03:13, Alvin Chang wrote:
When the trigger module resets, reset the value of CSR tcontrol as zero.
Signed-off-by: Alvin Chang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/debug.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/debug.c b/target
ug mailing list:
https://lists.riscv.org/g/tech-debug/topic/102702615#1461
The debug specification does not mention the operation to tcontrol.MPTE
when "mret" is executed. Therefore, we just keep its current value.
Signed-off-by: Alvin Chang
---
Reviewed-by: Daniel Henrique Barbo
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/
place to update 'vstart_eq_zero'.
Fixes: 8e1ee1fb57 ("target/riscv: rvv-1.0: add translation-time vector context
status")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/translate.c | 20
ernel.org/qemu-riscv/20240216112806.997948-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (3):
trans_rvv.c.inc: write CSRs must call mark_vs_dirty() too
trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
target/riscv/translate.c: set vstart_eq_zero in mark_vs_dirt
fb57 ("target/riscv: rvv-1.0: add translation-time vector context
status")
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rv
Hi,
Please disregard this version. I just posted a v2 after feedback from people
in Gitlab.
Thanks,
Daniel
On 2/16/24 08:28, Daniel Henrique Barboza wrote:
Hi,
This is my shot to fix https://gitlab.com/qemu-project/qemu/-/issues/1976.
First patch ensures that every vector instruction that
On 2/16/24 10:42, Alvin Che-Chia Chang(張哲嘉) wrote:
Hi Daniel,
-Original Message-
From: Daniel Henrique Barboza
Sent: Friday, February 16, 2024 8:51 PM
To: Alvin Che-Chia Chang(張哲嘉) ;
qemu-ri...@nongnu.org; qemu-devel@nongnu.org
Cc: alistair.fran...@wdc.com; bin.m...@windriver.com
On 2/16/24 03:13, Alvin Chang wrote:
The RISC-V debug specification defines an optional CSR "tcontrol" within
the trigger module. This commit adds its read/write operations and
related bit-field definitions.
Signed-off-by: Alvin Chang
---
Reviewed-by: Daniel Henrique Barboza
On 2/16/24 15:56, Richard Henderson wrote:
On 2/16/24 03:57, Daniel Henrique Barboza wrote:
The 'vstart_eq_zero' flag which is used to determine if some insns, like
vector reductor operations, should SIGILL. At this moment the flag is
being updated only during cpu_get_tb_cpu_state
On 2/16/24 20:41, Richard Henderson wrote:
On 2/16/24 12:40, Daniel Henrique Barboza wrote:
After reading the reviews of patches 1 and 3 what I'm considering here is:
1 - drop patch 1;
Ok.
2 - there's a patch from Ivan Klokov sent 2 months ago:
"[PATCH 1/1] targ
Richard,
On 12/14/23 08:18, Ivan Klokov wrote:
The vstart_qe_zero flag is set at the beginning of the translation
phase from the env->vstart variable. During the execution phase, some
instructions may change env->vstart, but the flag remains the same as
at the start of the block. With some comb
-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (6):
libqos/virtio.c: init all elems in qvring_indirect_desc_setup()
libqos/virtio.c: fix 'avail_event' offset in qvring_init()
hw/riscv/virt.c: create '/soc/pci@...' fdt node earlier
hw/riscv/virt.c: add virtio-iommu
, TCG logic - }
}
into:
if (virt_aclint_allowed() && s->have_aclint) {
- aclint logic -
} else if (tcg_enabled()) {
- non-aclint, TCG logic -
}
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 52 +-
e8 ("tests/qtest: properly initialise the vring used idx") fixed a
similar problem stating "It is probably not wise to assume guest memory
is zeroed anyway". I concur.
Initialize all elems in qvring_indirect_desc_setup().
Fixes: f294b029aa ("libqos: Added indirect
(!vq->event || (uint16_t)(idx-avail_event) < 1)) {
d->bus->virtqueue_kick(d, vq);
}
As a result the virtqueue is never kicked and we'll timeout waiting for it.
Fixes: 1053587c3f ("libqos: Added EVENT_IDX support")
Signed-off-by: Daniel Henrique Barboza
Rev
Hotplugged FDT nodes will attempt to write this node that, at this
moment, is being created only in create_fdt_pcie() during
finalize_fdt().
Create it earlier.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 9 -
1 file changed, 8 insertions
ke ecam and pio_base addresses, so we'll add an extra step to
set its parameters after creating it.
Our command line is incremented with 'aclint' parameters to allow the
machine to run MSI tests.
Signed-off-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Acked-by: T
We want to add a RISC-V 'virt' libqos machine to increase our test
coverage. Some of the tests will try to plug a virtio-iommu-pci
device into the board and do some tests with it.
Enable virtio-iommu-pci in the 'virt' machine.
Signed-off-by: Daniel Henrique Barboza
Acked-
On 2/20/24 08:08, frank.ch...@sifive.com wrote:
From: Frank Chang
Add missing include guard in pmu.h to avoid the problem of double
inclusion.
Signed-off-by: Frank Chang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/pmu.h | 5 +
1 file changed, 5 insertions(+)
diff
start = 0
every time.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 116 ---
target/riscv/insn_trans/trans_rvvk.c.inc | 18
2 files changed, 134 deletions(-)
diff --git a/target/riscv/insn_tran
ctx->vstart_eq_zero = true instead;
- finalize_rvv_inst() is removed from the #ifdef block since it's now
relevant to linux-user
- v2 link:
https://lore.kernel.org/qemu-riscv/20240216135719.1034289-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (4):
trans_rvv.c.inc: mark_
l.org/qemu-riscv/72c7503b-0f43-44b8-aa82-fbafed2aa...@linaro.org/
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 29 +++--
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn_t
s this
causes an illegal instruction exception. This patch simultaneously
updates flag and env->vstart and to avoid inconsistency.
Signed-off-by: Ivan Klokov
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 6 +-
target/riscv/insn_trans/trans_rvv.c.in
The helper isn't setting env->vstart = 0 after its execution, as it is
expected from every vector instruction that completes successfully.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/vector_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/vector_he
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/
On 2/20/24 17:17, Richard Henderson wrote:
On 2/20/24 09:26, Daniel Henrique Barboza wrote:
While discussing a problem with how we're (not) setting vstart_eq_zero
Richard had the following to say w.r.t the conditional mark_vs_dirty()
calls on load/store functions [1]:
"I think it&
to save vector
state on task switch."
Do a mark_vs_dirty() before both loads and stores.
[1]
https://lore.kernel.org/qemu-riscv/72c7503b-0f43-44b8-aa82-fbafed2aa...@linaro.org/
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_t
After the 'mark_vs_dirty' changes from the previous patch the 'is_store'
bool is unused in all load/store functions that were changed. Remove it.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 69 -
1 file ch
anges from v3:
- patch 1: do mark_vs_dirty() for both loads and stores
- patch 2 (new): remove the now unused 'is_store' arg from load/store
functions
- v3 link:
https://lore.kernel.org/qemu-riscv/20240220192607.141880-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (5
start = 0
every time.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvv.c.inc | 117 ---
target/riscv/insn_trans/trans_rvvk.c.inc | 18
2 files changed, 135 deletions(-)
diff --git
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard
The helper isn't setting env->vstart = 0 after its execution, as it is
expected from every vector instruction that completes successfully.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 1 +
1 file changed, 1 insertion(+)
diff
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976
Signed-off-by: Ivan Klokov
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 6 +-
target/riscv/insn_trans/trans_rvv.c.inc| 78 --
target/riscv/i
r/riscv-to-apply.next.
Patches missing acks: patch 4.
Changes from v4:
- patch 3:
- remove vstart >= vl and vl = 0 brconds from trans_fvbf16.c.inc
- patch 4 (new):
- remove cpu_vstart
- v4 link:
https://lore.kernel.org/qemu-riscv/20240220222510.209448-1-dbarb...@ventanamicro.com/
Daniel Henriq
to save vector
state on task switch."
Do a mark_vs_dirty() before both loads and stores.
[1]
https://lore.kernel.org/qemu-riscv/72c7503b-0f43-44b8-aa82-fbafed2aa...@linaro.org/
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_t
t = 0
every time.
While we're at it, remove the (vl == 0) brconds from trans_rvbf16.c.inc
too since they're unneeded.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 12
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976
Signed-off-by: Ivan Klokov
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 6 +-
target/riscv/insn_trans/trans_rvv.c.inc| 78 --
target/riscv/i
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard
After the 'mark_vs_dirty' changes from the previous patch the 'is_store'
bool is unused in all load/store functions that were changed. Remove it.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 69 -
1 file ch
The global is unused after recent changes.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 177418b2b9..f2f0593830 100644
--- a/target/riscv
The helper isn't setting env->vstart = 0 after its execution, as it is
expected from every vector instruction that completes successfully.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 1 +
1 file changed, 1 insertion(+)
diff
Hi Atish,
This series and its dependency, which I assume it's
"[PATCH v4 0/5] Add ISA extension smcntrpmf support"
Doesn't apply in neither master nor riscv-to-apply.next because of this patch:
"target/riscv: Use RISCVException as return type for all csr ops"
That changed some functions from
On 2/19/24 00:25, Alvin Chang wrote:
According to RISC-V Debug specification, there are several common
matching conditions before firing a trigger, including the enabled
privilege levels of the trigger.
This commit adds trigger_common_match() to prepare the common matching
conditions for the
On 2/19/24 00:25, Alvin Chang wrote:
We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level.
Remove the related code in riscv_cpu_debug_check_breakpoint() and invoke
trigger_common_match() to check the privile
On 2/19/24 00:25, Alvin Chang wrote:
We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level.
Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke
trigger_common_match() to check the privile
On 2/19/24 00:25, Alvin Chang wrote:
We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level. We
can invoke trigger_common_match() to check the privilege levels of the
type 3 triggers.
Signed-off-by: Alvin Cha
On 2/21/24 14:06, Atish Kumar Patra wrote:
On Wed, Feb 21, 2024 at 6:58 AM Daniel Henrique Barboza mailto:dbarb...@ventanamicro.com>> wrote:
Hi Atish,
This series and its dependency, which I assume it's
"[PATCH v4 0/5] Add ISA extension smcntrpmf support&quo
On 2/21/24 17:17, Atish Patra wrote:
On 2/21/24 10:26, Daniel Henrique Barboza wrote:
On 2/21/24 14:06, Atish Kumar Patra wrote:
On Wed, Feb 21, 2024 at 6:58 AM Daniel Henrique Barboza mailto:dbarb...@ventanamicro.com>> wrote:
Hi Atish,
This series and its dependency, w
Richard,
On 2/20/24 23:22, Daniel Henrique Barboza wrote:
Hi,
In this new version we removed the remaining brconds() from
trans_rvbf16.c.inc like Richard suggested in patch 3. Richard, I kept
your ack in that patch.
This change caused the 'cpu_vstart' global to be unused. A new pat
to save vector
state on task switch."
Do a mark_vs_dirty() before both loads and stores.
[1]
https://lore.kernel.org/qemu-riscv/72c7503b-0f43-44b8-aa82-fbafed2aa...@linaro.org/
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
t = 0
every time.
While we're at it, remove the (vl == 0) brconds from trans_rvbf16.c.inc
too since they're unneeded.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 12
move 'cpu_vl' global
- patch 9 (new): change the loop in ldst helpers
- v5 link:
https://lore.kernel.org/qemu-riscv/20240221022252.252872-1-dbarb...@ventanamicro.com/
Daniel Henrique Barboza (8):
trans_rvv.c.inc: mark_vs_dirty() before loads and stores
trans_rvv.c.inc: remove 'is_stor
Change the for loops in ldst helpers to do a single increment in the
counter, and assign it env->vstart, to avoid re-reading from vstart
every time.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/vector_helper.c | 6 +++---
1 file changed, 3 inserti
The global is unused after recent changes.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 177418b2b9..f2f0593830
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard
The helper isn't setting env->vstart = 0 after its execution, as it is
expected from every vector instruction that completes successfully.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/vector_helper.c | 1 +
1 file changed, 1 insertion(+)
diff
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976
Signed-off-by: Ivan Klokov
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 6 +-
target/riscv/insn_trans/trans_rvv.c.inc| 78 --
target/riscv/i
At this moment the global is used only in do_vsetvl(). Do a direct env
load in do_vsetvl() to read 'vl' and remove the global.
Suggested-by: Richard Henderson
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
target/riscv/translate.c
After the 'mark_vs_dirty' changes from the previous patch the 'is_store'
bool is unused in all load/store functions that were changed. Remove it.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
tar
On 2/21/24 22:46, Alvin Che-Chia Chang(張哲嘉) wrote:
Hi Daniel,
-Original Message-
From: Daniel Henrique Barboza
Sent: Thursday, February 22, 2024 1:26 AM
To: Alvin Che-Chia Chang(張哲嘉) ;
qemu-ri...@nongnu.org; qemu-devel@nongnu.org
Cc: alistair.fran...@wdc.com; bin.m...@windriver.com
On 2/24/24 10:02, demin.han wrote:
The result of (8 - 3 - vlmul) is negtive when vlmul >= 6,
and results in wrong vill.
Signed-off-by: demin.han
---
target/riscv/vector_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/ris
On 2/25/24 00:27, demin.han wrote:
The result of (8 - 3 - vlmul) is negtive when vlmul >= 6,
and results in wrong vill.
Signed-off-by: demin.han
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/vector_helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
d
On 2/25/24 14:41, demin.han wrote:
The result of (8 - 3 - vlmul) is negative when vlmul >= 6,
and results in wrong vill.
Signed-off-by: demin.han
---
Reviewed-by: Daniel Henrique Barboza
Changes in v2:
- Add vlen var
Changes in v3:
- Fix commit msg typo
target/riscv/vector_helpe
Hey Phil,
This patch is giving me a conflict in target/riscv/cpu_helper.c when applying
on top of master. Not sure if I'm missing any dependency.
It's a trivial conflict though, just a FYI. As for the patch:
Reviewed-by: Daniel Henrique Barboza
On 1/29/24 13:45, Philippe Mathieu-D
On 1/30/24 08:09, LIU Zhiwei wrote:
vxrm and vxsat have been moved into a special register vcsr since
RVV v1.0. So remove them from FCSR for vector 1.0.
Signed-off-by: LIU Zhiwei
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu_bits.h | 8
1 file changed, 8
o the vlen->vlenb changes that
got merged recently in riscv-to-apply.next.
As for the patch:
Reviewed-by: Daniel Henrique Barboza
target/riscv/csr.c | 117 -
1 file changed, 74 insertions(+), 43 deletions(-)
diff --git a/target/riscv/csr.c
On 1/29/24 22:10, Alistair Francis wrote:
On Fri, Jan 26, 2024 at 5:54 AM Daniel Henrique Barboza
wrote:
The RVA22U64 and RVA22S64 profiles mandates certain extensions that,
until now, we were implying that they were available.
We can't do this anymore since named features also
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