In the Vector spec section 3.2 [1]: "When mstatus.VS is set to Initial or Clean, executing any instruction that changes vector state, including the vector CSRs, will change mstatus.VS to Dirty."
ldst_us_trans(), ldst_stride_trans(), ldst_index_trans() and ldst_whole_trans() will change vector state regardless of being a store op or not. Stores will set env->vstart to zero after execution (see vext_ldst_us() in vector_helper.c), and this is vector CSR state change. [1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-start-index-csr-vstart Fixes: 8e1ee1fb57 ("target/riscv: rvv-1.0: add translation-time vector context status") Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> --- target/riscv/insn_trans/trans_rvv.c.inc | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 9e101ab434..044c9c903e 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -638,10 +638,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, fn(dest, mask, base, tcg_env, desc); - if (!is_store) { - mark_vs_dirty(s); - } - + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -799,10 +796,7 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, fn(dest, mask, base, stride, tcg_env, desc); - if (!is_store) { - mark_vs_dirty(s); - } - + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -906,10 +900,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, fn(dest, mask, base, index, tcg_env, desc); - if (!is_store) { - mark_vs_dirty(s); - } - + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1104,9 +1095,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf, fn(dest, base, tcg_env, desc); - if (!is_store) { - mark_vs_dirty(s); - } + mark_vs_dirty(s); gen_set_label(over); return true; -- 2.43.0
