On 2/15/24 06:52, Alistair Francis wrote:
On Sat, Feb 3, 2024 at 1:23 AM Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
Hi,
In this new version we changed patch 3 as suggested by Alistair in v1
[1]. Instead of creating individual always-true bool for each named
feature, create a bool flag will be always 'true' to be used as config
offset for these named extensions.
Patches based on riscv-to-apply.next.
Patches missing acks: patch 3.
Changes from v2:
- patch 3:
- 'ext_always_enabled' bool added
- individual always-enabled named features bools removed
- v2 link:
https://lore.kernel.org/qemu-riscv/20240126133101.61344-8-ajo...@ventanamicro.com/
[1]
https://lore.kernel.org/qemu-riscv/20240125195319.329181-1-dbarb...@ventanamicro.com/
Andrew Jones (3):
target/riscv: Reset henvcfg to zero
target/riscv: Gate hardware A/D PTE bit updating
target/riscv: Promote svade to a normal extension
Daniel Henrique Barboza (3):
target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile()
target/riscv: add riscv,isa to named features
target/riscv: add remaining named features
Do you mind rebasing? I feel bad always asking, but I think it's your
patches that cause the conflicts :P
:)
I'll re-send based on current riscv-to-apply.next. Thanks,
Daniel
Alistair
target/riscv/cpu.c | 70 +++++++++++++++++++++++++++-----------
target/riscv/cpu_cfg.h | 12 +++++--
target/riscv/cpu_helper.c | 19 ++++++++---
target/riscv/csr.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 34 +++++++++---------
5 files changed, 94 insertions(+), 43 deletions(-)
--
2.43.0
