Hello,
there was a proposed patch by Paolo Bonzini some time ago about adding an
option to qemu to disable tcg:
https://lists.gnu.org/archive/html/qemu-devel/2012-09/msg02568.html
Is there some plan to integrate it?
Paolo, do you have a newer version that applies cleanly to mainline?
Thanks,
most painful, and then I still need the
tcg_target_init and the prologue.
Is anybody else working on this?
Ciao,
Claudio
--
Claudio Fontana
Hi, resuming this conversation about external objdump,
On 10.08.2013 21:47, Richard Henderson wrote:
> On 08/10/2013 06:53 AM, Max Filippov wrote:
>> On Sat, Aug 10, 2013 at 8:42 PM, Richard Henderson wrote:
>>> On 08/10/2013 05:45 AM, Peter Maydell wrote:
Well, it depends. If we're going to
88
# bad: [9b8c69243585a32d14b9bb9fcd52c37b0b5a1b71] memory: Return -1 again on
reads from unsigned regions
git bisect bad 9b8c69243585a32d14b9bb9fcd52c37b0b5a1b71
# good: [b4afea11aafe85975e74dd562bb94f7ce3de1ef1] memory: actually set the
owner
git bisect good b4afea11aafe85975e74dd562bb94f7c
Hi Peter,
On 05.09.2013 10:59, Peter Maydell wrote:
> On 5 September 2013 09:31, Claudio Fontana wrote:
>
>> I just finished bisecting a regression I am experiencing on ARM 32bit target,
>
>> After a painful bisection, I got a first bad commit, which when reverted on
>
As I mentioned before, I just have one nit with this,
functionally it is fine (and I tested it with multiple targets, so you can add
my
Tested-by: Claudio Fontana
I describe my nit below:
On 22.09.2014 22:57, Richard Henderson wrote:
> The "old" qemu_ld opcode did not specify th
On 24.09.2014 17:19, Richard Henderson wrote:
> On 09/24/2014 01:20 AM, Claudio Fontana wrote:
>>> @@ -1118,7 +1119,8 @@ static void tcg_out_qemu_ld_direct(TCGContext *s,
>>> TCGMemOp memop,
>>> tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, off_r);
>>&
On 25 September 2014 19:15, Peter Maydell wrote:
> On 16 September 2014 10:31, Claudio Fontana wrote:
>> This is obviously wrong, we have to put a \0 to separate the two options.
>>
>> But thee question remains, should we mark that as arm,armv8-timer compatible?
>
>
This patch fixes my issue with page tables switching on OSv guest.
Thank you all!
Tested-by: Claudio Fontana
On 08.06.2014 15:53, Ian Campbell wrote:
> In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes
> and XN elsewhere. In v7 the bit is always XN. Since w
On 10.06.2014 19:06, Peter Maydell wrote:
> UEFI mandates that the platform must include an RTC, so provide
> one in 'virt', using the PL031.
>
> Signed-off-by: Peter Maydell
> ---
> hw/arm/virt.c | 30 ++
> 1 file changed, 30 insertions(+)
>
> diff --git a/hw/arm/vi
On 14.06.2014 01:10, Peter Crosthwaite wrote:
> On Thu, Jun 12, 2014 at 2:01 AM, Claudio Fontana
> wrote:
>> On 10.06.2014 19:06, Peter Maydell wrote:
>>> UEFI mandates that the platform must include an RTC, so provide
>>> one in 'virt', using the PL0
On 17.06.2014 11:03, David Marchand wrote:
> Hello all,
>
> On 06/17/2014 04:54 AM, Stefan Hajnoczi wrote:
>> ivshmem has a performance disadvantage for guest-to-host
>> communication. Since the shared memory is exposed as PCI BARs, the
>> guest has to memcpy into the shared memory.
>>
>> vhost-u
Hello David,
On 20.06.2014 14:15, David Marchand wrote:
> Hello,
>
> (as suggested by Paolo, ccing Claudio and kvm mailing list)
>
> Here is a patchset containing an update on ivshmem specs documentation and
> importing ivshmem server and client tools.
> These tools have been written from scrat
Hi,
we were reading through this quickly today, and these are some of the questions
that
we think can came up when reading this. Answers to some of these questions we
think
we have figured out, but I think it's important to put this information into the
documentation.
I will quote the file in i
think that using objdump is better even for AArch64, since objdump
will see more use and be more tested.
I don't have anywhere to test until September, but I generally
Acked-by: Claudio Fontana
Hello Peter,
are you ok with this one?
Thanks,
Claudio
On 26 September 2014 15:09, wrote:
> From: Claudio Fontana
>
> check if the first cpu is an armv8 cpu, and if so, put
> arm,armv8-timer in the compatible string list.
>
> Note that due to this check, this patch moves
Reviewed-by: Claudio Fontana
On 10.10.2014 06:22, Amanieu d'Antras wrote:
> On AArch64 the si_addr field of siginfo_t is truncated to 32 bits
> because the fault address passes through an uint32_t variable. This
> is fixed by changing the variable to uint64_t.
>
> Si
On 09.10.2014 19:04, Peter Maydell wrote:
> On 9 October 2014 18:00, Peter Maydell wrote:
>> On 26 September 2014 14:09, wrote:
>>> From: Claudio Fontana
>>>
>>> check if the first cpu is an armv8 cpu, and if so, put
>>> arm,armv8-timer in the com
Hello,
On 10.10.2014 14:09, Jiri Slaby wrote:
> I am using qemu for teaching the Linux kernel at our university. I
> wrote a simple PCI device that can answer to writes/reads, generate
> interrupts and perform DMA. As I am dragging it locally over 2 years,
> I am sending it to you now.
>
> Signed
On 10.10.2014 13:32, Peter Maydell wrote:
> On 10 October 2014 05:22, Amanieu d'Antras wrote:
>> On AArch64 the si_addr field of siginfo_t is truncated to 32 bits
>> because the fault address passes through an uint32_t variable. This
>> is fixed by changing the variable to uint64_t.
>>
>> Signed-o
Just to point out that for the client there is also a DEBUG_LOG to uppercase,
just like already pointed out for the server.
>> diff --git a/contrib/ivshmem-client/ivshmem-client.c
>> b/contrib/ivshmem-client/ivshmem-client.c
>> new file mode 100644
>> index 000..ad210c8
>> --- /dev/null
>> +
On 05.09.2014 16:50, Semion Prihodko wrote:
> Let's discard semihosting. I have aarch64-linux-gnu-* toolchain and
> qemu-system-aarch64 emulator. How can I build a minimal kernel which
> outputs Hello World! via serial port and run it on the emulator?
>
If you run qemu with the "virt" platform, y
Reviewed-by: Claudio Fontana
On 03.09.2014 18:46, Richard Henderson wrote:
> Use 1 32-bit word instead of 6.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/tcg-be-ldst.h | 19 ---
> 1 file changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a
On 11.07.2014 11:28, Alvise Rigo wrote:
> The kernel version is a very recent one: v3.16.0-rc1.
> Maybe you are right. I will test some older version to see if I'm able
> to reproduce the issue.
>
> Thank you,
> alvise
Any news on this?
I will be soon in the situation when I can start testing th
On 03.09.2014 18:46, Richard Henderson wrote:
> The "old" qemu_ld opcode did not specify the size of the result,
> and so we had to assume full register width. With the new opcodes,
> we can narrow the result.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.c | 29 ++
This is obviously wrong, we have to put a \0 to separate the two options.
But thee question remains, should we mark that as arm,armv8-timer compatible?
Thanks,
Claudio
On 15 September 2014 10:14, wrote:
> From: Claudio Fontana
>
> Signed-off-by: Claudio Fontana
> ---
> hw
>
> Signed-off-by: David Marchand
Reviewed-by: Claudio Fontana
> ---
> docs/specs/ivshmem_device_spec.txt | 124
> +++-
> 1 file changed, 93 insertions(+), 31 deletions(-)
>
> diff --git a/docs/specs/ivshmem_device_spec.txt
&g
s
> supporting multiple MSI vectors can use different vectors to indicate
> different
> events have occurred. The semantics of interrupt vectors are left to the
> user's discretion.
> -
> -
> -Usage in the Guest
> ---
> -
> -The shared memory device is intended to be used with the provided UIO driver.
> -Very little configuration is needed. The guest should map BAR0 to access the
> -registers (an array of 32-bit ints allows simple writing) and map BAR2 to
> -access the shared memory region itself. The size of the shared memory region
> -is specified when the guest (or shared memory server) is started. A guest
> may
> -map the whole shared memory region or only part of it.
>
--
Claudio Fontana
Server Virtualization Architect
Huawei Technologies Duesseldorf GmbH
Riesstraße 25 - 80992 München
office: +49 89 158834 4135
mobile: +49 15253060158
On 15.03.2014 03:48, Richard Henderson wrote:
> Since the kernel doesn't pass any info on the reason for the fault,
> disassemble the instruction to detect a store.
>
> Signed-off-by: Richard Henderson
> ---
> user-exec.c | 29 +++--
> 1 file changed, 23 insertions(+), 6
On 15.03.2014 03:48, Richard Henderson wrote:
> Since the kernel doesn't pass any info on the reason for the fault,
> disassemble the instruction to detect a store.
>
> Signed-off-by: Richard Henderson
> ---
> user-exec.c | 29 +++--
> 1 file changed, 23 insertions(+), 6
tcg_out_callr(s, TCG_REG_TMP);
> -tcg_out_goto(s, (tcg_target_long)lb->raddr);
> +tcg_out_goto(s, (intptr_t)lb->raddr);
> }
>
> static void add_qemu_ldst_label(TCGContext *s, int is_ld, int opc,
>
Reviewed-by: Claudio Fontana
xt(s, ext, MO_8, a0, a1);
> break;
> case INDEX_op_ext16s_i64:
> case INDEX_op_ext16s_i32:
> -tcg_out_sxt(s, ext, 1, a0, a1);
> +tcg_out_sxt(s, ext, MO_16, a0, a1);
> break;
> case INDEX_op_ext32s_i64:
> -tcg_out_sxt(s, 1, 2, a0, a1
return;
> +}
> +
> /* Check for bitfield immediates. For the benefit of 32-bit quantities,
> use the sign-extended value. That lets us match rotated values such
> as 0xffff with the same 64-bit logic matching 0xffff.
> */
>
Reviewed-by: Claudio Fontana
t the lane that we just set. */
> +value &= ~(0xUL << shift);
> +
> +/* Iterate until all lanes have been set, and thus cleared from VALUE.
> */
> +while (value) {
> +shift = ctz64(value) & (63 & -16);
> +tcg_out_insn(s, 3405, MOVK, type, rd, value >> shift, shift);
> value &= ~(0xUL << shift);
> -insn = I3405_MOVK;
> -} while (value);
> +}
> }
>
> static inline void tcg_out_ldst_r(TCGContext *s,
>
Reviewed-by: Claudio Fontana
On 15.03.2014 03:48, Richard Henderson wrote:
> Loading an qemu pointer as an immediate happens often. E.g.
>
> - exit_tb $0x7fa8140013
> + exit_tb $0x7f81ee0013
> ...
> - : d2800260mov x0, #0x13
> - : f2b50280movkx0, #0xa814, lsl #16
> - : f2c00fe0movkx0, #
-c += r;
> -}
> -} else {
> -r = 64 - l; /* form 1100 or 0..01..10..0 */
> -c = r - h - 1;
> -}
> -if (ext == TCG_TYPE_I32) {
> -r &= 31;
> -c &= 31;
> -}
> -
> -tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c);
> -}
> -
> static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl,
> TCGReg rh, TCGReg al, TCGReg ah,
> tcg_target_long bl, tcg_target_long bh,
>
Reviewed-by: Claudio Fontana
_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
> -tcg_out_gotor(s, tcg_target_call_iarg_regs[1]);
> +tcg_out_insn(s, 3207, BR, tcg_target_call_iarg_regs[1]);
>
> tb_ret_addr = s->code_ptr;
>
> @@ -1914,5 +1926,5 @@ static void tcg_target_qemu_prologue(TCGContext *s)
> /* pop (FP, LR), restore SP to previous frame, return */
> tcg_out_pop_pair(s, TCG_REG_SP,
> TCG_REG_FP, TCG_REG_LR, frame_size_callee_saved);
> -tcg_out_ret(s);
> +tcg_out_insn(s, 3207, RET, TCG_REG_LR);
> }
>
Reviewed-by: Claudio Fontana
atic inline void tcg_out_rev(TCGContext *s, TCGType ext,
> @@ -1568,8 +1563,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> a1 = (int32_t)a1;
> /* FALLTHRU */
> case INDEX_op_brcond_i64:
> -tcg_out_cmp(s, ext, a0, a1, const_args[1]);
> -tcg_out_goto_label_cond(s, a2, args[3]);
> +tcg_out_brcond(s, ext, a2, a0, a1, const_args[1], args[3]);
> break;
>
> case INDEX_op_setcond_i32:
>
Reviewed-by: Claudio Fontana
3202, B_C, c, offset);
> +if (need_cmp) {
> +tcg_out_insn(s, 3202, B_C, c, offset);
> +} else if (c == TCG_COND_EQ) {
> +tcg_out_insn(s, 3201, CBZ, ext, a, offset);
> +} else {
> +tcg_out_insn(s, 3201, CBNZ, ext, a, offset);
> +}
> }
>
> static inline void tcg_out_rev(TCGContext *s, TCGType ext,
>
Reviewed-by: Claudio Fontana
sp = (value >> 12) - ((intptr_t)s->code_ptr >> 12);
> +if (disp == sextract64(disp, 0, 21)) {
> +tcg_out_insn(s, 3406, ADRP, rd, disp);
> +if (value & 0xfff) {
> +tcg_out_insn(s, 3401, ADDI, type, rd, rd, value & 0xfff);
> +
CG_REG_X2,
> (tlb_offset & 0xfff) + (offsetof(CPUTLBEntry, addend)) -
> (is_read ? offsetof(CPUTLBEntry, addr_read)
>: offsetof(CPUTLBEntry, addr_write)));
> +
> /* Perform the address comparison. */
> tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3, 0);
> -*label_ptr = s->code_ptr;
> +
> /* If not equal, we jump to the slow path. */
> +*label_ptr = s->code_ptr;
> tcg_out_goto_cond_noaddr(s, TCG_COND_NE);
> }
>
>
Reviewed-by: Claudio Fontana
qemu_st_helpers[size]);
> -tcg_out_callr(s, TCG_REG_TMP);
> +tcg_out_call(s, (intptr_t)qemu_st_helpers[size]);
> tcg_out_goto(s, (intptr_t)lb->raddr);
> }
>
>
Reviewed-by: Claudio Fontana
out_movi(s, TCG_TYPE_I32, TCG_REG_X3, lb->mem_index);
> -tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_X4, (intptr_t)lb->raddr);
> +tcg_out_adr(s, TCG_REG_X4, (intptr_t)lb->raddr);
> tcg_out_call(s, (intptr_t)qemu_st_helpers[size]);
> tcg_out_goto(s, (intptr_t)lb->raddr);
> }
>
Reviewed-by: Claudio Fontana
tcg_out_qemu_ld(s, args, MO_TEUL);
> break;
> case INDEX_op_qemu_ld32s:
> -tcg_out_qemu_ld(s, args, 4 | 2);
> -break;
> -case INDEX_op_qemu_ld32:
> -tcg_out_qemu_ld(s, args, 0 | 2);
> +tcg_out_qemu_ld(s, args, MO_TESL);
> break;
> case INDEX_op_qemu_ld64:
> -tcg_out_qemu_ld(s, args, 0 | 3);
> +tcg_out_qemu_ld(s, args, MO_TEQ);
> break;
> case INDEX_op_qemu_st8:
> -tcg_out_qemu_st(s, args, 0);
> +tcg_out_qemu_st(s, args, MO_UB);
> break;
> case INDEX_op_qemu_st16:
> -tcg_out_qemu_st(s, args, 1);
> +tcg_out_qemu_st(s, args, MO_TEUW);
> break;
> case INDEX_op_qemu_st32:
> -tcg_out_qemu_st(s, args, 2);
> +tcg_out_qemu_st(s, args, MO_TEUL);
> break;
> case INDEX_op_qemu_st64:
> -tcg_out_qemu_st(s, args, 3);
> +tcg_out_qemu_st(s, args, MO_TEQ);
> break;
>
> case INDEX_op_bswap32_i64:
>
Reviewed-by: Claudio Fontana
t; } },
> -
> -{ INDEX_op_qemu_ld32, { "r", "l" } },
> -{ INDEX_op_qemu_ld64, { "r", "l" } },
> -
> -{ INDEX_op_qemu_st8, { "l", "l" } },
> -{ INDEX_op_qemu_st16, { "l", "l" } },
> -{ INDEX_op_qemu_st32, { "l", "l" } },
> -{ INDEX_op_qemu_st64, { "l", "l" } },
> +{ INDEX_op_qemu_ld_i32, { "r", "l" } },
> +{ INDEX_op_qemu_ld_i64, { "r", "l" } },
> +{ INDEX_op_qemu_st_i32, { "l", "l" } },
> +{ INDEX_op_qemu_st_i64, { "l", "l" } },
>
> { INDEX_op_bswap16_i32, { "r", "r" } },
> { INDEX_op_bswap32_i32, { "r", "r" } },
> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
> index faccc36..adf0261 100644
> --- a/tcg/aarch64/tcg-target.h
> +++ b/tcg/aarch64/tcg-target.h
> @@ -98,7 +98,7 @@ typedef enum {
> #define TCG_TARGET_HAS_muluh_i641
> #define TCG_TARGET_HAS_mulsh_i641
>
> -#define TCG_TARGET_HAS_new_ldst 0
> +#define TCG_TARGET_HAS_new_ldst 1
>
> static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
> {
>
Reviewed-by: Claudio Fontana
TCGReg rd, TCGReg rm)
> + TCGReg rd, TCGReg rn)
> {
> -/* using REV16 0x5ac00400 */
> -unsigned int base = ext ? 0xdac00400 : 0x5ac00400;
> -tcg_out32(s, base | rm << 5 | rd);
> +tcg_out_insn(s, 3507, REV16, ext, rd, rn);
> }
>
> static inline void tcg_out_sxt(TCGContext *s, TCGType ext, TCGMemOp s_bits,
>
Reviewed-by: Claudio Fontana
EG_X9, TCG_REG_X10, TCG_REG_X11,
> +TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
> +TCG_REG_X16, TCG_REG_X17, TCG_REG_X18, TCG_REG_X19,
> +TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23,
> +TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27,
> +TCG_REG_X28, TCG_REG_X29, TCG_REG_X30,
> +
> +/* X31 is either the stack pointer or zero, depending on context. */
> +TCG_REG_SP = 31,
> +TCG_REG_XZR = 31,
> +
> +/* Aliases. */
> +TCG_REG_FP = TCG_REG_X29,
> +TCG_REG_LR = TCG_REG_X30,
> +TCG_AREG0 = TCG_REG_X19,
> } TCGReg;
>
> #define TCG_TARGET_NB_REGS 32
> @@ -92,10 +98,6 @@ typedef enum {
> #define TCG_TARGET_HAS_muluh_i641
> #define TCG_TARGET_HAS_mulsh_i641
>
> -enum {
> -TCG_AREG0 = TCG_REG_X19,
> -};
> -
> #define TCG_TARGET_HAS_new_ldst 0
>
> static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
>
--
Claudio Fontana
Server Virtualization Architect
Huawei Technologies Duesseldorf GmbH
Riesstraße 25 - 80992 München
office: +49 89 158834 4135
mobile: +49 15253060158
On 03.04.2014 21:56, Richard Henderson wrote:
> Since the kernel doesn't pass any info on the reason for the fault,
> disassemble the instruction to detect a store.
>
> Signed-off-by: Richard Henderson
> ---
> user-exec.c | 29 +++--
> 1 file changed, 23 insertions(+), 6
On 03.04.2014 21:56, Richard Henderson wrote:
> It's obviously call-clobbered, but is otherwise unused.
> Repurpose it as the TCG temporary.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.c | 34 --
> tcg/aarch64/tcg-target.h | 32
On 07.04.2014 11:49, Peter Maydell wrote:
> On 7 April 2014 09:03, Claudio Fontana wrote:
>> On 03.04.2014 21:56, Richard Henderson wrote:
>>> It's obviously call-clobbered, but is otherwise unused.
>>> Repurpose it as the TCG temporary.
>
>> Giving on
On 03.04.2014 21:56, Richard Henderson wrote:
> The definition of op_type wasn't encoded for the proper shift for
> the field, making the implementations confusing.
>
> Signed-off-by: Richard Henderson
At the end of the day the magic values remain in the load/store instructions
though.
Can we f
a1, a2);
> +tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2);
> break;
> case INDEX_op_ld_i32:
> case INDEX_op_ld32u_i64:
> -tcg_out_ldst(s, MO_32, LDST_LD, a0, a1, a2);
> +tcg_out_ldst(s, I3312_LDRW, a0, a1, a2);
> break;
> case INDEX_op_ld32s_i64:
> -tcg_out_ldst(s, MO_32, LDST_LD_S_X, a0, a1, a2);
> +tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2);
> break;
> case INDEX_op_ld_i64:
> -tcg_out_ldst(s, MO_64, LDST_LD, a0, a1, a2);
> +tcg_out_ldst(s, I3312_LDRX, a0, a1, a2);
> break;
>
> case INDEX_op_st8_i32:
> case INDEX_op_st8_i64:
> -tcg_out_ldst(s, MO_8, LDST_ST, REG0(0), a1, a2);
> +tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2);
> break;
> case INDEX_op_st16_i32:
> case INDEX_op_st16_i64:
> -tcg_out_ldst(s, MO_16, LDST_ST, REG0(0), a1, a2);
> +tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2);
> break;
> case INDEX_op_st_i32:
> case INDEX_op_st32_i64:
> -tcg_out_ldst(s, MO_32, LDST_ST, REG0(0), a1, a2);
> +tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2);
> break;
> case INDEX_op_st_i64:
> -tcg_out_ldst(s, MO_64, LDST_ST, REG0(0), a1, a2);
> +tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2);
> break;
>
> case INDEX_op_add_i32:
>
--
Claudio Fontana
Server Virtualization Architect
Huawei Technologies Duesseldorf GmbH
Riesstraße 25 - 80992 München
office: +49 89 158834 4135
mobile: +49 15253060158
On 03.04.2014 21:56, Richard Henderson wrote:
> Cleaning up the implementation of REV and REV16 at the same time.
>
> Reviewed-by: Claudio Fontana
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.c | 22 ++
> 1 file changed, 14 inser
/* DW_CFA_offset, x21, -64 */
> +0x80 + 20, 9, /* DW_CFA_offset, x20, -72 */
> +0x80 + 19, 10, /* DW_CFA_offset, x1p, -80 */
> +0x80 + 30, 11, /* DW_CFA_offset, lr, -88 */
> +0x80 + 29, 12, /* DW_CFA_offset, fp, -96 */
> +}
> +};
> +
> +void tcg_register_jit(void *buf, size_t buf_size)
> +{
> +debug_frame.fde.func_start = (intptr_t)buf;
> +debug_frame.fde.func_len = buf_size;
> +
> +tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
> +}
>
Reviewed-by: Claudio Fontana
e_saved area */
> + /* Restore registers x19..x28. */
> for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
> -int idx = (r - TCG_REG_X19) / 2 + 1;
> -tcg_out_load_pair(s, TCG_REG_SP, r, r + 1, idx);
> +int ofs = (r - TCG_REG_X19 + 2) * 8;
> +tcg_out_insn(s, 3314, LDP, r, r + 1, TCG_REG_SP, ofs, 1, 0);
> }
>
> -/* pop (FP, LR), restore SP to previous frame, return */
> -tcg_out_pop_pair(s, TCG_REG_SP,
> - TCG_REG_FP, TCG_REG_LR, frame_size_callee_saved);
> +/* Pop (FP, LR), restore SP to previous frame. */
> +tcg_out_insn(s, 3314, LDP, TCG_REG_FP, TCG_REG_LR,
> + TCG_REG_SP, frame_size_callee_saved, 0, 1);
> tcg_out_insn(s, 3207, RET, TCG_REG_LR);
> }
>
Reviewed-by: Claudio Fontana
G_X2, TCG_REG_X3,
> +TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7,
> +TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11,
> +TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
> + TCG_REG_X16, TCG_REG_X17, TCG_REG_X18, TCG_REG_X19,
> +TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23,
> +TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27,
> +TCG_REG_X28, TCG_REG_X29, TCG_REG_X30,
> +
> +/* X31 is either the stack pointer or zero, depending on context. */
> +TCG_REG_SP = 31,
> +TCG_REG_XZR = 31,
> +
> +/* Aliases. */
> +TCG_REG_FP = TCG_REG_X29,
> +TCG_REG_LR = TCG_REG_X30,
> +TCG_AREG0 = TCG_REG_X19,
> } TCGReg;
>
> #define TCG_TARGET_NB_REGS 32
> @@ -92,10 +98,6 @@ typedef enum {
> #define TCG_TARGET_HAS_muluh_i641
> #define TCG_TARGET_HAS_mulsh_i641
>
> -enum {
> -TCG_AREG0 = TCG_REG_X19,
> -};
> -
> #define TCG_TARGET_HAS_new_ldst 0
>
> static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
>
Reviewed-by: Claudio Fontana
t; +tcg_out_mov(s, size == MO_64, TCG_REG_X2, lb->datalo_reg);
> tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, lb->mem_index);
> tcg_out_adr(s, TCG_REG_X4, (intptr_t)lb->raddr);
> tcg_out_call(s, (intptr_t)qemu_st_helpers[opc]);
>
Reviewed-by: Claudio Fontana
O_TEUW);
> +tcg_out_qemu_st(s, a0, a1, MO_TEUW, a2);
> break;
> case INDEX_op_qemu_st32:
> -tcg_out_qemu_st(s, args, MO_TEUL);
> +tcg_out_qemu_st(s, a0, a1, MO_TEUL, a2);
> break;
> case INDEX_op_qemu_st64:
> -tcg_out_qemu_st(s, args, MO_TEQ);
> +tcg_out_qemu_st(s, a0, a1, MO_TEQ, a2);
> break;
>
> case INDEX_op_bswap32_i64:
>
Reviewed-by: Claudio Fontana
p_st16_i32:
> case INDEX_op_st16_i64:
> +tcg_out_ldst(s, LDST_16, LDST_ST, REG0(0), a1, a2);
> +break;
> + case INDEX_op_st_i32:
> case INDEX_op_st32_i64:
> -tcg_out_ldst(s, aarch64_ldst_get_data(opc),
> aarch64_ldst_get_type(opc),
> - REG0(0), a1, a2);
> +tcg_out_ldst(s, LDST_32, LDST_ST, REG0(0), a1, a2);
> +break;
> +case INDEX_op_st_i64:
> +tcg_out_ldst(s, LDST_64, LDST_ST, REG0(0), a1, a2);
> break;
>
> case INDEX_op_add_i32:
>
Reviewed-by: Claudio Fontana
Reviewed-by: Claudio Fontana
On 07.04.2014 16:31, Richard Henderson wrote:
> On 04/07/2014 04:45 AM, Claudio Fontana wrote:
>> On 03.04.2014 21:56, Richard Henderson wrote:
>>> The definition of op_type wasn't encoded for the proper shift for
>>> the field, maki
{ INDEX_op_st8_i64, { "rZ", "r" } },
> +{ INDEX_op_st16_i64, { "rZ", "r" } },
> +{ INDEX_op_st32_i64, { "rZ", "r" } },
> +{ INDEX_op_st_i64, { "rZ", "r" } },
>
> { INDEX_op_add_i32, { "r", "r", "rwA" } },
> { INDEX_op_add_i64, { "r", "r", "rA" } },
> @@ -1753,8 +1756,8 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
>
> { INDEX_op_qemu_ld_i32, { "r", "l" } },
> { INDEX_op_qemu_ld_i64, { "r", "l" } },
> -{ INDEX_op_qemu_st_i32, { "l", "l" } },
> -{ INDEX_op_qemu_st_i64, { "l", "l" } },
> +{ INDEX_op_qemu_st_i32, { "lZ", "l" } },
> +{ INDEX_op_qemu_st_i64, { "lZ", "l" } },
>
> { INDEX_op_bswap16_i32, { "r", "r" } },
> { INDEX_op_bswap32_i32, { "r", "r" } },
>
Reviewed-by: Claudio Fontana
gt; }
> }
>
> +if (offset >= -256 && offset < 256) {
> +tcg_out_ldst_9(s, size, type, rd, rn, offset);
> +return;
> +}
> +
> /* Worst-case scenario, move offset to temp register, use reg offset. */
> tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset);
> tcg_out_ldst_r(s, size, type, rd, rn, TCG_REG_TMP);
>
Reviewed-by: Claudio Fontana
Just to remember that there is an issue with this, as the previous reviewed-by
tag by me might mislead:
Nacked-by: Claudio Fontana
On 03.04.2014 21:56, Richard Henderson wrote:
> Cleaning up the implementation of REV and REV16 at the same time.
>
> Reviewed-by: Claudio Fontana
>
0, a1, a2);
> break;
> case INDEX_op_ld_i32:
> case INDEX_op_ld32u_i64:
> -tcg_out_ldst(s, MO_32, LDST_LD, a0, a1, a2);
> +tcg_out_ldst(s, I3312_LDRW, a0, a1, a2);
> break;
> case INDEX_op_ld32s_i64:
> -tcg_out_ldst(s, MO_32, LDST_LD_S_X, a0, a1, a2);
> +tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2);
> break;
> case INDEX_op_ld_i64:
> -tcg_out_ldst(s, MO_64, LDST_LD, a0, a1, a2);
> +tcg_out_ldst(s, I3312_LDRX, a0, a1, a2);
> break;
>
> case INDEX_op_st8_i32:
> case INDEX_op_st8_i64:
> -tcg_out_ldst(s, MO_8, LDST_ST, REG0(0), a1, a2);
> +tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2);
> break;
> case INDEX_op_st16_i32:
> case INDEX_op_st16_i64:
> -tcg_out_ldst(s, MO_16, LDST_ST, REG0(0), a1, a2);
> +tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2);
> break;
> case INDEX_op_st_i32:
> case INDEX_op_st32_i64:
> -tcg_out_ldst(s, MO_32, LDST_ST, REG0(0), a1, a2);
> +tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2);
> break;
> case INDEX_op_st_i64:
> -tcg_out_ldst(s, MO_64, LDST_ST, REG0(0), a1, a2);
> +tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2);
> break;
>
> case INDEX_op_add_i32:
>
Reviewed-by: Claudio Fontana
ut_ldst(s, LDST_32, LDST_LD, a0, a1, a2);
> +tcg_out_ldst(s, MO_32, LDST_LD, a0, a1, a2);
> break;
> case INDEX_op_ld32s_i64:
> - tcg_out_ldst(s, LDST_32, LDST_LD_S_X, a0, a1, a2);
> +tcg_out_ldst(s, MO_32, LDST_LD_S_X, a0, a1, a2);
> break;
> case INDEX_op_ld_i64:
> -tcg_out_ldst(s, LDST_64, LDST_LD, a0, a1, a2);
> +tcg_out_ldst(s, MO_64, LDST_LD, a0, a1, a2);
> break;
>
> case INDEX_op_st8_i32:
> case INDEX_op_st8_i64:
> -tcg_out_ldst(s, LDST_8, LDST_ST, REG0(0), a1, a2);
> +tcg_out_ldst(s, MO_8, LDST_ST, REG0(0), a1, a2);
> break;
> case INDEX_op_st16_i32:
> case INDEX_op_st16_i64:
> -tcg_out_ldst(s, LDST_16, LDST_ST, REG0(0), a1, a2);
> +tcg_out_ldst(s, MO_16, LDST_ST, REG0(0), a1, a2);
> break;
> case INDEX_op_st_i32:
> case INDEX_op_st32_i64:
> -tcg_out_ldst(s, LDST_32, LDST_ST, REG0(0), a1, a2);
> +tcg_out_ldst(s, MO_32, LDST_ST, REG0(0), a1, a2);
> break;
> case INDEX_op_st_i64:
> -tcg_out_ldst(s, LDST_64, LDST_ST, REG0(0), a1, a2);
> +tcg_out_ldst(s, MO_64, LDST_ST, REG0(0), a1, a2);
> break;
>
> case INDEX_op_add_i32:
>
Reviewed-by: Claudio Fontana
On 07.04.2014 18:33, Richard Henderson wrote:
> On 04/07/2014 12:58 AM, Claudio Fontana wrote:
>>> +|| (insn & 0x3bc0) == 0x2840 /* C3.3.7 */
>>
>> I think the Load (L) bit should be 0 here so
>>
>> == 0x2800
>
> Oop
1,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
> tcg_out_qemu_st(s, REG0(0), a1, a2, args[3]);
> break;
>
> -case INDEX_op_bswap32_i64:
> -/* Despite the _i64, this is a 32-bit bswap. */
> -ext = 0;
> - /* FALLTHRU */
> case INDEX_op_bswap64_i64:
> +tcg_out_rev64(s, a0, a1);
> +break;
> +case INDEX_op_bswap32_i64:
> case INDEX_op_bswap32_i32:
> -tcg_out_rev(s, ext, a0, a1);
> +tcg_out_rev32(s, a0, a1);
> break;
> case INDEX_op_bswap16_i64:
> case INDEX_op_bswap16_i32:
> -tcg_out_rev16(s, TCG_TYPE_I32, a0, a1);
> +tcg_out_rev16(s, a0, a1);
> break;
>
> case INDEX_op_ext8s_i64:
>
Reviewed-by: Claudio Fontana
t; +tcg_out_ldst(s, I3312_LDRH, a0, a1, a2);
> break;
> case INDEX_op_ld16s_i32:
> -tcg_out_ldst(s, LDST_16, LDST_LD_S_W, a0, a1, a2);
> +tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2);
> break;
> case INDEX_op_ld16s_i64:
> - tc
m4 != 0) {
> +unallocated_encoding(s);
add a return here.
> +}
> +
> +/* DUP (element, scalar) */
> +handle_simd_dupes(s, rd, rn, imm5);
> }
>
> /* C3.6.8 AdvSIMD scalar pairwise
>
Ciao,
Claudio
--
Claudio Fontana
Server Virtualization Architect
Huawei Technologies Duesseldorf GmbH
Riesstraße 25 - 80992 München
office: +49 89 158834 4135
mobile: +49 15253060158
On 14.03.2013 17:16, Peter Maydell wrote:
> On 14 March 2013 15:57, Claudio Fontana wrote:
>> I am currently working on an aarch64 tcg target implementation,
>> based on the available gdb patches contributed by ARM and the results
>> of the linaro toolchain.
>
> Do
linux test image, all from qemu-devel testing page.
Also tested on x86-64/linux built with buildroot,
and on arm v7/linux built with buildroot as well.
Claudio Fontana (3):
configure: permit compilation on arm aarch64
include/elf.h: add aarch64 ELF machine and relocs
tcg/aarch64: implement new
we will use the 26bit relative relocations in the aarch64 tcg target.
Signed-off-by: Claudio Fontana
---
include/elf.h | 128 ++
1 file changed, 128 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index a21ea53..43f6c9b 100644
add preliminary support for TCG target aarch64.
Signed-off-by: Claudio Fontana
---
include/exec/exec-all.h |5 +-
tcg/aarch64/tcg-target.c | 1084 ++
tcg/aarch64/tcg-target.h | 106 +
3 files changed, 1194 insertions(+), 1 deletion
support compiling on aarch64.
Signed-off-by: Claudio Fontana
---
configure | 8
1 file changed, 8 insertions(+)
diff --git a/configure b/configure
index 9439f1c..9cc398c 100755
--- a/configure
+++ b/configure
@@ -384,6 +384,8 @@ elif check_define __s390__ ; then
fi
elif
On 13.05.2013 20:29, Peter Maydell wrote:
> On 13 May 2013 14:28, Claudio Fontana wrote:
>>
>> support compiling on aarch64.
>>
>> Signed-off-by: Claudio Fontana
>
> This looks good, but it should be the last patch in the series,
> so we don't allow
On 13.05.2013 20:34, Peter Maydell wrote:
> On 13 May 2013 14:31, Claudio Fontana wrote:
>>
>> we will use the 26bit relative relocations in the aarch64 tcg target.
>
> This patch looks OK, but can I ask you to just neaten up
> the #defines by making the column of value
On 13.05.2013 20:28, Peter Maydell wrote:
> On 13 May 2013 14:33, Claudio Fontana wrote:
>>
>> add preliminary support for TCG target aarch64.
>
> Thanks for this patch. Some comments below.
>
>> Signed-off-by: Claudio Fontana
>> ---
>> include/exec
On 13.05.2013 21:49, Richard Henderson wrote:
> On 05/13/2013 06:33 AM, Claudio Fontana wrote:
>> +enum aarch64_cond_code {
>> +COND_EQ = 0x0,
>> +COND_NE = 0x1,
>> +COND_CS = 0x2, /* Unsigned greater or equal */
>> +COND_HS = 0x2, /* ALIAS gr
On 14.05.2013 17:19, Richard Henderson wrote:
> On 05/14/2013 05:25 AM, Peter Maydell wrote:
>>> Yes, I agree. I could not find an image which triggered that
code path for register rotation amounts.
>> Try PPC : rlwmn will generate a rotl (as will other insns).
>>
>
> rlwmn will only generate
regarding
missing braces which are actually there. I suspect it is
because of a comment.
checkpatch also complains about the labeled statements in
the switch, which I think are in fact good for readability.
Claudio Fontana (4):
include/elf.h: add aarch64 ELF machine and relocs
tcg/aarch64
we will use the 26bit relative relocs in the aarch64 tcg target.
Signed-off-by: Claudio Fontana
---
include/elf.h | 129 ++
1 file changed, 129 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index a21ea53..cf0d3e2 100644
--- a
support compiling on aarch64.
Signed-off-by: Claudio Fontana
---
configure | 8
1 file changed, 8 insertions(+)
diff --git a/configure b/configure
index 9439f1c..9cc398c 100755
--- a/configure
+++ b/configure
@@ -384,6 +384,8 @@ elif check_define __s390__ ; then
fi
elif
add SUBS to the arithmetic instructions and add a shift parameter to
all arithmetic instructions, so we can make use of shifted registers.
Signed-off-by: Claudio Fontana
---
tcg/aarch64/tcg-target.c | 36 +++-
1 file changed, 27 insertions(+), 9 deletions
add preliminary support for TCG target aarch64.
Signed-off-by: Claudio Fontana
---
include/exec/exec-all.h |5 +-
tcg/aarch64/tcg-target.c | 1185 ++
tcg/aarch64/tcg-target.h | 99
translate-all.c |2 +
4 files changed, 1290
On 23.05.2013 15:03, Peter Maydell wrote:
> On 23 May 2013 13:53, Andreas Färber wrote:
>> Am 23.05.2013 14:50, schrieb Peter Maydell:
>>> I'm happy for us to wait until an actual big-endian system
>>> running Linux appears before we worry about it.
>
>> I was worried about Big Endian QEMU target
On 23.05.2013 18:39, Peter Maydell wrote:
> On 23 May 2013 09:18, Claudio Fontana wrote:
>>
>> add preliminary support for TCG target aarch64.
>
> Richard's handling the technical bits of the review, so
> just some minor style nits here.
>
> I tested this on t
On 23.05.2013 18:29, Richard Henderson wrote:
> On 05/23/2013 01:18 AM, Claudio Fontana wrote:
>> +static inline void patch_reloc(uint8_t *code_ptr, int type,
>> + tcg_target_long value, tcg_target_long
>> addend)
>> +{
>>
Hello,
I am running kvm controlled qemu using mach virt,
and I have this glitch where the SP value in "info registers" always
appears as zero to me:
(qemu) info registers
PC=400b0044 SP=
X00=40324000 X01=40331000 X02=400b
X03=
;info registers" (kvm control)
To: Claudio Fontana
On 20 February 2014 15:13, Claudio Fontana wrote:
> I got it to "work for me" by replacing AARCH64_CORE_REG(regs.sp)
> with AARCH64_CORE_REG(sp_el1), since I am at EL1.
>
> I read in kvm_arch_put_registers:
19:17, Claudio Fontana wrote:
> From: Claudio Fontana
>
> this is general polishing for tcg/aarch64, removing the inline magic
> insn numbers, and putting up enums for intruction classes and subclasses
> in their stead.
>
> Signed-off-by: Claudio Fontana
> Tested-by: Claudio
Hello Peter,
I just wanted to ask what is the current state of kvm control for
qemu-system-aarch64.
I tried latest mainline but I think it's not all there yet (it complains
about missing cpu when I use -M virt and -cpu host, so I suspect some of
VOS patches are still missing).
Is your aarch64-kvm
Hello Peter,
thank you for your answer,
On 4 February 2014 16:39, Peter Maydell wrote:
>
> On 4 February 2014 15:36, Claudio Fontana wrote:
> > I just wanted to ask what is the current state of kvm control for
> > qemu-system-aarch64.
> > I tried latest mainline but I
On 4 February 2014 20:40, Christoffer Dall wrote:
> On Tue, Feb 04, 2014 at 04:52:08PM +, Peter Maydell wrote:
>> On 4 February 2014 16:37, Claudio Fontana wrote:
>> > On 4 February 2014 16:39, Peter Maydell wrote:
>> >> On 4 February 2014 15:36, Claudio
From: Claudio Fontana
this is general polishing for tcg/aarch64, removing the inline magic
insn numbers, and putting up enums for intruction classes and subclasses
in their stead.
Signed-off-by: Claudio Fontana
Tested-by: Claudio Fontana
---
tcg/aarch64/tcg-target.c | 528
Hello Peter,
On 13.12.2013 20:18, Peter Maydell wrote:
> From: Alexander Graf
>
> This patch adds emulation for the "Data-processing (3 source)"
> family of instructions, namely MADD, MSUB, SMADDL, SMSUBL, SMULH,
> UMADDL, UMSUBL, UMULH.
>
> Signed-off-by: Alexander Graf
> Signed-off-by: Alex
provide a skeleton for a64 instruction decoding in translate-a64.c,
by dividing instructions into the classes defined by the
ARM Architecture Reference Manual(DDI0487A_a) C3
Signed-off-by: Claudio Fontana
---
The following patch has been started during Linaro Connect
by me and Alex Bennee.
The
provide a skeleton for a64 instruction decoding in translate-a64.c,
by dividing instructions into the classes defined by the
ARM Architecture Reference Manual(DDI0487A_a) C3
Signed-off-by: Claudio Fontana
Signed-off-by: Alex Bennée
Reviewed-by: Alex Bennée
---
target-arm/translate-a64.c | 368
Hello,
On 09/27/2013 08:25 PM, Richard Henderson wrote:
> On 09/26/2013 05:48 PM, Alexander Graf wrote:
>> This patch adds emulation support for the orr instruction.
>>
>> Signed-off-by: Alexander Graf
>> ---
>> target-arm/helper-a64.c| 28 +++
>> target-arm/helper-a64.h| 1 +
On 11/18/2013 02:15 PM, Peter Maydell wrote:
> On 18 November 2013 13:12, Michael Matz wrote:
>> Hi,
>>
>> On Mon, 18 Nov 2013, Claudio Fontana wrote:
>>
>>>>> +case 3:
>>>>> +tcg_gen_rotr_i64(r, cpu_reg(reg), tcg_shift);
&
Btw, in the first patch:
On 11/18/2013 02:12 PM, Michael Matz wrote:
>
> From df54486da31d6329696effa61096eda5ab85395a Mon Sep 17 00:00:00 2001
> From: Michael Matz
> Date: Sun, 24 Mar 2013 02:52:42 +0100
> Subject: [PATCH] Fix 32bit rotates.
>
> The 32bit shifts generally weren't careful with
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