My team is working on sysemu support for Hexagon. We've made some good
progress so far and we'll work on upstreaming after Taylor’s hexagon linux-user
patch series lands.
The only use case we have focused on with sysemu is booting/running elf
programs. Both "-device loader,file=..." or "-kern
> -Original Message-
> From: Qemu-devel bounces+bcain=codeaurora@nongnu.org> On Behalf Of Taylor Simpson
> Sent: Friday, February 28, 2020 10:43 AM
> To: qemu-devel@nongnu.org
> Cc: riku.voi...@iki.fi; richard.hender...@linaro.org; laur...@vivier.eu;
> Taylor Simpson ; phi...@redhat.co
> -Original Message-
> From: Rob Landley
...
> On 7/12/21 8:42 AM, Brian Cain wrote:
...
> > and there's also a binary hexagon-linux cross toolchain that
> > we shared for use by kernel developers. The hexagon linux
> > toolchain is built on Ubuntu 16.0
> -Original Message-
> From: Rob Landley
> Sent: Monday, July 12, 2021 3:16 AM
...
> Except the LLVM_ENABLE_LLD part breaks with a standard debian/devuan x86-
> 64 host
> toolchain because it ONLY works with host llvm, and apparently only a pretty
> current one at that:
>
> https://gi
> -Original Message-
> From: Philippe Mathieu-Daudé On
> Behalf Of Philippe Mathieu-Daudé
> Sent: Monday, September 13, 2021 3:19 PM
> To: Waksmanski, Lukasz ; qemu-
> de...@nongnu.org
> Cc: Taylor Simpson ; Brian Cain
>
> Subject: Re: [qemu-hexagon] Error map
> -Original Message-
> From: Qemu-devel
> On Behalf Of Rob Landley
...
>
> On 8/30/20 3:47 PM, Taylor Simpson wrote:
> > Richard,
> >
> > Thank you so much for the feedback. I really appreciate it.
> >
> > I'll get to work addressing the issues. Since some of the items will take
> > lo
: Brian Cain
Subject: Known issue? qemu is much slower when built with clang vs gcc
We're seeing significant slowdowns when we build qemu with clang instead of
gcc. I'm hoping this is a known issue and there is a workaround or fix.
Please advise.
I have an example where qemu is 29X s
) {
ERROR("patch seems to be corrupt (line wrapped?)\n" .
This change makes sense to me, thanks for suggesting it.
Reviewed-by: Brian Cain
On 10/7/2024 10:45 AM, Daniel P. Berrangé wrote:
We expect all new code to be contributed with the "GPL-2.0-or-later"
license tag. Divergance is permitted if the new file is derived from
pre-existing code under a different license, whether from elsewhere
in QEMU codebase, or outside.
Issue a w
On 10/7/2024 6:03 AM, Paolo Bonzini wrote:
The following changes since commit b5ab62b3c0050612c7f9b0b4baeb44ebab42775a:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2024-10-04 19:28:37 +0100)
are available in the Git repository at:
https://gitlab.com/bonzi
On 10/7/2024 2:15 PM, Paolo Bonzini wrote:
Il lun 7 ott 2024, 19:56 Brian Cain ha scritto:
On 10/7/2024 6:03 AM, Paolo Bonzini wrote:
> The following changes since commit
b5ab62b3c0050612c7f9b0b4baeb44ebab42775a:
>
> Merge tag 'for-upstream' of
On 11/4/2024 11:49 AM, Taylor Simpson wrote:
All Hexagon debugging is now done with QEMU mechanisms
(e.g., -d in_asm) or with a connected debugger (lldb).
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h | 8 +--
target/hexagon/helper.h| 5 +-
target/hexagon/internal.h
TARGET_NR_listmount 458
+#define TARGET_NR_lsm_get_self_attr 459
+#define TARGET_NR_lsm_set_self_attr 460
+#define TARGET_NR_lsm_list_modules 461
+#define TARGET_NR_mseal 462
+#define TARGET_NR_syscalls 463
For hexagon system calls:
Reviewed-by: Brian Cain
Note for future updates that as of v6.11
On 9/16/2024 11:31 AM, Brian Cain wrote:
On 9/16/2024 11:05 AM, Brian Cain wrote:
On 9/16/2024 10:47 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/16/2024 8:12 AM, Alex Bennée wrote:
Brian Cain writes:
On 9/6/2024 9:39 PM, Brian Cain wrote:
With newer clang builds (19.x), there
>free, so that that the memory is
properly cleaned when the object is finalized, but the former doesn't.
Fixes: e72a7f65c1 (hw: Move declaration of IRQState to header and add init
function)
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: BALATON Zoltan
---
Reviewed-by: Brian
On 9/17/2024 1:47 PM, Matheus Tavares Bernardino wrote:
At e72a7f65c1 (hw: Move declaration of IRQState to header and add init
function, 2024-06-29), we've changed qemu_allocate_irq() to use a
combination of g_new() + object_initialize() instead of
IRQ(object_new()). The latter sets obj->free,
From: Brian Cain
Also: add mapping for "quic_bc...@quicinc.com" which was ~briefly
used for some replies to mailing list traffic.
Signed-off-by: Brian Cain
Signed-off-by: Brian Cain
---
.mailmap| 2 ++
MAINTAINERS | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
di
-addr-update-oss.qualcomm.com
Brian Cain (1):
MAINTAINERS: update email addr for Brian Cain
.mailmap| 2 ++
MAINTAINERS | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
--
2.34.1
On 12/3/2024 8:53 AM, Philippe Mathieu-Daudé wrote:
On 3/12/24 15:31, Peter Maydell wrote:
On Tue, 3 Dec 2024 at 14:23, Brian Cain
wrote:
On 12/2/2024 2:43 PM, Philippe Mathieu-Daudé wrote:
On 23/11/24 17:46, Brian Cain wrote:
From: Brian Cain
Also: add mapping for "qu
On 12/2/2024 2:43 PM, Philippe Mathieu-Daudé wrote:
On 23/11/24 17:46, Brian Cain wrote:
From: Brian Cain
Also: add mapping for "quic_bc...@quicinc.com" which was ~briefly
used for some replies to mailing list traffic.
Signed-off-by: Brian Cain
Signed-off-by: Brian Cain
---
-by: Brian Cain
target/hexagon/gen_analyze_funcs.py | 6 +++--
target/hexagon/gen_decodetree.py| 19 +++
target/hexagon/gen_helper_funcs.py | 7 +++---
target/hexagon/gen_helper_protos.py | 7 +++---
target/hexagon/gen_idef_parser_funcs.py | 11
patch. Sorry, I am
not sure how I missed it.
Reviewed-by: Brian Cain
target/hexagon/cpu.h | 6 --
target/hexagon/helper.h| 3 -
target/hexagon/internal.h | 11
target/hexagon/translate.h | 2 -
target/hexagon/genptr.c| 7 ---
target/hexagon/op_helper.c
On 12/3/2024 12:56 PM, Anton Johansson via wrote:
On 22/11/24, Richard Henderson wrote:
On 11/20/24 19:49, Anton Johansson wrote:
Temporary vectors in helper-to-tcg generated code are allocated from an
array of bytes in CPUArchState, specified with --temp-vector-block.
This commits adds such
Mea culpa, I don't know how I got this wrong in 2dfe93699c. Still
getting used to the new address, I suppose. Somehow I got it right in the
mailmap, though.
Signed-off-by: Brian Cain
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTA
Reviewed-by: Leif Lindholm
Reviewed-by: Brian Cain
---
.mailmap | 5 +++--
MAINTAINERS | 2 +-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/.mailmap b/.mailmap
index 727ce204b2..5f6df414e1 100644
--- a/.mailmap
+++ b/.mailmap
@@ -87,8 +87,9 @@ Huacai Chen
H
th_is_big_endian = hexagon_cpu_datapath_is_big_endian;
cc->has_work = hexagon_cpu_has_work;
cc->dump_state = hexagon_dump_state;
cc->set_pc = hexagon_cpu_set_pc;
For hexagon:
Reviewed-by: Brian Cain
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index c38439c1800..8ccd22
On 1/3/2025 5:17 PM, Philippe Mathieu-Daudé wrote:
Keep the Hexagon target in line with others.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Brian Cain
target/Kconfig | 1 +
target/hexagon/Kconfig | 2 ++
2 files changed, 3 insertions(+)
create mode 100644
On 1/31/2025 7:24 AM, Alex Bennée wrote:
Hi,
The KVM/QEMU community call is at:
https://meet.jit.si/kvmcallmeeting
@
04/02/2025 14:00 UTC
Are there any agenda items for the sync-up?
I'd like to discuss the upstreaming of hexagon sysemu - one piece we
could use help is the "QTimer." This i
On 12/6/2024 10:01 AM, Anton Johansson via wrote:
Separate submission of patches 35 and 37 from the helper-to-tcg
patchset:
https://lore.kernel.org/qemu-devel/20241121014947.18666-1-a...@rev.ng/
Anton Johansson (2):
target/hexagon: Use argparse in all python scripts
target/hexagon: M
On 12/4/2024 1:59 PM, Brian Cain wrote:
On 11/5/2024 10:27 AM, Taylor Simpson wrote:
All Hexagon debugging is now done with QEMU mechanisms
(e.g., -d in_asm) or with a connected debugger (lldb).
Signed-off-by: Taylor Simpson
Reviewed-by: Matheus Tavares Bernardino
---
I was wondering
_status);
-tmp = internal_fmafx(minus_RsV, RtV, RxV, 0, &env->fp_status);
-if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) {
-RxV = tmp;
-}
-set_float_exception_flags(0, &env->fp_status);
-if (float32_is_infinity(RxV) && !infinp) {
-
->fp_status);
arch_fpop_end(env);
return RdV;
}
Reviewed-by: Brian Cain
, &env->fp_status);
+RxV = float32_muladd(RsV, RtV, RxV, 0, &env->fp_status);
arch_fpop_end(env);
return RxV;
}
Reviewed-by: Brian Cain
, 0, &env->fp_status);
+RxV = float32_muladd(RsV, RtV, RxV, float_muladd_negate_product,
+ &env->fp_status);
arch_fpop_end(env);
return RxV;
}
Reviewed-by: Brian Cain
dd_scalbn(RsV, RtV, RxV, fSXTN(8, 64, PuV),
+float_muladd_suppress_add_product_zero,
+&env->fp_status);
arch_fpop_end(env);
return RxV;
}
Reviewed-by: Brian Cain
= int128_mul_6464(accumulated, 1);
+x.mant = int128_make64(accumulated);
x.sticky = sticky;
prod = fGETUWORD(1, float64_getmant(a)) * fGETUWORD(1,
float64_getmant(b));
x.mant = int128_add(x.mant, int128_mul_6464(prod, 0x1ULL));
Reviewed-by: Brian Cain
p;l, &h, ai, bi);
+return int128_make128(l, h);
}
Reviewed-by: Brian Cain
static Int128 int128_sub_borrow(Int128 a, Int128 b, int borrow)
acc.sign = c_sign;
-result = accum_add(prod, acc);
-} else {
-result = prod;
-}
-result.exp += scale;
-return accum_round_float32(result, fp_status);
-}
float64 internal_mpyhh(float64 a, float64 b,
unsigned long long int accumulated,
Reviewed-by: Brian Cain
.i;
+}
+assert(a.exp == 1);
+Double ret;
+ret.i = 0;
+ret.sign = a.sign;
+ret.exp = 0;
+ret.mant = int128_getlo(a.mant);
+return ret.i;
}
-GEN_XF_ROUND(float64, DF_MANTBITS, DF_INF_EXP, Double)
-
float64 internal_mpyhh(float64 a, float64 b,
unsigned long long int accumulated,
float_status *fp_status)
Reviewed-by: Brian Cain
= f32 };
+int exp = float32_getexp_raw(f32);
if (float32_is_normal(f32)) {
-return a.exp;
+return exp;
}
if (float32_is_denormal(f32)) {
-return a.exp + 1;
+return exp + 1;
}
return -1;
}
Reviewed-by: Brian Cain
gn);
+return ret;
}
float64 internal_mpyhh(float64 a, float64 b,
Reviewed-by: Brian Cain
From: Anton Johansson
QOL commit, all the various gen_* python scripts take a large set
arguments where order is implicit. Using argparse we also get decent
error messages if a field is missing or too many are added.
Signed-off-by: Anton Johansson
Reviewed-by: Brian Cain
Signed-off-by: Brian
From: Taylor Simpson
All Hexagon debugging is now done with QEMU mechanisms
(e.g., -d in_asm) or with a connected debugger (lldb).
Signed-off-by: Taylor Simpson
Reviewed-by: Matheus Tavares Bernardino
Reviewed-by: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/README | 9
AUSE fixes
Anton Johansson (2):
target/hexagon: Use argparse in all python scripts
target/hexagon: Make HVX vector args. restrict *
Brian Cain (2):
target/hexagon: rename HEX_EXCP_*=>HEX_CAUSE_*
target/hexagon: add enums for event, cause
Taylor Simpson (1):
From: Brian Cain
Reviewed-by: Taylor Simpson
Signed-off-by: Brian Cain
---
target/hexagon/cpu_bits.h | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index 2e60c0fafe..ff596e2a94 100644
--- a
From: Anton Johansson
Adds restrict qualifier to HVX pointer arguments. This will allow the
compiler to produce better optimized code, as input vectors are now
assumed not to alias, and no runtime aliasing checks will be required.
Signed-off-by: Anton Johansson
Reviewed-by: Brian Cain
Signed
From: Brian Cain
The values previously used for "HEX_EXCP_*" were the cause code
definitions and not the event numbers. So in this commit, we update
the names to reflect the cause codes. In HEX_EVENT_TRAP0's case, we add
a new "HEX_EVENT_*" with the correct event num
pat, false),
DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust,
0,
qdev_prop_uint32, target_ulong),
Reviewed-by: Brian Cain
+ Stefan
On 12/12/2024 10:18 PM, Brian Cain wrote:
The following changes since commit a5ba0a7e4e150d1350a041f0d0ef9ca6c8d7c307:
Merge tag 'pull-aspeed-20241211' of https://github.com/legoater/qemu into
staging (2024-12-11 15:16:47 +)
are available in the Git repository at:
* bar" should be "foo *bar"
#33: FILE: target/hexagon/mmvec/macros.h:28:
+#define VuV (*(MMVector * restrict)(VuV_void))
I think checkpatch.pl has a point here. :)
I'll switch to `*restrict`!:)
With this change to fix checkpatch,
Reviewed-by: Brian Cain
//Anton
tion"
+#endif
+
#define NUM_PREGS 4
#define TOTAL_PER_THREAD_REGS 64
We hope to mitigate this one in the not-too-distant future. Staged
commits on my tree implement system emulation, undergoing some
review/revision now. ;)
But of course this change makes sense for the time being.
Reviewed-by: Brian Cain
On 1/21/2025 8:23 AM, Philippe Mathieu-Daudé wrote:
Remove as unreachable code.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Brian Cain
target/hexagon/cpu.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index
On 3/24/2025 8:53 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Anton Johansson
Sent: Wednesday, March 12, 2025 2:46 PM
To: qemu-devel@nongnu.org
Cc: a...@rev.ng; ltaylorsimp...@gmail.com; brian.c...@oss.qualcomm.com;
phi...@linaro.org
Subject: [PATCH 2/2] target/hexag
On 3/18/2025 2:14 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Sid Manning
Sent: Tuesday, March 18, 2025 1:34 PM
To: ltaylorsimp...@gmail.com; 'Brian Cain'
; qemu-devel@nongnu.org
Cc: richard.hender...@linaro.org; phi...@linaro.org; Matheus Bernardino
On 4/4/2025 9:33 AM, Richard Henderson wrote:
On 4/3/25 19:52, Brian Cain wrote:
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu-param.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index 45ee7b4640
On 3/3/2025 6:26 AM, Philippe Mathieu-Daudé wrote:
Hi Brian and Sid,
On 1/3/25 18:20, Brian Cain wrote:
From: Sid Manning
Co-authored-by: Matheus Tavares Bernardino
Co-authored-by: Damien Hedde
Signed-off-by: Brian Cain
---
MAINTAINERS | 2 +
docs/devel/hexagon
Changes since previous "misc hexagon patches" series (v2):
- changed author to match MAINTAINERS (I was fooled by the mailmap before --
so, for real this time).
Brian Cain (5):
target/hexagon: handle .new values
target/hexagon: Fix badva reference, delete CAUSE
target/hexagon: A
The BADVA reg is referred to with the wrong identifier. The
CAUSE reg field of SSR is not yet modeled.
Signed-off-by: Brian Cain
---
target/hexagon/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 766b678651
We should raise an exception in the event that we encounter a packet
that can't be correctly decoded, not fault.
Signed-off-by: Brian Cain
---
target/hexagon/decode.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
To remove any confusion with HVX or other potential store instructions,
we'll qualify this context var with "scalar".
Signed-off-by: Brian Cain
---
target/hexagon/idef-parser/README.rst | 2 +-
target/hexagon/insn.h | 4 ++--
target/h
On 3/24/2025 2:40 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Saturday, March 1, 2025 11:21 AM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a
On 3/17/2025 1:43 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Friday, February 28, 2025 11:28 PM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a
On 3/19/2025 2:50 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Friday, February 28, 2025 11:28 PM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a
On 3/3/2025 6:26 AM, Philippe Mathieu-Daudé wrote:
Hi Brian and Sid,
On 1/3/25 18:20, Brian Cain wrote:
From: Sid Manning
Co-authored-by: Matheus Tavares Bernardino
Co-authored-by: Damien Hedde
Signed-off-by: Brian Cain
---
MAINTAINERS | 2 +
docs/devel/hexagon
76854-1-phi...@linaro.org/
Brian Cain (5):
target/hexagon: handle .new values
target/hexagon: Fix badva reference, delete CAUSE
target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof
target/hexagon: s/pkt_has_store/pkt_has_scalar_store
target/hexagon: Remove unreachable
target/hexag
From: Brian Cain
The BADVA reg is referred to with the wrong identifier. The
CAUSE reg field of SSR is not yet modeled.
Signed-off-by: Brian Cain
---
target/hexagon/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index
From: Brian Cain
To remove any confusion with HVX or other potential store instructions,
we'll qualify this context var with "scalar".
Signed-off-by: Brian Cain
---
target/hexagon/idef-parser/README.rst | 2 +-
target/hexagon/insn.h | 4 ++--
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 758e5fd12d..6803908718 100755
--- a/target/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 6803908718..a2dcb0aa2e 100755
--- a/target/hexagon/hex_common.py
+++ b/target
From: Brian Cain
We should raise an exception in the event that we encounter a packet
that can't be correctly decoded, not fault.
Signed-off-by: Brian Cain
---
target/hexagon/decode.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/decode.c b/t
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 758e5fd12d..6803908718 100755
--- a/target/hexagon/hex_common.py
+++ b/target
fe to base the table on the
complete opcodes table.
Signed-off-by: Taylor Simpson
---
Reviewed-by: Brian Cain
Tested-by: Brian Cain
target/hexagon/genptr.c | 6 ++-
target/hexagon/README| 1 -
target/hexagon/gen_tcg_func_table.py
Adding Matheus, Marco -- their "quic_" email addresses might be
deactivated soon if not already.
On 4/16/2025 9:45 AM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Philippe Mathieu-Daudé
Sent: Wednesday, April 16, 2025 12:18 AM
To: Taylor Simpson ; qemu-devel@nongnu.org
C
On 4/17/2025 11:33 AM, Matheus Tavares Bernardino wrote:
This is the new email I'll be using from now on.
Signed-off-by: Matheus Tavares Bernardino
---
Reviewed-by: Brian Cain
Tested-by: Brian Cain
.mailmap | 1 +
1 file changed, 1 insertion(+)
diff --git a/.mailmap b/.ma
On 4/24/2025 4:46 AM, Philippe Mathieu-Daudé wrote:
Since the macros.h headers call GETPC(), they need to
include "accel/tcg/getpc.h", which defines it.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Brian Cain
target/hexagon/macros.h | 1 +
target/hex
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 6803908718..a2dcb0aa2e 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon
On 4/16/2025 12:54 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Friday, February 28, 2025 10:26 PM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a
: Brian Cain
Sent: Monday, April 7, 2025 1:27 PM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; matheus.bernard...@oss.qualcomm.com;
a...@rev.ng;
a...@rev.ng; marco.lie...@oss.qualcomm.com;
ltaylorsimp...@gmail.com; alex.ben...@linaro.org
On 4/14/2025 12:04 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Monday, April 7, 2025 1:27 PM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; matheus.bernard...@oss.qualcomm.com; a...@rev.ng
On 1/11/2025 4:08 PM, Stefan Weil via wrote:
Am 10.01.25 um 21:33 schrieb Pierrick Bouvier:
For now, it was only possible to build plugins using GCC on Windows.
However,
windows-aarch64 only supports Clang.
This biggest roadblock was to get rid of gcc_struct attribute, which
is not
supported
Signed-off-by: Brian Cain
Signed-off-by: Matheus Tavares Bernardino
---
target/hexagon/cpu.c| 10 +++---
target/hexagon/cpu_helper.c | 17 ++---
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 80f5e23794
On 2/28/2025 11:28 PM, Brian Cain wrote:
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/sys_macros.h | 8 +--
target/hexagon/op_helper.c | 104
2 files changed, 108 insertions(+), 4 deletions(-)
diff --git a/target/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/translate.c | 16
1 file changed, 16 insertions(+)
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index d4b22acb72..ff881d1060 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu.h | 1 +
target/hexagon/cpu.c | 7 ++-
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index baa48ec051..4667a1f748 100644
--- a/target/hexagon/cpu.h
+++ b/target
From: Brian Cain
The hardware-assisted scheduler helps manage tasks on the run queue
and interrupt steering.
This instruction is defined in the Qualcomm Hexagon V71 Programmer's Reference
Manual -
https://docs.qualcomm.com/bundle/publicresource/80-
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/hex_common.py | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 1e94e1fef5..7b5bb2cd46 100755
--- a/target/hexagon/hex_common.py
+++ b/target/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu_bits.h | 2 ++
target/hexagon/gen_tcg_funcs.py | 32 +++-
2 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index ff596e2a94
From: Brian Cain
siad is the 'Set interrupt auto disable' instruction.
Signed-off-by: Brian Cain
---
target/hexagon/op_helper.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 687e7f45c2..
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/attribs_def.h.inc | 414 +++--
target/hexagon/imported/macros.def | 558 +
2 files changed, 942 insertions(+), 30 deletions(-)
mode change 100755 => 100644 target/hexagon/impor
From: Brian Cain
Also: add nop TCG overrides for break,unpause,fetchbo,dczeroa
break: this hardware breakpoint instruction is used with the in-silicon
debugger feature, this is not modeled.
unpause: this instruction is used to resume hardware threads that are
stalled by pause instructions
From: Brian Cain
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Brian Cain
---
target/hexagon/cpu.h | 6 ++
target/hexagon/internal.h | 4 ++
target/hexagon/cpu.c | 17 ++
target/hexagon/gdbstub.c | 45 ++
target/hexagon/op_helper.c | 16
On 3/4/2025 12:27 AM, Markus Armbruster wrote:
Brian Cain writes:
From: Brian Cain
Co-authored-by: Mike Lambert
Co-authored-by: Sid Manning
Signed-off-by: Brian Cain
[...]
diff --git a/qapi/machine.json b/qapi/machine.json
index a6b8795b09..a7070bad4d 100644
--- a/qapi/machine.json
On 3/4/2025 9:46 AM, Philippe Mathieu-Daudé wrote:
Hi Brian,
On 1/3/25 18:20, Brian Cain wrote:
From: Brian Cain
A bit opaque...
Whoops -- will fix it.
Signed-off-by: Brian Cain
---
MAINTAINERS | 1 +
tests/functional/meson.build | 8
On 3/4/2025 9:46 AM, Philippe Mathieu-Daudé wrote:
Hi Brian,
On 1/3/25 18:20, Brian Cain wrote:
From: Brian Cain
A bit opaque...
Whoops -- will fix it.
Signed-off-by: Brian Cain
---
MAINTAINERS | 1 +
tests/functional/meson.build | 8
From: Brian Cain
Co-authored-by: Taylor Simpson
Co-authored-by: Michael Lambert
Co-authored-by: Sid Manning
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Brian Cain
---
target/hexagon/cpu-param.h | 4 +
target/hexagon/cpu.h | 13 +
target/hexagon/hex_mmu.h | 30
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu_helper.h | 1 +
target/hexagon/cpu.c| 23 +
target/hexagon/cpu_helper.c | 41 +
3 files changed, 65 insertions(+)
diff --git a/target/hexagon/cpu_helper.h b
From: Brian Cain
These registers are defined in the Qualcomm Hexagon V71 Programmer's
Reference Manual -
https://docs.qualcomm.com/bundle/publicresource/80-N2040-51_REV_AB_Hexagon_V71_ProgrammerS_Reference_Manual.pdf
Refer to §11.9.1 SYSTEM GUEST, §11.9.2 SYSTEM MONITOR.
Signed-off-by:
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/hex_mmu.c | 54 +++-
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c
index 54c4ba2dbf..d2297c036d 100644
--- a/target/hexagon
From: Brian Cain
Signed-off-by: Brian Cain
---
docs/system/hexagon/emulation.rst | 16
docs/system/target-hexagon.rst| 1 +
2 files changed, 17 insertions(+)
create mode 100644 docs/system/hexagon/emulation.rst
diff --git a/docs/system/hexagon/emulation.rst
b/docs
From: Brian Cain
Signed-off-by: Brian Cain
---
target/hexagon/cpu.h| 3 ++
target/hexagon/cpu_bits.h | 1 +
target/hexagon/cpu_helper.h | 3 ++
target/hexagon/cpu.c| 14 +-
target/hexagon/cpu_helper.c | 94 +
target/hexagon
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