On Tue, May 10, 2022 at 3:03 AM Atish Patra wrote:
>
> stimecmp allows the supervisor mode to update stimecmp CSR directly
> to program the next timer interrupt. This CSR is part of the Sstc
> extension which was ratified recently.
>
> Signed-off-by: Atish Patra
> ---
> target/riscv/cpu.c
On Tue, May 10, 2022 at 3:03 AM Atish Patra wrote:
>
> vstimecmp CSR allows the guest OS or to program the next guest timer
> interrupt directly. Thus, hypervisor no longer need to inject the
> timer interrupt to the guest if vstimecmp is used. This was ratified
> as a part of the Sstc extension.
also emulates the real hardware
> more closely.
>
> Signed-off-by: Atish Patra
Otherwise, this looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> hw/intc/riscv_aclint.c | 41 --
> hw/timer/ibex_timer.c | 1
INT mtime MMIO register
> writable")
>
> Signed-off-by: Atish Patra
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> hw/intc/riscv_aclint.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/riscv_aclint.c b/hw/in
On Fri, May 13, 2022 at 1:34 AM Dylan Reid wrote:
>
> When starting the virt machine with `-machine virt,aia=aplic-imsic`,
> both the imsic and aplic init code will add platform fdt nodes by
> calling `platform_bus_add_all_fdt_nodes`. This leads to an error at
> startup:
> ```
> qemu_fdt_add_subno
On Tue, May 17, 2022 at 5:46 AM Alistair Francis wrote:
>
> On Thu, May 12, 2022 at 12:52 AM Anup Patel wrote:
> >
> > We should disable extensions in riscv_cpu_realize() if minimum required
> > priv spec version is not satisfied. This also ensures that machines with
On Sat, Sep 4, 2021 at 8:42 PM Bin Meng wrote:
>
> On Thu, Sep 2, 2021 at 7:42 PM Anup Patel wrote:
> >
> > The machine or device emulation should be able to force set certain
> > CPU features because:
> > 1) We can have certain CPU features which are in-general o
hanges since v1:
- Revamped whole series and created more granular patches
- Added HGEIE and HGEIP CSR emulation for H-extension
- Added APLIC emulation
- Added IMSIC emulation
Anup Patel (22):
target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64
HS-mode
target/riscv: Imp
We should be returning illegal instruction trap when RV64 HS-mode tries
to access RV32 HS-mode CSR.
Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 2 +-
1 file changed, 1
The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external
interrupt to Guest/VM running at VS-level.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c| 61
A hypervsior can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 3 ++-
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 18 +++---
3 files changed, 16
devices expect AIA CSRs implemented by RISC-V CPUs.
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 11 +++
target/riscv/cpu.h | 5 +
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv
We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 3
console input and other I/O events.
To solve this, we check and inject interrupt after setting V=1.
Signed-off-by: Anup Patel
---
target/riscv/cpu_helper.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index bb7ac9890b
12 so we
add dummy implementation (i.e. read zero and ignore write) of AIA
interrupt filtering CSRs.
Signed-off-by: Anup Patel
---
target/riscv/csr.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 46d0cabbde..43ae444774 1
.
Signed-off-by: Anup Patel
---
target/riscv/cpu.c| 19 +++
target/riscv/cpu.h| 12 ++
target/riscv/cpu_helper.c | 241 +-
target/riscv/machine.c| 3 +
4 files changed, 245 insertions(+), 30 deletions(-)
diff --git a/target/riscv/cpu.c b/target
The AIA specification defines IMSIC interface CSRs for easy access
to the per-HART IMSIC registers without using indirect xiselect and
xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
Signed-off-by: Anup Patel
---
target/riscv/csr.c | 199
The RISC-V AIA specification extends RISC-V local interrupts and
introduces new CSRs. This patch adds defines for the new AIA CSRs.
Signed-off-by: Anup Patel
---
target/riscv/cpu_bits.h | 128
1 file changed, 128 insertions(+)
diff --git a/target/riscv
The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 14 +-
target/riscv/cpu_helper.c | 10 +-
target/riscv/csr.c| 560
.
This patch adds device emulation for RISC-V AIA IMSIC which
supports M-level, S-level, and VS-level MSIs.
Signed-off-by: Anup Patel
---
hw/intc/Kconfig | 3 +
hw/intc/meson.build | 1 +
hw/intc/riscv_imsic.c | 443 ++
include
The AIA specification introduces new [m|s|vs]topi CSRs for
reporting pending local IRQ number and associated IRQ priority.
Signed-off-by: Anup Patel
---
target/riscv/csr.c | 154 +
1 file changed, 154 insertions(+)
diff --git a/target/riscv/csr.c b
The AIA device emulation (such as AIA IMSIC) should be able to set
(or provide) AIA ireg read-modify-write callback for each privilege
level of a RISC-V HART.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 19 +++
target/riscv/cpu_helper.c | 14 ++
2 files
The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h | 7 ++
target/riscv/csr.c
We should use the AIA INTC compatible string in the CPU INTC
DT nodes when the CPUs support AIA feature. This will allow
Linux INTC driver to use AIA local interrupt CSRs.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 13 +++--
1 file changed, 11
We have two new machine options "aia" and "aia-guests" available
for the RISC-V virt machine so let's document these options.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
docs/system/riscv/virt.rst | 16
1 file changed, 16 insertions(+)
The AIA hvictl and hviprioX CSRs allow hypervisor to control
interrupts visible at VS-level. This patch implements AIA hvictl
and hviprioX CSRs.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h | 1 +
target/riscv/csr.c | 126 +
target/riscv
We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +
target/riscv/cpu.
adds device emulation for RISC-V AIA APLIC.
Signed-off-by: Anup Patel
---
hw/intc/Kconfig | 3 +
hw/intc/meson.build | 1 +
hw/intc/riscv_aplic.c | 970 ++
include/hw/intc/riscv_aplic.h | 73 +++
4 files changed, 1047 insertions
We extend virt machine to emulate AIA APLIC devices only when
"aia=aplic" parameter is passed along with machine name in QEMU
command-line. When "aia=none" or not specified then we fallback
to original PLIC device emulation.
Signed-off-by: Anup Patel
---
hw/riscv/Kconfi
SIs to the AIA IMSIC.
We also provide "aia-guests=" parameter which can be used
to specify number of VS-level AIA IMSIC Guests MMIO pages for
each HART.
Signed-off-by: Anup Patel
---
hw/riscv/Kconfig| 1 +
hw/riscv/virt.c | 430 --
Hi Alistair,
On Sat, Oct 23, 2021 at 2:17 PM Anup Patel wrote:
>
> The advanced interrupt architecture (AIA) extends the per-HART local
> interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
> and Advanced PLIC (wired interrupt controller).
>
> Th
The RISC-V AIA specification extends RISC-V local interrupts and
introduces new CSRs. This patch adds defines for the new AIA CSRs.
Signed-off-by: Anup Patel
---
target/riscv/cpu_bits.h | 128
1 file changed, 128 insertions(+)
diff --git a/target/riscv
The AIA specification adds new CSRs for RV32 so that RISC-V hart can
support 64 local interrupts on both RV32 and RV64.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 14 +-
target/riscv/cpu_helper.c | 10 +-
target/riscv/csr.c| 560
The AIA specification defines IMSIC interface CSRs for easy access
to the per-HART IMSIC registers without using indirect xiselect and
xireg CSRs. This patch implements the AIA IMSIC interface CSRs.
Signed-off-by: Anup Patel
---
target/riscv/csr.c | 199
We add "x-aia" command-line option for RISC-V HART using which
allows users to force enable CPU AIA CSRs without changing the
interrupt controller available in RISC-V machine.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +
target/riscv/cpu.
devices expect AIA CSRs implemented by RISC-V CPUs.
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 11 +++
target/riscv/cpu.h | 5 +
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv
We have two new machine options "aia" and "aia-guests" available
for the RISC-V virt machine so let's document these options.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
docs/system/riscv/virt.rst | 16
1 file changed, 16 insertions(+)
The hgeie and hgeip CSRs are required for emulating an external
interrupt controller capable of injecting virtual external
interrupt to Guest/VM running at VS-level.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c| 61
ted more granular patches
- Added HGEIE and HGEIP CSR emulation for H-extension
- Added APLIC emulation
- Added IMSIC emulation
Anup Patel (22):
target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64
HS-mode
target/riscv: Implement SGEIP bit in hip and hie CSRs
target/risc
A hypervsior can optionally take guest external interrupts using
SGEIP bit of hip and hie CSRs.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 3 ++-
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 18 +++---
3 files changed, 16
We should be returning illegal instruction trap when RV64 HS-mode tries
to access RV32 HS-mode CSR.
Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 2 +-
1 file changed, 1
The AIA hvictl and hviprioX CSRs allow hypervisor to control
interrupts visible at VS-level. This patch implements AIA hvictl
and hviprioX CSRs.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h | 1 +
target/riscv/csr.c | 126 +
target/riscv
console input and other I/O events.
To solve this, we check and inject interrupt after setting V=1.
Signed-off-by: Anup Patel
---
target/riscv/cpu_helper.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index bb7ac9890b
12 so we
add dummy implementation (i.e. read zero and ignore write) of AIA
interrupt filtering CSRs.
Signed-off-by: Anup Patel
---
target/riscv/csr.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 46d0cabbde..43ae444774 1
.
Signed-off-by: Anup Patel
---
target/riscv/cpu.c| 19 +++
target/riscv/cpu.h| 12 ++
target/riscv/cpu_helper.c | 241 +-
target/riscv/machine.c| 3 +
4 files changed, 245 insertions(+), 30 deletions(-)
diff --git a/target/riscv/cpu.c b/target
adds device emulation for RISC-V AIA APLIC.
Signed-off-by: Anup Patel
---
hw/intc/Kconfig | 3 +
hw/intc/meson.build | 1 +
hw/intc/riscv_aplic.c | 970 ++
include/hw/intc/riscv_aplic.h | 73 +++
4 files changed, 1047 insertions
The AIA specification introduces new [m|s|vs]topi CSRs for
reporting pending local IRQ number and associated IRQ priority.
Signed-off-by: Anup Patel
---
target/riscv/csr.c | 154 +
1 file changed, 154 insertions(+)
diff --git a/target/riscv/csr.c b
.
This patch adds device emulation for RISC-V AIA IMSIC which
supports M-level, S-level, and VS-level MSIs.
Signed-off-by: Anup Patel
---
hw/intc/Kconfig | 3 +
hw/intc/meson.build | 1 +
hw/intc/riscv_imsic.c | 443 ++
include
We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 3
We should use the AIA INTC compatible string in the CPU INTC
DT nodes when the CPUs support AIA feature. This will allow
Linux INTC driver to use AIA local interrupt CSRs.
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
hw/riscv/virt.c | 13 +++--
1 file changed, 11
The AIA device emulation (such as AIA IMSIC) should be able to set
(or provide) AIA ireg read-modify-write callback for each privilege
level of a RISC-V HART.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h| 19 +++
target/riscv/cpu_helper.c | 14 ++
2 files
We extend virt machine to emulate AIA APLIC devices only when
"aia=aplic" parameter is passed along with machine name in QEMU
command-line. When "aia=none" or not specified then we fallback
to original PLIC device emulation.
Signed-off-by: Anup Patel
---
hw/riscv/Kconfi
SIs to the AIA IMSIC.
We also provide "aia-guests=" parameter which can be used
to specify number of VS-level AIA IMSIC Guests MMIO pages for
each HART.
Signed-off-by: Anup Patel
---
hw/riscv/Kconfig| 1 +
hw/riscv/virt.c | 430 --
The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs
which allow indirect access to interrupt priority arrays and per-HART
IMSIC registers. This patch implements AIA xiselect and xireg CSRs.
Signed-off-by: Anup Patel
---
target/riscv/cpu.h | 7 ++
target/riscv/csr.c
On Sat, Jan 8, 2022 at 12:05 PM Frank Chang wrote:
>
> Anup Patel 於 2021年12月30日 週四 下午8:55寫道：
>>
>> From: Anup Patel
>>
>> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
>> interrupt controller for wired interrupts called APLIC (Advanced
&g
On Wed, Jan 5, 2022 at 9:01 AM Frank Chang wrote:
>
> Anup Patel 於 2021年12月30日 週四 下午8:53寫道：
>>
>> From: Anup Patel
>>
>> The AIA specification defines IMSIC interface CSRs for easy access
>> to the per-HART IMSIC registers without using indirect xiselect and
On Fri, Jan 7, 2022 at 2:23 PM Frank Chang wrote:
>
> Anup Patel 於 2021年12月30日 週四 下午8:55寫道：
>>
>> From: Anup Patel
>>
>> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
>> interrupt controller for wired interrupts called APLIC (Advanced
&g
On Fri, Jan 7, 2022 at 7:45 AM Atish Patra wrote:
>
> The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
> and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
> extension allows the perf to handle overflow interrupts and filtering
> support. This patch provides a fra
On Mon, Jan 10, 2022 at 6:38 PM Frank Chang wrote:
>
> Anup Patel 於 2021年12月30日 週四 下午8:38寫道：
>>
>> From: Anup Patel
>>
>> The AIA spec defines programmable 8-bit priority for each local interrupt
>> at M-level, S-level and VS-level so we extend local int
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> Reviewed-by: Alistair Francis
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> hw/intc/sifive_plic.c| 20 +++---
> hw/riscv/boot.c | 16 ++
On Wed, Jan 12, 2022 at 1:44 PM Yifei Jiang wrote:
>
> Add riscv kvm support in meson.build file.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> meson.build | 2 ++
> 1 file changed,
On Wed, Jan 12, 2022 at 5:46 PM Frank Chang wrote:
>
> Anup Patel 於 2021年12月30日 週四 下午8:47寫道：
>>
>> From: Anup Patel
>>
>> The AIA specification introduces new [m|s|vs]topi CSRs for
>> reporting pending local IRQ number and associated IRQ priority.
>>
&
On Wed, Jan 12, 2022 at 8:30 AM Frank Chang wrote:
>
> On Wed, Jan 12, 2022 at 1:18 AM Anup Patel wrote:
>>
>>
>>
>> On Mon, Jan 10, 2022 at 6:38 PM Frank Chang wrote:
>> >
>> > Anup Patel 於 2021年12月30日 週四 下午8:38寫道：
>> >>
>> &g
On Wed, Jan 12, 2022 at 6:45 PM Frank Chang wrote:
>
> Anup Patel 於 2021年12月30日 週四 下午8:41寫道：
>>
>> From: Anup Patel
>>
>> The AIA hvictl and hviprioX CSRs allow hypervisor to control
>> interrupts visible at VS-level. This patch implements AIA hvictl
>&
On Thu, Jan 13, 2022 at 12:56 PM Frank Chang wrote:
>
> Anup Patel 於 2021年12月30日 週四 下午9:00寫道：
>>
>> From: Anup Patel
>>
>> The RISC-V AIA (Advanced Interrupt Architecture) defines a new
>> interrupt controller for MSIs (message signal interrupts) call
On Thu, Feb 10, 2022 at 1:58 PM Atish Patra wrote:
>
> On Mon, Feb 7, 2022 at 10:51 PM Alistair Francis wrote:
> >
> > On Tue, Feb 8, 2022 at 2:16 PM Alistair Francis
> > wrote:
> > >
> > > On Sat, Feb 5, 2022 at 3:47 AM Anup Patel wrote:
> > &
On Wed, Feb 16, 2022 at 5:39 AM Atish Patra wrote:
>
> The Linux kernel parses the ISA extensions from "riscv,isa" DT
> property. It used to parse only the single letter base extensions
> until now. A generic ISA extension parsing framework was proposed[1]
> recently that can parse multi-letter IS
r=format=]
> >
> > ../hw/riscv/virt.c:569:49: error: format '%lx' expects argument of
> > type 'long unsigned int', but argument 2 has type 'hwaddr' {aka 'long
> > long unsigned int'} [-Werror=format=]
> >
> > Printing h
From: Anup Patel
The advanced interrupt architecture (AIA) extends the per-HART local
interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
and Advanced PLIC (wired interrupt controller).
The latest AIA draft specification can be found here:
https://github.com/riscv/riscv-aia
From: Anup Patel
We extend virt machine to emulate both AIA IMSIC and AIA APLIC
devices only when "aia=aplic-imsic" parameter is passed along
with machine name in the QEMU command-line. The AIA IMSIC is
only a per-HART MSI controller so we use AIA APLIC in MSI-mode
to forward
From: Anup Patel
We extend virt machine to emulate AIA APLIC devices only when
"aia=aplic" parameter is passed along with machine name in QEMU
command-line. When "aia=none" or not specified then we fallback
to original PLIC device emulation.
Signed-off-by: Anup Patel
Signe
From: Anup Patel
The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for MSIs (message signal interrupts) called
IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC
is per-HART device and also suppport virtualizaiton of MSIs using
dedicated VS-level
From: Anup Patel
We have two new machine options "aia" and "aia-guests" available
for the RISC-V virt machine so let's document these options.
Signed-off-by: Anup Patel
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
---
docs/s
From: Anup Patel
To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
We also add a detailed source level comments about limit defines which
impact the physical address space utilization.
Signed-off-by
://github.com/avpatel/qemu.git
The RISC-V nested virtualization was tested on QEMU RISC-V using
Xvisor RISC-V which has required hypervisor support to run another
hypervisor as Guest/VM.
Anup Patel (4):
target/riscv: Fix csr number based privilege checking
target/riscv: Fix hstatus.GVA bit setting for
When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
the riscv_csrrw_check() function should generate virtual instruction
trap instead illegal instruction trap.
Fixes: 533c91e8f22c ("target/riscv: Use RISCVException enum for
CSR access")
Signed-off-by: Anup Patel
---
ta
mstatus.TVM or hstatus.VTVM).
We improve setting of [m|s]tval CSRs for all types of illegal and
virtual instruction traps.
Signed-off-by: Anup Patel
---
target/riscv/cpu.c| 2 ++
target/riscv/cpu.h| 8 +++-
target/riscv/cpu_helper.c | 1 +
target/riscv/translate.c | 17
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Signed-off-by: Anup Patel
---
target/riscv/cpu_helper.c | 168 +-
target/riscv
g GVA")
Signed-off-by: Anup Patel
---
target/riscv/cpu_helper.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e1aa4f2097..d83579accf 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1434,7 +1434
This series covers few fixes discovered while trying to detect priv spec
version on QEMU virt machine and QEMU sifive_u machine.
These patches can also be found in riscv_priv_version_fixes_v1 branch at:
https://github.com/avpatel/qemu.git
Anup Patel (3):
target/riscv: Don't force update
t latest priv spec version (i.e. v1.12)
for base rv64/rv32 cpu and riscv_cpu_realize() will override priv
spec version only when "cpu->cfg.priv_spec != NULL".
Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12")
Signed-off-by: Anup Patel
---
target
tree")
Signed-off-by: Anup Patel
---
target/riscv/cpu.c | 36 +++-
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 02ee7d45d8..d8c88b96bc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -
The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
implementation that don't want to implement can simply have a dummy
mcountinhibit which always zero.
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in
the CSR ops.")
Signed-off-by: Anup Pat
riv spec version for all extensions.
>>
>> Fixes: a775398be2e ("target/riscv: Add isa extenstion strings to the
>> device tree")
>> Signed-off-by: Anup Patel
>> ---
>> target/riscv/cpu.c | 36 +++-
>> 1 file changed,
On Thu, May 5, 2022 at 3:21 PM Alistair Francis wrote:
>
> On Fri, Apr 29, 2022 at 1:38 PM Anup Patel wrote:
> >
> > Currently, QEMU does not set hstatus.GVA bit for traps taken from
> > HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
> > on QEM
On Thu, May 5, 2022 at 4:24 PM Daniel P. Berrangé wrote:
>
> On Thu, May 05, 2022 at 07:36:51PM +1000, Alistair Francis wrote:
> > On Tue, May 3, 2022 at 5:57 PM Atish Patra wrote:
> > >
> > > On Tue, Apr 19, 2022 at 5:26 PM Atish Patra wrote:
> > > >
> > > > On Tue, Apr 19, 2022 at 9:51 AM Dani
On Mon, May 9, 2022 at 2:54 PM Alistair Francis wrote:
>
> On Thu, May 5, 2022 at 12:36 PM Anup Patel wrote:
> >
> > On Thu, May 5, 2022 at 3:21 PM Alistair Francis
> > wrote:
> > >
> > > On Fri, Apr 29, 2022 at 1:38 PM Anup Patel
> > >
-032.pdf)
Based on above, we update QEMU RISC-V to:
1) Have separate config options for Smaia and Ssaia extensions
which replace RISCV_FEATURE_AIA in CPU features
2) Not generate AIA INTC compatible string in virt machine
Signed-off-by: Anup Patel
Reviewed-by: Andrew Jones
---
hw/intc
On Fri, Aug 19, 2022 at 10:24 AM Weiwei Li wrote:
>
>
> 在 2022/8/19 上午11:09, Anup Patel 写道:
> > The arch review of AIA spec is completed and we now have official
> > extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode
> > AIA CSRs).
> >
> &g
-032.pdf)
Based on above, we update QEMU RISC-V to:
1) Have separate config options for Smaia and Ssaia extensions
which replace RISCV_FEATURE_AIA in CPU features
2) Not generate AIA INTC compatible string in virt machine
Signed-off-by: Anup Patel
Reviewed-by: Andrew Jones
---
Changes since v1
On Fri, Aug 19, 2022 at 8:40 PM Richard Henderson
wrote:
>
> On 8/19/22 00:31, Anup Patel wrote:
> > static int aia_hmode(CPURISCVState *env, int csrno)
> > {
> > -if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> > +CPUState *cs = env_cpu(env);
> &g
-032.pdf)
Based on above, we update QEMU RISC-V to:
1) Have separate config options for Smaia and Ssaia extensions
which replace RISCV_FEATURE_AIA in CPU features
2) Not generate AIA INTC compatible string in virt machine
Signed-off-by: Anup Patel
Reviewed-by: Andrew Jones
---
Changes since v2
On Mon, Oct 31, 2022 at 6:25 AM Alistair Francis wrote:
>
> On Fri, Oct 28, 2022 at 2:53 AM Anup Patel wrote:
> >
> > The time CSR will wrap-around immediately after reaching UINT64_MAX
> > so we don't need to re-start QEMU timer when timecmp == UINT64_MAX
>
On Wed, Nov 2, 2022 at 5:40 AM Alistair Francis wrote:
>
> On Mon, Oct 31, 2022 at 1:49 PM Anup Patel wrote:
> >
> > On Mon, Oct 31, 2022 at 6:25 AM Alistair Francis
> > wrote:
> > >
> > > On Fri, Oct 28, 2022 at 2:53 AM Anup Patel
> > > w
The htimedelta[h] CSR has impact on the VS timer comparison so we
should call riscv_timer_write_timecmp() whenever htimedelta changes.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/
Added detailed comment block in PATCH4
Anup Patel (5):
target/riscv: Typo fix in sstc() predicate
target/riscv: Update VS timer whenever htimedelta changes
target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP
target/riscv: No need to re-start QEMU timer wh
We should use "&&" instead of "&" when checking hcounteren.TM and
henvcfg.STCE bits.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/csr.c | 2 +-
1 file changed, 1
Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
for VSTIP.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/cp
as zero in htinst CSR for guest MMIO emulation
which makes MMIO emulation in hypervisor slow and also breaks nested
virtualization.
Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc")
Signed-off-by: Anup Patel
---
target/riscv/insn_trans/trans_rva.c.in
The time CSR will wrap-around immediately after reaching UINT64_MAX
so we don't need to re-start QEMU timer when timecmp == UINT64_MAX
in riscv_timer_write_timecmp().
Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
---
target/riscv/time_helper.c | 24
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