This series does fixes and improvements to have nested virtualization on QEMU RISC-V. The first two patches are fixes whereas the second two patches make nested virtualization performance better on for QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v1 branch at: https://github.com/avpatel/qemu.git The RISC-V nested virtualization was tested on QEMU RISC-V using Xvisor RISC-V which has required hypervisor support to run another hypervisor as Guest/VM. Anup Patel (4): target/riscv: Fix csr number based privilege checking target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode target/riscv: Set [m|s]tval for both illegal and virtual instruction traps target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() target/riscv/cpu.c | 2 + target/riscv/cpu.h | 8 +- target/riscv/cpu_helper.c | 170 ++++++++++++++++++++++++++++++++++++-- target/riscv/csr.c | 8 +- target/riscv/instmap.h | 41 +++++++++ target/riscv/translate.c | 17 +++- 6 files changed, 234 insertions(+), 12 deletions(-) -- 2.34.1
