Re: [Qemu-devel] [PATCH v1 0/3] Extend the performance monitoring registers

Alistair, On Feb 03 16:34, Alistair Francis wrote: > This patch set is based on the patch sent by Christopher Covington and > written by Aaron Lindsay which was sent as an RFC (Implement remaining > PMU functionality). These patches look like a good start to improving the PMU support, t

Re: [Qemu-devel] [PATCH v1 0/3] Extend the performance monitoring registers

On Feb 04 10:52, Alistair Francis wrote: > On Thu, Feb 4, 2016 at 5:39 AM, Aaron Lindsay wrote: > > Please add my > > Signed-off-by: Aaron Lindsay > > to all three. > > Ok, I wasn't sure what you wanted to do there. I'll add them all and > they will be th

Re: [Qemu-devel] [PATCH v2 1/5] target-arm: Add the pmceid0 and pmceid1 registers

On Feb 09 15:11, Alistair Francis wrote: > On Tue, Feb 9, 2016 at 9:19 AM, Peter Maydell > wrote: > > On 6 February 2016 at 00:55, Alistair Francis > > wrote: > >> Signed-off-by: Aaron Lindsay > >> Signed-off-by: Alistair Francis > >> Tested-by:

Plugin Memory Callback Debugging

Hello, I have been wrestling with what might be a bug in the plugin memory callbacks. The immediate error is that I hit the `g_assert_not_reached()` in the 'default:' case in qemu_plugin_vcpu_mem_cb, indicating the callback type was invalid. When breaking on this assertion in gdb, the contents of

Re: Plugin Memory Callback Debugging

Sorry, left off the very end of my timeline: On Nov 18 16:58, Aaron Lindsay wrote: > I have, so far, discovered the following timeline: > 1. My plugin receives a instruction execution callback for a load >instruction. At this time, cpu->plugin_mem_cbs points to the same >me

Re: [PATCH 2/4] translator: always pair plugin_gen_insn_{start,end} calls

On Jan 08 11:47, Emilio Cota wrote: > Related: #1381 > > Signed-off-by: Emilio Cota > --- > accel/tcg/translator.c | 15 ++- > 1 file changed, 10 insertions(+), 5 deletions(-) Tested-by: Aaron Lindsay

Re: [PATCH 1/4] plugins: fix optimization in plugin_gen_disable_mem_helpers

on. > > Related: #1381 > > Signed-off-by: Emilio Cota > --- > accel/tcg/plugin-gen.c | 26 ++ > include/qemu/plugin.h | 7 +++ > 2 files changed, 25 insertions(+), 8 deletions(-) Tested-by: Aaron Lindsay

[PATCH v3 2/8] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 65 +-- target/arm/tcg/pauth_helper.c | 2 +- 2 files changed, 63 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f0f27f259d..868d844d5a 100644 --- a/target/arm

[PATCH v3 6/8] targer/arm: Inform helpers whether a PAC instruction is 'combined'

feature for ARMv8.3. Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson --- target/arm/helper-a64.h| 4 ++ target/arm/tcg/pauth_helper.c | 71 +++--- target/arm/tcg/translate-a64.c | 20 +- 3 files changed, 72 insertions(+), 23 deletions(-) dif

[PATCH v3 0/8] Implement Most ARMv8.3 Pointer Authentication Features

code formatting fixes and logic simplifications [0] - https://lists.nongnu.org/archive/html/qemu-devel/2023-02/msg06494.html Aaron Lindsay (8): target/arm: Add ID_AA64ISAR2_EL1 target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection target/arm: Implement v8.3 QARMA3 PAC cipher targe

[PATCH v3 3/8] target/arm: Implement v8.3 QARMA3 PAC cipher

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/pauth_helper.c | 54 --- 1 file changed, 44 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index

[PATCH v3 5/8] target/arm: Implement v8.3 Pauth2

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/pauth_helper.c | 33 +++-- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index

[PATCH v3 7/8] target/arm: Implement v8.3 FPAC and FPACCOMBINE

Signed-off-by: Aaron Lindsay --- target/arm/syndrome.h | 7 +++ target/arm/tcg/pauth_helper.c | 16 2 files changed, 23 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index d27d1bc31f..bf79c539d9 100644 --- a/target/arm/syndrome.h +++ b

[PATCH v3 8/8] target/arm: Add CPU property for QARMA3, enable FPACCombined by default

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 48 +++--- 2 files changed, 34 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 868d844d5a..80683c428f 100644 --- a/target/arm/cpu.h

[PATCH v3 4/8] target/arm: Implement v8.3 EnhancedPAC

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/pauth_helper.c | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 122c208de2

[PATCH v3 1/8] target/arm: Add ID_AA64ISAR2_EL1

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 1 + target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 1 + target/arm/kvm64.c | 2 ++ 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c097cae988..f0f27f259d 100644 --- a/target

Re: [PATCH v2 6/7] target/arm: Implement v8.3 FPAC and FPACCOMBINE

On Feb 22 11:37, Richard Henderson wrote: > On 2/22/23 09:35, Aaron Lindsay wrote: > > @@ -406,6 +421,16 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t > > ptr, uint64_t modifier, > > uint64_t xor_mask = MAKE_64BIT_MASK(bot_bit, top_b

Re: [PATCH v2 7/7] target/arm: Add CPU properties for most v8.3 PAC features

On Feb 22 12:14, Richard Henderson wrote: > On 2/22/23 09:35, Aaron Lindsay wrote: > > +static Property arm_cpu_pauth2_property = > > +DEFINE_PROP_BOOL("pauth2", ARMCPU, prop_pauth2, false); > > +static Property arm_cpu_pauth_fpac_property = > > +

Re: [PATCH 7/7] target/arm: Add CPU properties for most v8.3 PAC features

On Feb 13 17:11, Peter Maydell wrote: > On Thu, 2 Feb 2023 at 21:12, Aaron Lindsay > wrote: > > > > Signed-off-by: Aaron Lindsay > > --- > > target/arm/cpu.h | 5 +++ > > target/arm/cpu64.c | 81 ++ > &

Re: [PATCH 1/7] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection

On Feb 13 16:01, Peter Maydell wrote: > On Thu, 2 Feb 2023 at 21:13, Aaron Lindsay > wrote: > > +static inline bool isar_feature_aa64_pauth_epac(const ARMISARegisters *id) > > +{ > > +return isar_feature_pauth_get_features(id) == 0b0010; > > This should

[PATCH v2 1/7] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 61 +-- target/arm/helper.c | 4 +-- target/arm/pauth_helper.c | 2 +- 3 files changed, 61 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8cf70693be

[PATCH v2 4/7] target/arm: Implement v8.3 Pauth2

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/pauth_helper.c | 32 ++-- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index a83956652f..c4ee040da7 100644 --- a/target/arm

[PATCH v2 5/7] targer/arm: Inform helpers whether a PAC instruction is 'combined'

feature for ARMv8.3. Signed-off-by: Aaron Lindsay --- target/arm/helper-a64.h| 4 +++ target/arm/pauth_helper.c | 71 +++--- target/arm/translate-a64.c | 20 +-- 3 files changed, 72 insertions(+), 23 deletions(-) diff --git a/target/arm/helper-a64.h b/t

[PATCH v2 0/7] Implement Most ARMv8.3 Pointer Authentication Features

vious patchset - I'm planning to await further discussion about the appropriate way to organize them before making those changes and particularly welcome further review there. -Aaron [0] https://lists.nongnu.org/archive/html/qemu-devel/2023-02/msg00660.html Aaron Lindsay (7): target/arm:

[PATCH v2 2/7] target/arm: Implement v8.3 QARMA3 PAC cipher

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/pauth_helper.c | 50 +++ 1 file changed, 40 insertions(+), 10 deletions(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index e5206453f6..f525ef7fad 100644 --- a

[PATCH v2 7/7] target/arm: Add CPU properties for most v8.3 PAC features

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 5 +++ target/arm/cpu64.c | 81 ++ 2 files changed, 72 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9c3cbc9a29..40b4631f11 100644 --- a/target/arm/cpu.h

[PATCH v2 3/7] target/arm: Implement v8.3 EnhancedPAC

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/pauth_helper.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index f525ef7fad..a83956652f 100644 --- a/target/arm/pauth_helper.c

[PATCH v2 6/7] target/arm: Implement v8.3 FPAC and FPACCOMBINE

Signed-off-by: Aaron Lindsay --- target/arm/pauth_helper.c | 35 ++- target/arm/syndrome.h | 7 +++ 2 files changed, 37 insertions(+), 5 deletions(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index 96770d7860..db6cf9b5bc 100644

[BUG] AArch64 boot hang with -icount and -smp >1 (iothread locking issue?)

Pavel's "replay: rewrite async event handling" commit [2]. Commits prior to that one boot successfully (neither assertions nor hangs) with `-icount 0 -smp 2`. I've looked over these two commits ([1], [2]), but it is not obvious to me how/why they might be interacting to produce the

Re: [BUG] AArch64 boot hang with -icount and -smp >1 (iothread locking issue?)

On Oct 21 17:00, Peter Maydell wrote: > On Fri, 21 Oct 2022 at 16:48, Aaron Lindsay > wrote: > > > > Hello, > > > > I am encountering one or more bugs when using -icount and -smp >1 that I am > > attempting to sort out. My current theory is that it is an

[PATCH 3/7] target/arm: Implement v8.3 EnhancedPAC

Signed-off-by: Aaron Lindsay --- target/arm/pauth_helper.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index f525ef7fad..a83956652f 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c

[PATCH 5/7] targer/arm: Inform helpers whether a PAC instruction is 'combined'

feature for ARMv8.3. Signed-off-by: Aaron Lindsay --- target/arm/helper-a64.h| 4 +++ target/arm/pauth_helper.c | 63 -- target/arm/translate-a64.c | 20 ++-- 3 files changed, 68 insertions(+), 19 deletions(-) diff --git a/target/arm/helper-a64.h b/t

[PATCH 0/7] Implement Most ARMv8.3 Pointer Authentication Features

Hello, I've taken a first pass at implementing many of the ARMv8.3 Pointer Authentication features and welcome your review. Thanks! -Aaron Aaron Lindsay (7): target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection target/arm: Implement v8.3 QARMA3 PAC cipher target/arm: Implement

[PATCH 7/7] target/arm: Add CPU properties for most v8.3 PAC features

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 5 +++ target/arm/cpu64.c | 81 ++ 2 files changed, 72 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9be59163ff..a9420bae67 100644 --- a/target/arm/cpu.h

[PATCH 1/7] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 57 --- target/arm/helper.c | 4 +-- target/arm/pauth_helper.c | 4 +-- 3 files changed, 58 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8cf70693be

[PATCH 2/7] target/arm: Implement v8.3 QARMA3 PAC cipher

Signed-off-by: Aaron Lindsay --- target/arm/pauth_helper.c | 48 +++ 1 file changed, 39 insertions(+), 9 deletions(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index a0c9bea06b..f525ef7fad 100644 --- a/target/arm/pauth_helper.c +++ b

[PATCH 4/7] target/arm: Implement v8.3 Pauth2

Signed-off-by: Aaron Lindsay --- target/arm/pauth_helper.c | 29 +++-- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index a83956652f..6ebf6df75c 100644 --- a/target/arm/pauth_helper.c +++ b/target

[PATCH 6/7] target/arm: Implement v8.3 FPAC and FPACCOMBINE

Signed-off-by: Aaron Lindsay --- target/arm/pauth_helper.c | 26 ++ target/arm/syndrome.h | 6 ++ 2 files changed, 32 insertions(+) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index 66dc90a289..3a2772de0e 100644 --- a/target/arm

Re: Plugin Memory Callback Debugging

Emilio, On Dec 18 00:24, Emilio Cota wrote: > On Tue, Nov 29, 2022 at 15:37:51 -0500, Aaron Lindsay wrote: > (snip) > > > Does this hint that there are cases where reset cpu->plugin_mem_cbs to > > > NULL is > > > getting optimized away, but not the code to se

Plugins Not Reporting AArch64 SVE Memory Operations

Hi folks, I see there has been some previous discussion [1] about 1.5 years ago around the fact that AArch64 SVE instructions do not emit any memory operations via the plugin interface, as one might expect them to. I am interested in being able to more accurately trace the memory operations of SV

[PATCH v3 1/8] target/arm: Add ID_AA64ISAR2_EL1

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 1 + target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 1 + target/arm/kvm64.c | 2 ++ 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 36c608f0e6..df04c9a9ab 100644 --- a/target

[PATCH v3 6/8] targer/arm: Inform helpers whether a PAC instruction is 'combined'

feature for ARMv8.3. Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson --- target/arm/tcg/helper-a64.h| 4 ++ target/arm/tcg/pauth_helper.c | 71 +++--- target/arm/tcg/translate-a64.c | 12 +++--- 3 files changed, 68 insertions(+), 19 deletions(-) diff --

[PATCH v3 4/8] target/arm: Implement v8.3 EnhancedPAC

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/pauth_helper.c | 15 ++- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 68942015e1

[PATCH v3 8/8] target/arm: Add CPU property for QARMA3, enable FPACCombined by default

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 48 +++--- 2 files changed, 34 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 22dd898577..0c4c6c9c82 100644 --- a/target/arm/cpu.h

[PATCH v3 5/8] target/arm: Implement v8.3 Pauth2

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/pauth_helper.c | 33 +++-- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index

[PATCH v3 3/8] target/arm: Implement v8.3 QARMA3 PAC cipher

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/pauth_helper.c | 54 --- 1 file changed, 44 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index

[PATCH v3 7/8] target/arm: Implement v8.3 FPAC and FPACCOMBINE

Signed-off-by: Aaron Lindsay --- target/arm/syndrome.h | 7 +++ target/arm/tcg/pauth_helper.c | 16 2 files changed, 23 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index d27d1bc31f..bf79c539d9 100644 --- a/target/arm/syndrome.h +++ b

[PATCH v3 2/8] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 65 +-- target/arm/tcg/pauth_helper.c | 2 +- 2 files changed, 63 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index df04c9a9ab..22dd898577 100644 --- a/target/arm

[PATCH v3 0/8] Implement Most ARMv8.3 Pointer Authentication Features

decoding PAC branch instructions) [0] - https://lists.nongnu.org/archive/html/qemu-devel/2023-02/msg06494.html Aaron Lindsay (8): target/arm: Add ID_AA64ISAR2_EL1 target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection target/arm: Implement v8.3 QARMA3 PAC cipher target/arm: Implement v8.3

Re: [PATCH v3 1/8] target/arm: Add ID_AA64ISAR2_EL1

On Jun 09 13:49, Richard Henderson wrote: > On 6/9/23 10:23, Aaron Lindsay wrote: > > --- a/target/arm/hvf/hvf.c > > +++ b/target/arm/hvf/hvf.c > > @@ -847,6 +847,7 @@ static bool > > hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) > >

Re: [PATCH v3 2/8] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection

On Jun 09 13:51, Richard Henderson wrote: > On 6/9/23 10:23, Aaron Lindsay wrote: > > +static inline int isar_feature_pauth_get_features(const ARMISARegisters > > *id) > > +{ > > +if (isar_feature_aa64_pauth_arch_qarma5(id)) { > > +return FIELD_EX64(id

Re: [Qemu-devel] [PULL 03/12] target-arm: Add support for PMU register PMINTENSET_EL1

Wei, Peter, On Feb 10 18:07, Peter Maydell wrote: > From: Wei Huang > > This patch adds access support for PMINTENSET_EL1. > > Signed-off-by: Wei Huang > Reviewed-by: Peter Maydell > Message-id: 1486504171-26807-4-git-send-email-...@redhat.com > Signed-off-by: Peter Maydell > --- > target/a

Re: [Qemu-devel] [PATCH v3 2/2] avx2 configure: Use primitives in test

On Jun 10 12:16, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > Use the avx2 primitives during the test, thus making sure that the > compiler and assembler could actually use avx2. > > This also detects the failure case on gcc 4.8.x with -save-temps > and avoids the nee

Re: [Qemu-devel] [PATCH v3 2/2] avx2 configure: Use primitives in test

On Jul 14 14:33, Dr. David Alan Gilbert wrote: > * Aaron Lindsay (alind...@codeaurora.org) wrote: > > I'm configuring with: > > # ./configure \ > > --static \ > > --disable-gtk \ > > --target-list=aarch64-softmmu > > Does it work if you co

Re: [Qemu-devel] [PATCH v3 2/2] avx2 configure: Use primitives in test

On Jul 14 14:23, Peter Maydell wrote: > On 14 July 2016 at 14:15, Paolo Bonzini wrote: > > On 14/07/2016 15:13, Aaron Lindsay wrote: > >> I'm configuring with: > >> # ./configure \ > >> --static \ > >> --disable-gtk \ > >>

Re: [Qemu-devel] [PATCH v3 2/2] avx2 configure: Use primitives in test

On Jul 14 15:35, Peter Maydell wrote: > On 14 July 2016 at 15:27, Aaron Lindsay wrote: > > On Jul 14 14:23, Peter Maydell wrote: > >> On 14 July 2016 at 14:15, Paolo Bonzini wrote: > >> > On 14/07/2016 15:13, Aaron Lindsay wrote: > >> >>

Re: [Qemu-devel] [PATCH v3 2/2] avx2 configure: Use primitives in test

On Jul 14 16:05, Dr. David Alan Gilbert wrote: > * Aaron Lindsay (alind...@codeaurora.org) wrote: > > On Jul 14 14:33, Dr. David Alan Gilbert wrote: > > > * Aaron Lindsay (alind...@codeaurora.org) wrote: > > > > I'm configuring with: > >

[Qemu-devel] [PATCH] avx2 configure: Disable if static build

{ (gdb) bt #0 buffer_find_nonzero_offset_ifunc () at ./util/cutils.c:333 #1 0x00939c58 in __libc_start_main () #2 0x00419337 in _start () Signed-off-by: Aaron Lindsay --- configure | 17 ++--- 1 file changed, 10 insertions(+), 7 deletions

[Qemu-devel] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0]

A53 advertises ARM_FEATURE_PMU, but wasn't initializing pmceid[01] Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 2 +- target/arm/cpu64.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 04b062c..921b028 100644 --- a/t

[Qemu-devel] [PATCH 00/13] More fully implement ARM PMUv3

ut it doesn't seem like the right way to handle this. I would like to eventually add sending interrupts on counter overflow. Suggestions for the best direction to handle this are most welcome. Thanks for any feedback, Aaron Aaron Lindsay (13): target/arm: A53: Initialize PMCEID[0]

[Qemu-devel] [PATCH 02/13] target/arm: Check PMCNTEN for whether PMCCNTR is enabled

Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8cb7a94..391 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -964,7 +964,7 @@ static inline bool

[Qemu-devel] [PATCH 03/13] target/arm: Reorganize PMCCNTR read, write, sync

pmccntr_read and pmccntr_write contained duplicate code that was already being handled by pmccntr_sync. This also moves the calls to get the clock inside the 'if' statement so they are not executed if not needed. Signed-off-by: Aaron Lindsay --- target/arm/hel

[Qemu-devel] [PATCH 04/13] target/arm: Mask PMU register writes based on PMCR_EL0.N

This is in preparation for enabling counters other than PMCCNTR Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 24 +++- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 390256b..e8189b8 100644 --- a/target

[Qemu-devel] [PATCH 07/13] target/arm: Implement PMOVSSET

Also modify it to be stored as a uint64_t Signed-off-by: Aaron Lindsay --- target/arm/cpu.h| 2 +- target/arm/helper.c | 27 --- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ae2a294..f3524f6 100644 --- a

[Qemu-devel] [PATCH 05/13] target/arm: Allow AArch32 access for PMCCFILTR

Also fix the existing bitmask for writes. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 23 ++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e8189b8..530fc7c 100644 --- a/target/arm/helper.c +++ b

[Qemu-devel] [PATCH 08/13] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled

Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9c01269..5d07f72 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -975,17 +975,22 @@ static

[Qemu-devel] [PATCH 06/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0

mechanism for handling this? Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 4 +++ target/arm/cpu.h | 15 +++ target/arm/helper.c| 73 +++--- target/arm/kvm64.c | 2 ++ target/arm/machine.c | 2 ++ target/arm/op_helper.c

[Qemu-devel] [PATCH 13/13] target/arm: Implement PMSWINC

Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 40 ++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a15b932..2c51f92 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -907,6

[Qemu-devel] [PATCH 09/13] target/arm: Add array for supported PMU events, generate PMCEID[01]

This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Signed-off-by: Aaron Lindsay --- target/arm/cpu.c

[Qemu-devel] [PATCH 10/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER

Add arrays to hold the registers, the definitions themselves, access functions, and add logic to reset counters when PMCR.P is set. Signed-off-by: Aaron Lindsay --- target/arm/cpu.h| 7 +- target/arm/helper.c | 187 2 files changed, 179

[Qemu-devel] [PATCH 11/13] target/arm: PMU: Add instruction and cycle events

The instruction event is only enabled when icount is used, cycles are always supported. Note: Setting can_do_io=1 should not be done here. It is ugly and wrong, but I am not sure of the proper way to handle this (See 'target/arm: Filter cycle counter based on PMCCFILTR_EL0') Signed-off

[Qemu-devel] [PATCH 12/13] target/arm: PMU: Set PMCR.N to 4

This both advertises that we support four counters and adds them to the implementation because the PMU_NUM_COUNTERS macro reads this value from the PMCR. Signed-off-by: Aaron Lindsay --- target/arm/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm

[Qemu-devel] [RFC] Pointers for implementing AArch64 PMU instruction counter?

I am interested in implementing an instruction counter to augment the ongoing (mostly cycle-counter) PMU work on AArch64. The icount infrastructure seems like the logical source for the instruction counts, but I have a couple of implementation-related questions: 1. It looks like cpu_get_icount_raw

Re: [Qemu-devel] [PULL 08/24] tcg: drop global lock during TCG code execution

On Feb 27 14:39, Alex Bennée wrote: > > Laurent Desnogues writes: > > > Hello, > > > > On Fri, Feb 24, 2017 at 12:20 PM, Alex Bennée > > wrote: > >> From: Jan Kiszka > >> > >> This finally allows TCG to benefit from the iothread introduction: Drop > >> the global mutex while running pure TCG

Re: [Qemu-devel] [PATCH v2 00/13] More fully implement ARM PMUv3

ale. -Aaron On Sep 29 22:08, Aaron Lindsay wrote: > The ARM PMU implementation currently contains a basic cycle counter, but it is > often useful to gather counts of other events and filter them based on > execution mode. These patches flesh out the implementations of various PMU > reg

Re: [Qemu-devel] [PATCH v2 00/13] More fully implement ARM PMUv3

On Oct 09 19:27, Peter Maydell wrote: > On 9 October 2017 at 15:46, Aaron Lindsay wrote: > > Unfortunately I'm not sure who to add other than the current recipients, > > but I'm eager for feedback and would love to work this into something > > that will allow for

Re: [Qemu-devel] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0]

On Oct 09 19:19, Peter Maydell wrote: > On 19 April 2017 at 18:41, Aaron Lindsay wrote: > > A53 advertises ARM_FEATURE_PMU, but wasn't initializing pmceid[01] > > > > Signed-off-by: Aaron Lindsay > > --- > > target/arm/cpu.c | 2 +- > > targe

Re: [Qemu-devel] [PATCH v8 08/13] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0

On Nov 30 16:14, Peter Maydell wrote: > On Tue, 20 Nov 2018 at 21:26, Aaron Lindsay > wrote: > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > > index 50de58e4a2..32c3397948 100644 > > --- a/target/arm/cpu.h > > +++ b/target/arm/cpu.h > > @@ -993,6 +993,

Re: [Qemu-devel] [PATCH v8 07/13] target-arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]

On Nov 30 16:10, Peter Maydell wrote: > On Tue, 20 Nov 2018 at 21:26, Aaron Lindsay > wrote: > > > > Signed-off-by: Aaron Lindsay > > --- > > target/arm/cpu.h| 4 ++-- > > target/arm/helper.c | 12 ++-- > > 2 files changed, 12 insertio

Re: [Qemu-devel] [PATCH v8 07/13] target-arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]

On Dec 03 16:57, Richard Henderson wrote: > On 12/3/18 4:19 PM, Peter Maydell wrote: > > On Mon, 3 Dec 2018 at 20:45, Aaron Lindsay > > wrote: > >> > >> On Nov 30 16:10, Peter Maydell wrote: > >>> PMCEID2 and PMCEID3 are only defined from ARMv8.1; b

[Qemu-devel] [PATCH v9 01/14] migration: Add post_save function to VMStateDescription

In some cases it may be helpful to modify state before saving it for migration, and then modify the state back after it has been saved. The existing pre_save function provides half of this functionality. This patch adds a post_save function to provide the second half. Signed-off-by: Aaron Lindsay

[Qemu-devel] [PATCH v9 00/14] More fully implement ARM PMUv3

.html Aaron Lindsay (14): migration: Add post_save function to VMStateDescription target/arm: Reorganize PMCCNTR accesses target/arm: Swap PMU values before/after migrations target/arm: Filter cycle counter based on PMCCFILTR_EL0 target/arm: Allow AArch32 access for PMCCFILTR targe

[Qemu-devel] [PATCH v9 02/14] target/arm: Reorganize PMCCNTR accesses

register value and the last underlying cycle count - this ensures time isn't lost and will also allow us to access the 'old' architectural register value in order to detect overflows in later patches. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Mayde

[Qemu-devel] [PATCH v9 04/14] target/arm: Filter cycle counter based on PMCCFILTR_EL0

Rename arm_ccnt_enabled to pmu_counter_enabled, and add logic to only return 'true' if the specified counter is enabled and neither prohibited or filtered. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target

[Qemu-devel] [PATCH v9 03/14] target/arm: Swap PMU values before/after migrations

r the state is saved/restored. By doing this and adding raw read/write functions for the affected registers, we avoid migration-related inconsistencies. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 6 -- target/arm/machine.c

[Qemu-devel] [PATCH v9 10/14] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER

Add arrays to hold the registers, the definitions themselves, access functions, and logic to reset counters when PMCR.P is set. Update filtering code to support counters other than PMCCNTR. Support migration with raw read/write functions. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay

[Qemu-devel] [PATCH v9 05/14] target/arm: Allow AArch32 access for PMCCFILTR

Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 27 ++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ddb47813d2..0aff261528 100644 --- a

[Qemu-devel] [PATCH v9 07/14] target/arm: Define FIELDs for ID_DFR0

This is immediately necessary for the PMUv3 implementation to check ID_DFR0.PerfMon to enable/disable specific features, but defines the full complement of fields for possible future use elsewhere. Signed-off-by: Aaron Lindsay --- target/arm/cpu.h | 8 1 file changed, 8 insertions

[Qemu-devel] [PATCH v9 06/14] target/arm: Implement PMOVSSET

Add an array for PMOVSSET so we only define it for v7ve+ platforms Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson --- target/arm/helper.c | 28 1 file changed, 28 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0aff261528

[Qemu-devel] [PATCH v9 12/14] target/arm: PMU: Set PMCR.N to 4

This both advertises that we support four counters and enables them because the pmu_num_counters() reads this value from PMCR. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 10 +- 1 file changed, 5 insertions(+), 5

[Qemu-devel] [PATCH v9 08/14] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]

Signed-off-by: Aaron Lindsay --- target/arm/cpu.h| 4 ++-- target/arm/helper.c | 18 -- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 304e6e47b3..4216fe22db 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h

[Qemu-devel] [PATCH v9 09/14] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0

s are supported at runtime, generate it dynamically. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/cpu.c| 19 +-- target/arm/cpu.h| 10 target/arm/cpu64.c | 4 target/arm/helper.c | 57 + 4

[Qemu-devel] [PATCH v9 11/14] target/arm: PMU: Add instruction and cycle events

The instruction event is only enabled when icount is used, cycles are always supported. Always defining get_cycle_count (but altering its behavior depending on CONFIG_USER_ONLY) allows us to remove some CONFIG_USER_ONLY #defines throughout the rest of the code. Signed-off-by: Aaron Lindsay

[Qemu-devel] [PATCH v9 13/14] target/arm: Implement PMSWINC

Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson --- target/arm/helper.c | 39 +-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 724c2f1d69..3906b6c7a4 100644 --- a/target/arm

[Qemu-devel] [PATCH v9 14/14] target/arm: Send interrupts on PMU counter overflow

Setup a QEMUTimer to get a callback when we expect counters to next overflow and trigger an interrupt at that time. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay --- target/arm/cpu.c| 12 + target/arm/cpu.h| 7 +++ target/arm/helper.c | 126

Re: [Qemu-devel] [PATCH v9 08/14] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]

On Dec 05 08:43, Aaron Lindsay wrote: > Signed-off-by: Aaron Lindsay > --- > target/arm/cpu.h| 4 ++-- > target/arm/helper.c | 18 -- > 2 files changed, 18 insertions(+), 4 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > inde

Re: [Qemu-devel] [PATCH v9 14/14] target/arm: Send interrupts on PMU counter overflow

On Dec 06 16:03, Peter Maydell wrote: > On Wed, 5 Dec 2018 at 13:44, Aaron Lindsay > wrote: > > > > Setup a QEMUTimer to get a callback when we expect counters to next > > overflow and trigger an interrupt at that time. > > > > Signed-off-by: Aaron Linds

[Qemu-devel] [PATCH v10 00/14] More fully implement ARM PMUv3

timer's migration is handled * Added a check against implementing PMCEID[23] if ID_DFR0.PerfMon == 0xf * Added TRACEFILT to the ID_DFR0 field definitions [1] - https://lists.gnu.org/archive/html/qemu-devel/2018-12/msg00805.html Aaron Lindsay (14): migration: Add post_save functi

[Qemu-devel] [PATCH v10 03/14] target/arm: Swap PMU values before/after migrations

r the state is saved/restored. By doing this and adding raw read/write functions for the affected registers, we avoid migration-related inconsistencies. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 6 -- target/arm/machine.c

[Qemu-devel] [PATCH v10 01/14] migration: Add post_save function to VMStateDescription

In some cases it may be helpful to modify state before saving it for migration, and then modify the state back after it has been saved. The existing pre_save function provides half of this functionality. This patch adds a post_save function to provide the second half. Signed-off-by: Aaron Lindsay

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