On 3/7/25 12:55, Philippe Mathieu-Daudé wrote:
We should be able to use the 'host' CPU with any hardware accelerator.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/arm/arm-qmp-cmds.c | 5 +++--
target/arm/cpu.c | 5 +++--
2 files changed, 6 insert
On Thu, 3 Jul 2025 at 14:45, Philippe Mathieu-Daudé wrote:
>
> On 3/7/25 12:55, Philippe Mathieu-Daudé wrote:
> > We should be able to use the 'host' CPU with any hardware accelerator.
> >
> > Signed-off-by: Philippe Mathieu-Daudé
> > Reviewed-by: Richard Henderson
> > ---
> > target/arm/arm-q
Impl for DummyState {
impl ResettablePhasesImpl for DummyState {}
-impl DeviceImpl for DummyState {
+impl DevicePropertiesImpl for DummyState {
fn properties() -> &'static [Property] {
&DUMMY_PROPERTIES
}
+}
+
+impl DeviceImpl for DummyState {
fn vm
-id: 20250703-rust_bindings_allow_unnecessary_transmutes-d614db4517a4
--
γαῖα πυρί μιχθήτω
When using an IGVM file the configuration of the system firmware is
defined by IGVM directives contained in the file. In this case the user
should not configure any pflash devices.
This commit skips initialization of the ROM mode when pflash0 is not set
then checks to ensure no pflash devices have
On 7/3/25 16:42, Ed Tanous wrote:
To support the newly added gb200 machine, add appropriate tests.
Signed-off-by: Ed Tanous
---
tests/functional/aspeed.py| 9 +--
tests/functional/meson.build | 2 ++
.../test_arm_aspeed_gb200nvl_bmc.py |
On 7/3/25 16:42, Ed Tanous wrote:
This patch series adds support for gb200-bmc, a baseboard management controller
module based on an Aspeed 2600 SOC.
v2:
- Rebase on master
- Drop duplicated patch for enabling PCA954X
- Updated commit message with source information
- Added functional tests and
On 7/3/25 16:42, Ed Tanous wrote:
Aspeed2600 has two spi lanes; Add a new struct that can mount the
second SPI.
Signed-off-by: Ed Tanous
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/arm/aspeed.c | 2 ++
include/hw/arm/aspeed.h | 2 ++
2 files changed, 4 insertions(+)
d
On 7/3/25 16:42, Ed Tanous wrote:
This patch updates the docs for support of gb200-bmc.
Signed-off-by: Ed Tanous
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
docs/system/arm/aspeed.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/aspeed.rs
On 7/3/25 16:42, Ed Tanous wrote:
GB200nvl72 is a system for for accelerated compute. This is a model for
the BMC target within the system.
This is based on the device tree aspeed-bmc-nvidia-gb200nvl-bmc.dts
from:
[1]
https://github.com/openbmc/linux/blob/dev-6.6/arch/arm/boot/dts/aspeed/aspe
On Thu, Jul 03, 2025 at 11:41:05AM +0100, Jonathan Cameron wrote:
> v17: Thanks to Eric for review
> - Add a comment to the high memory map to reduce the chance of nasty
> surprises in the future as similar to device_memory, the CXL
> Fixed Memory Windows are of variable size as so can't be rep
Fabiano Rosas writes:
> Markus Armbruster writes:
>
>> Fabiano Rosas writes:
>>
>>> Now that the TLS options have been made the same between
>>> migrate-set-parameters and query-migrate-parameters, a single type can
>>> be used. Remove MigrateSetParameters.
>>>
>>> The TLS options documentation
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Since commit 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER",
released with QEMU v8.1.0) we get pointless output:
(qemu) info opcount
[TCG profiler not compiled]
Remove that unstable and unuseful command.
Signed-off-by: Philippe Mathieu
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
TCG profiler was removed in commit 1b65b4f54c7.
Fixes: 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER")
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
---
accel/tcg/monitor.c | 27 +--
1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/accel/tcg/monitor.c b
On 7/4/2025 12:27 PM, Xiaoyao Li wrote:
On 7/4/2025 1:32 AM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Xiaoyao Li
---
accel/tcg/monitor.c | 27 +--
1 file changed, 17 insertions(+), 10 deletio
Philippe Mathieu-Daudé writes:
> Since commit 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER",
> released with QEMU v8.1.0) we get pointless output:
>
> (qemu) info opcount
> [TCG profiler not compiled]
>
> Remove that unstable and unuseful command.
>
> Signed-off-by: Philippe Mathieu-Daudé
Philippe Mathieu-Daudé writes:
> Display the CPU model in 'info cpus'. Example before:
>
> $ qemu-system-aarch64 -M xlnx-versal-virt -S -monitor stdio
> QEMU 10.0.0 monitor - type 'help' for more information
> (qemu) info cpus
> * CPU #0: thread_id=42924
>CPU #1: thread_id=42924
>CPU
On Fri, 2025-06-27 at 15:41 +0530, Ani Sinha wrote:
> On Fri, Jun 13, 2025 at 7:24 PM Roy Hopkins
> wrote:
> >
> > Adds an IGVM loader to QEMU which processes a given IGVM file and
> > applies the directives within the file to the current guest
> > configuration.
> >
> > The IGVM loader can be
On 7/2/25 12:25, Philippe Mathieu-Daudé wrote:
On 2/7/25 17:19, Richard Henderson wrote:
On 7/1/25 08:40, Philippe Mathieu-Daudé wrote:
Allocate ForceRcuNotifier on the Heap.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-accel-ops-mttcg.c | 30 --
1 fi
On Wed, 2 Jul 2025 at 13:38, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/helper-sve.h| 8 +
> target/arm/tcg/sve_helper.c| 317 +
> target/arm/tcg/translate-sve.c | 93 ++
> target/arm/tcg/sve.decode
On Wed, 2 Jul 2025 at 13:41, Richard Henderson
wrote:
>
> Implement the SVE2p1 consecutive register LD1/ST1,
> and the SME2 strided register LD1/ST1.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/helper-sve.h| 16 ++
> target/arm/tcg/sve_helper.c| 493 +
al(ts: TokenStream) -> TokenStream {
let ts = proc_macro2::TokenStream::from(ts);
let mut it = ts.into_iter();
-let expanded = BitsConstInternal::parse(&mut
it).unwrap_or_else(Into::into);
-TokenStream::from(expanded)
+BitsConstInternal::parse(&mut it)
+.unwrap_or_else(syn::Error::into_compile_error)
+.into()
}
diff --git a/rust/qemu-api-macros/src/utils.rs
b/rust/qemu-api-macros/src/utils.rs
deleted file mode 100644
index
02c91aed7f6a6d33075bbaa8b4fec4536da94e60..
--- a/rust/qemu-api-macros/src/utils.rs
+++ /dev/null
@@ -1,26 +0,0 @@
-// Procedural macro utilities.
-// Author(s): Paolo Bonzini
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-use proc_macro2::Span;
-use quote::quote_spanned;
-
-pub enum MacroError {
-Message(String, Span),
-ParseError(syn::Error),
-}
-
-impl From for MacroError {
-fn from(err: syn::Error) -> Self {
-MacroError::ParseError(err)
-}
-}
-
-impl From for proc_macro2::TokenStream {
-fn from(err: MacroError) -> Self {
-match err {
-MacroError::Message(msg, span) => quote_spanned! { span =>
compile_error!(#msg); },
-MacroError::ParseError(err) => err.into_compile_error(),
-}
-}
-}
---
base-commit: c77283dd5d79149f4e7e9edd00f65416c648ee59
change-id: 20250703-rust_macros-53d9e6a0b802
--
γαῖα πυρί μιχθήτω
On Thu, 19 Jun 2025 at 00:05, Jackson Donaldson wrote:
>
> This patch adds support for the MAX78000FTHR machine.
>
> The MAX78000FTHR contains a MAX78000 and a RISC-V core. This patch
> implements only the MAX78000, which is Cortex-M4 based.
> Details can be found at:
> https://www.analog.com/medi
On Thu, 19 Jun 2025 at 00:05, Jackson Donaldson wrote:
>
> This commit implements the Instruction Cache Controller
> for the MAX78000
>
> Signed-off-by: Jackson Donaldson
> ---
> hw/arm/Kconfig | 1 +
> hw/misc/Kconfig| 3 +
> hw/misc/max78000_icc.c |
The initialization sections in IGVM files contain configuration that
should be applied to the guest platform before it is started. This
includes guest policy and other information that can affect the security
level and the startup measurement of a guest.
This commit introduces handling of the init
On Thu, 19 Jun 2025 at 00:06, Jackson Donaldson wrote:
>
> This commit adds the Global Control Register to
> max78000_soc
>
> Signed-off-by: Jackson Donaldson
> @@ -106,13 +115,21 @@ static void max78000_soc_realize(DeviceState *dev_soc,
> Error **errp)
> }
> dev->id = g_str
On Thu, 19 Jun 2025 at 00:06, Jackson Donaldson wrote:
>
> This commit adds the instruction cache controller
> to max78000_soc
>
> Signed-off-by: Jackson Donaldson
> ---
> hw/arm/max78000_soc.c | 19 +++
> include/hw/arm/max78000_soc.h | 6 ++
> 2 files changed, 21 i
On Thu, 19 Jun 2025 at 00:06, Jackson Donaldson wrote:
>
> This commit implements UART support for the MAX78000
>
> Signed-off-by: Jackson Donaldson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Thu, 19 Jun 2025 at 00:06, Jackson Donaldson wrote:
>
> This commit adds UART to max78000_soc
>
> Signed-off-by: Jackson Donaldson
> ---
> hw/arm/max78000_soc.c | 28
> include/hw/arm/max78000_soc.h | 3 +++
> 2 files changed, 27 insertions(+), 4 deletion
On Thu, 19 Jun 2025 at 00:06, Jackson Donaldson wrote:
>
> This commit implements the Global Control Register
> for the MAX78000
>
> Signed-off-by: Jackson Donaldson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, Jul 02, 2025 at 05:02:15PM +0100, Jonathan Cameron wrote:
> From: Anisa Su
>
> Prepatory patch for following FMAPI Add/Release Patches. Refactors part
> of qmp_cxl_process_dynamic_capacity_prescriptive() into a helper
> function to create DC Event Records and insert in the event log.
>
>
On Thu, 19 Jun 2025 at 00:06, Jackson Donaldson wrote:
>
> This commit implements the True Random Number
> Generator for the MAX78000
>
> Signed-off-by: Jackson Donaldson
> static const MemoryRegionOps max78000_gcr_ops = {
> diff --git a/hw/misc/max78000_trng.c b/hw/misc/max78000_trng.c
> new f
On Thu, 19 Jun 2025 at 00:06, Jackson Donaldson wrote:
>
> This commit adds TRNG to max78000_soc
>
> Signed-off-by: Jackson Donaldson
> ---
> hw/arm/max78000_soc.c | 10 +-
> include/hw/arm/max78000_soc.h | 2 ++
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a
On Wed, Jul 02, 2025 at 05:02:17PM +0100, Jonathan Cameron wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5605 implemented per CXL r3.2 Spec Section
> 7.6.7.6.6
>
> Signed-off-by: Anisa Su
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> hw/cxl/cxl-mailbox-utils.c |
Adds a handler for the guest policy initialization IGVM section and
builds an SEV policy based on this information and the ID block
directive if present. The policy is applied using by calling
'set_guest_policy()' on the ConfidentialGuestSupport object.
Signed-off-by: Roy Hopkins
Acked-by: Michae
On Wed, Jul 02, 2025 at 05:02:16PM +0100, Jonathan Cameron wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5604 implemented per CXL r3.2 Spec Section
> 7.6.7.6.5
>
> Signed-off-by: Anisa Su
> Signed-off-by: Jonathan Cameron
Reviewed-by: Fan Ni
Only a minor comment inline ...
> ---
The new cgs_set_guest_policy() function is provided to receive the guest
policy flags, SNP ID block and SNP ID authentication from guest
configuration such as an IGVM file and apply it to the platform prior to
launching the guest.
The policy is used to populate values for the existing 'policy',
'i
On 7/3/25 04:20, Peter Maydell wrote:
On Wed, 2 Jul 2025 at 13:38, Richard Henderson
wrote:
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-sme.h| 20 ++
target/arm/tcg/sme_helper.c| 116 +
target/arm/tcg/translate-sme.c | 35 ++
++--
rust/hw/timer/hpet/src/device.rs | 14 +++
rust/qemu-api/meson.build| 1 +
rust/qemu-api/src/memory.rs | 86 +++-
5 files changed, 93 insertions(+), 27 deletions(-)
---
base-commit: c77283dd5d79149f4e7e9edd00f65416c648ee59
change-id: 20250703-rust
We have the ability to make memory accesses use a typesafe access width
type in Rust, which the C API currently lacks as it does not use a
newtype wrapper for specifying the amount of bytes a memory access has;
it uses a plain 32-bit integer value instead.
Replace use of u32 size arguments with a
On Thu, 3 Jul 2025 14:35:32 +0200
Eric Auger wrote:
> Set up the IO registers used to communicate between QEMU
> and ACPI.
>
> Signed-off-by: Eric Auger
Reviewed-by: Jonathan Cameron
On 7/3/25 1:55 PM, Vladimir Sementsov-Ogievskiy wrote:
Theoretically tap_read_packet() may return size less than
s->host_vnet_hdr_len, and next, we'll work with negative size
(in case of !s->using_vnet_hdr). Let's avoid it.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
net/tap.c | 5 +
The IGVM library allows Independent Guest Virtual Machine files to be
parsed and processed. IGVM files are used to configure guest memory
layout, initial processor state and other configuration pertaining to
secure virtual machines.
This adds the --enable-igvm configure option, enabled by default,
Hi Shameer,
On 7/3/25 10:46 AM, Shameer Kolothum wrote:
> Commit d6afe18b7242 ("hw/arm/virt-acpi-build: Fix ACPI IORT and MADT tables
> when its=off") moved ITS group node generation under the its=on condition.
> However, it still creates rc_its_idmaps unconditionally, which results in
> duplicate
Here is v9 of the set of patches to add support for IGVM files to QEMU. This is
based on commit c77283dd5d79149f4e7e9edd00f65416c648ee59 of qemu.
Once again, this is mostly a rebase of the previous patch series. However,
thanks to those reviewers who have provided feedback on v8 which has now been
In preparation for supporting the processing of IGVM files to configure
guests, this adds a set of functions to ConfidentialGuestSupport
allowing configuration of secure virtual machines that can be
implemented for each supported isolation platform type such as Intel TDX
or AMD SEV-SNP. These funct
On Thu, 3 Jul 2025 14:35:35 +0200
Eric Auger wrote:
> The disassembled DSDT table is given below
I'd suggest maybe a spot of cropping to bring this down to a reasonable length.
See inline.
Otherwise LGTM
Reviewed-by: Jonathan Cameron
>
> * Original Table Header:
> * Signature
On 7/3/25 03:45, Peter Maydell wrote:
On Wed, 2 Jul 2025 at 13:34, Richard Henderson
wrote:
Signed-off-by: Richard Henderson
+/* Similar for 2-way dot product */
+#define DO_DOT(NAME, TYPED, TYPEN, TYPEM) \
+void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, uint32_t desc) \
+{
IGVM files can contain an initial VMSA that should be applied to each
vcpu as part of the initial guest state. The sev_features flags are
provided as part of the VMSA structure. However, KVM only allows
sev_features to be set during initialization and not as the guest is
being prepared for launch.
On Thu, 19 Jun 2025 at 00:06, Jackson Donaldson wrote:
>
> This commit adds AES to max78000_soc
>
> Signed-off-by: Jackson Donaldson
> ---
> hw/arm/max78000_soc.c | 12 +---
> include/hw/arm/max78000_soc.h | 2 ++
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --gi
On Thu, 19 Jun 2025 at 00:06, Jackson Donaldson wrote:
>
> This commit implements AES for the MAX78000
>
> Signed-off-by: Jackson Donaldson
> ---
> +static uint64_t max78000_aes_read(void *opaque, hwaddr addr,
> +unsigned int size)
> +{
> +Max78000AesState
On 7/3/25 4:46 AM, Shameer Kolothum wrote:
Commit d6afe18b7242 ("hw/arm/virt-acpi-build: Fix ACPI IORT and MADT tables
when its=off") moved ITS group node generation under the its=on condition.
However, it still creates rc_its_idmaps unconditionally, which results in
duplicate ID mappings in t
On Thu, 19 Jun 2025 at 03:50, wrote:
>
> v2 changes: Addresses comments by Peter.
Thanks for sending out a v2, and sorry it's taken me a
couple of weeks to get to it for review. I've left comments
on the various patches, but this is looking pretty good.
I should mention that QEMU's softfreeze fo
Philippe Mathieu-Daudé writes:
> vCPUs are not really usable until fully realized. Do not attempt
> to commit memory changes in the middle of vCPU realization. Defer
> until realization is completed and vCPU fully operational.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Richard Hend
Hi Markus,
On 3/7/25 12:54, Philippe Mathieu-Daudé wrote:
Extract TCG and KVM definitions from machine.json to accelerator.json.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Zhao Liu
---
MAINTAINERS| 1 +
qapi/accelerator.json | 57
On Wed, 2 Jul 2025 at 13:22, Richard Henderson
wrote:
>
> Implement FPProcessNaNs4 within f16_dotadd, rather than
> simply letting NaNs propagate through the function.
>
> Cc: qemu-sta...@nongnu.org
> Fixes: 3916841ac75 ("target/arm: Implement FMOPA, FMOPS (widening)")
> Signed-off-by: Richard Hen
From: Davidlohr Bueso
This adds initial support for the Maintenance command, specifically
the soft and hard PPR operations on a dpa. The implementation allows
to be executed at runtime, therefore semantically, data is retained
and CXL.mem requests are correctly processed.
Keep track of the reque
From: Shiju Jose
CXL spec 3.2 section 8.2.9.2.1 Table 8-55, Common Event Record
format has updated with optional Maintenance Operation Subclass,
LD ID and ID of the device head information.
Add updates for the above optional parameters in the related
CXL events reporting and in the QMP commands
From: Shiju Jose
Memory sparing is defined as a repair function that replaces a portion of
memory with a portion of functional memory at that same DPA. The
subclasses for this operation vary in terms of the scope of the sparing
being performed. The Cacheline sparing subclass refers to a sparing
a
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.1 Table 8-57, general media event
table has updated with following new fields.
1. Advanced Programmable Corrected Memory Error Threshold Event Flags
2. Corrected Memory Error Count at Event
3. Memory Event Sub-Type
4. Support for component ID in
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.3 Table 8-50, memory module
event record has updated with following new fields.
1. Validity Flags
2. Component Identifier
3. Device Event Sub-Type
Add updates for the above spec changes in the CXL memory module
event reporting and QMP command t
From: Shiju Jose
Add updates for the CXL spec rev3.2 changes, in the CXL events reporting
and QMP command to inject CXL events.
Add maintenance support and emulation support for memory Post Package
Repair(PPR) and memory sparing control features.
Add support for reporting the memory sparing eve
On Wed, 2 Jul 2025 at 13:22, Richard Henderson
wrote:
>
> Gvec only operates on size 8 and multiples of 16.
> Predicates may be any multiple of 2.
> Round up the size using the appropriate function.
>
> Cc: qemu-sta...@nongnu.org
> Fixes: 598ab0b24c0 ("target/arm: Implement PSEL")
> Signed-off-by:
On Wed, 2 Jul 2025 at 13:22, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/translate-sve.c | 23 ---
> 1 file changed, 16 insertions(+), 7 deletions(-)
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 2 Jul 2025 at 13:22, Richard Henderson
wrote:
>
> Implement FPProcessNaNs4 within f16_dotadd, rather than
should be "bfdotadd_ebf" ?
> simply letting NaNs propagate through the function.
>
> Cc: qemu-sta...@nongnu.org
> Fixes: 0e1850182a1 ("target/arm: Implement FPCR.EBF=1 semantics for
On Wed, 2 Jul 2025 at 13:22, Richard Henderson
wrote:
>
> Replace @rda_rn_rm_e0 with @rda_rn_rm_ex, and require
> users to supply an explicit esz.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/sve.decode | 48 +++
> 1 file changed, 24 insertions(
From: Shiju Jose
CXL spec rev3.2 section 8.2.10.2.1.2 Table 8-58, DRAM event record
has updated with following new fields.
1. Component Identifier
2. Sub-channel of the memory event location
3. Advanced Programmable Corrected Memory Error Threshold Event Flags
4. Corrected Volatile Memory Error C
From: Shiju Jose
Move the declaration of scrub and ECS feature attributes in
cmd_features_set_feature() to the local scope where they are used.
Signed-off-by: Shiju Jose
---
hw/cxl/cxl-mailbox-utils.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/hw/cxl
On Thu, 3 Jul 2025 09:46:32 +0100
Shameer Kolothum wrote:
> Commit d6afe18b7242 ("hw/arm/virt-acpi-build: Fix ACPI IORT and MADT tables
> when its=off") moved ITS group node generation under the its=on condition.
> However, it still creates rc_its_idmaps unconditionally, which results in
> duplic
Hi, Xiaoyao!
Hi, Zhao!
Thank you for your feedback.
You wrote:
> QEMU allocates separate KVM address space for SMM in
> register_smram_listener(). But the address space doesn't associated with
> cpu's address space.
The address space allocated in register_sm_ram_listener() is stored in
KVMSta
> Nice clean-up patch series. Thanks.
>
> Reviewed-by: Dapeng Mi
>
Thanks for your review and effort!
Regards,
Zhao
On Wed, 2 Jul 2025 at 13:34, Richard Henderson
wrote:
>
> Pipe the value through from SMCR_ELx through hflags and into
> the disassembly context. Enable EZT0 in smcr_write.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, Jul 02, 2025 at 01:08:41PM -0700, Pierrick Bouvier wrote:
> On 7/2/25 6:09 AM, Daniel P. Berrangé wrote:
> > On Fri, Jun 27, 2025 at 01:02:22PM -0700, Pierrick Bouvier wrote:
> > > This test allows to document and exercise device passthrough, using a
> > > nested virtual machine setup. Two
Remove vhost-user specific hack from generic code.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
hw/virtio/vhost-user.c| 8
hw/virtio/vhost.c | 15 ++-
include/hw/virtio/vhost-backend.h | 2 ++
3 files changed, 16 insertions(+), 9 deletions(-)
We are going to drop backend_features variable as an extra one.
Call to qemu_has_vnet_hdr() is cheap.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
hw/net/vhost_net.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c
inde
On 7/3/25 7:49 AM, Djordje Todorovic wrote:
Add RISC-V implementations of the Coherent Manager Global Control
Register (CMGCR) and Cluster Power Controller (CPC) devices. These
are based on the existing MIPS CMGCR and CPC implementations but
adapted for RISC-V systems.
The CMGCR device provid
Simply use features instead, we have same flag here.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
hw/virtio/vhost-user.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index 1b2879a90cc..cf6f53801db 1006
No need to export aml_pci_device_dsm() as it is only used
in hw/i386/acpi-build.c.
Signed-off-by: Eric Auger
Reviewed-by: Gustavo Romero
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
include/hw/acpi/pci.h | 1 -
hw/i386/acpi-build.c | 2 +-
Let pass the root bus to ich9 and piix4 through a property link
instead of through an argument passed to acpi_pcihp_init().
Also make sure the root bus is set at the entry of acpi_pcihp_init().
The rationale of that change is to be consistent with the forecoming ARM
implementation where the machi
Some sysbus devices have conditional mmio regions. This
happens for instance with the hw/acpi/ged device. In that case
it becomes difficult to predict which index a specific MMIO
region corresponds to when one needs to mmio map the region.
Introduce a new helper that takes the name of the region in
Add a subsection to migrate the AcpiPciHpState state.
Signed-off-by: Eric Auger
Reviewed-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
hw/acpi/generic_event_device.c | 20
1 file changed, 20 insertions(+)
diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic
This series enables ACPI PCI hotplug/hotunplug on ARM.
It is not enabled by default and ACPI PCI hotplug can
be selected by setting:
-global acpi-ged.acpi-pci-hotplug-with-bridge-support=on
Expected benefits should be similar to those listed in [1],
ie. removal of some racy behaviors, improved la
The MonitorDef API is related to two HMP monitor commands: 'p' and 'x':
(qemu) help p
print|p /fmt expr -- print expression value (use $reg for CPU register access)
(qemu) help x
x /fmt addr -- virtual memory dump starting at 'addr'
For x86, one of the few targets that implements it, it is possib
GB200nvl72 is a system for for accelerated compute. This is a model for
the BMC target within the system.
This is based on the device tree aspeed-bmc-nvidia-gb200nvl-bmc.dts
from:
[1]
https://github.com/openbmc/linux/blob/dev-6.6/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200nvl-bmc.dts
Sign
To support the newly added gb200 machine, add appropriate tests.
Signed-off-by: Ed Tanous
---
tests/functional/aspeed.py| 9 +--
tests/functional/meson.build | 2 ++
.../test_arm_aspeed_gb200nvl_bmc.py | 26 +++
3 files changed
This patch series adds support for gb200-bmc, a baseboard management controller
module based on an Aspeed 2600 SOC.
v2:
- Rebase on master
- Drop duplicated patch for enabling PCA954X
- Updated commit message with source information
- Added functional tests and example openbmc image
Ed Tanous (4)
Aspeed2600 has two spi lanes; Add a new struct that can mount the
second SPI.
Signed-off-by: Ed Tanous
---
hw/arm/aspeed.c | 2 ++
include/hw/arm/aspeed.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index d0b333646e..3ef7f6c5b2 100644
--- a/h
This patch updates the docs for support of gb200-bmc.
Signed-off-by: Ed Tanous
---
docs/system/arm/aspeed.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 43d27d83cb..bec0a1dfa8 100644
--- a/docs/system/arm/
When an SEV guest is started, the reset vector and state are
extracted from metadata that is contained in the firmware volume.
In preparation for using IGVM to setup the initial CPU state,
the code has been refactored to populate vmcb_save_area for each
CPU which is then applied during guest start
The x86 segment registers are identified by the X86Seg enumeration which
includes LDTR and TR as well as the normal segment registers. The
function 'cpu_x86_load_seg_cache()' uses the enum to determine which
segment to set. However, specifying R_LDTR or R_TR results in an
out-of-bounds access of th
On 7/3/25 04:54, Philippe Mathieu-Daudé wrote:
Since commit 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER",
released with QEMU v8.1.0) we get pointless output:
(qemu) info opcount
[TCG profiler not compiled]
Remove that unstable and unuseful command.
Signed-off-by: Philippe Mathieu-Dau
On 7/3/25 04:54, Philippe Mathieu-Daudé wrote:
TCG profiler was removed in commit 1b65b4f54c7.
Fixes: 1b65b4f54c7 ("accel/tcg: remove CONFIG_PROFILER")
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/monitor.c | 6 --
1 file changed, 6 deletions(-)
Reviewed-by: Richard Henderson
r
Richard Henderson writes:
> From: Peter Maydell
>
> Signed-off-by: Peter Maydell
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Richard Henderson writes:
> From: Peter Maydell
>
> Signed-off-by: Peter Maydell
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Richard Henderson writes:
> Signed-off-by: Richard Henderson
> ---
> target/arm/tcg/cpu64.c| 10 --
> docs/system/arm/emulation.rst | 6 ++
> 2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> index 5d8ed2794
On 7/3/25 04:55, Philippe Mathieu-Daudé wrote:
+void dummy_thread_precreate(CPUState *cpu)
+{
+#ifdef _WIN32
+qemu_sem_init(&cpu->sem, 0);
+#endif
+}
Incidentally, why is this not in cpu_common_initfn, the instance_init for CPUState? Given
the placement of CPUState.sem, that would seem to
On 7/3/25 04:55, Philippe Mathieu-Daudé wrote:
In order to dispatch overAccelOpsClass::handle_interrupt(),
we need it always defined, not calling a hidden handler under
the hood. MakeAccelOpsClass::handle_interrupt() mandatory.
Expose generic_handle_interrupt() prototype and register it
for each
On Tue, Jul 01, 2025 at 08:12:27AM +0200, Markus Armbruster wrote:
> Fabiano Rosas writes:
>
> > Caught by inspection, but ASAN also reports:
> >
> > Direct leak of 16 byte(s) in 1 object(s) allocated from:
> > #0 in malloc
> > #1 in g_malloc
> > #2 in g_memdup
> > #3 in qapi_clone_start_stru
On Thu, Jul 03, 2025 at 11:21:38PM +0200, Cédric Le Goater wrote:
> On 7/3/25 21:45, Peter Xu wrote:
> > On Wed, Jul 02, 2025 at 03:41:08PM -0400, Steven Sistare wrote:
> > > The irq producer is not closed, but it is detached from the kvm consumer.
> > > It's eventfd is preserved in new QEMU, and i
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