On Thu, 19 Jun 2025 at 00:06, Jackson Donaldson <jackson88...@gmail.com> wrote:
>
> This commit implements AES for the MAX78000
>
> Signed-off-by: Jackson Donaldson
> ---
> +static uint64_t max78000_aes_read(void *opaque, hwaddr addr,
> + unsigned int size)
> +{
> + Max78000AesState *s = opaque;
> + switch (addr) {
> + case CTRL:
> + return s->ctrl;
> +
> + case STATUS:
> + return s->status;
> +
> + case INTFL:
> + return s->intfl;
> +
> + case INTEN:
> + return s->inten;
> +
> + case FIFO:
> + if (s->result_index >= 4) {
> + s->intfl &= ~DONE;
> + s->result_index -= 4;
> + max78000_aes_set_status(s);
> + return (s->result[s->result_index] << 24) +
> + (s->result[s->result_index + 1] << 16) +
> + (s->result[s->result_index + 2] << 8) +
> + s->result[s->result_index + 3];
You can write this more simply as
return ldl_be_p(&s->result[s->result_index]);
(that's a function which loads a big-endian 32-bit value from
the given possibly-unaligned host address).
> + } else{
> + return 0;
> + }
> +
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"
> + HWADDR_PRIx "\n", __func__, addr);
> + break;
> +
> + }
> + return 0;
> +}
> +static void max78000_aes_write(void *opaque, hwaddr addr,
> + uint64_t val64, unsigned int size)
> +{
> + Max78000AesState *s = opaque;
> + uint32_t val = val64;
> + int i;
> + switch (addr) {
> + case CTRL:
> + if (val & OUTPUT_FLUSH) {
> + s->result_index = 0;
> + val &= ~OUTPUT_FLUSH;
> + }
> + if (val & INPUT_FLUSH) {
> + s->data_index = 0;
> + val &= ~INPUT_FLUSH;
> + }
> + if (val & START) {
> + max78000_aes_do_crypto(s);
> + }
> +
> + /* Hardware appears to stay enabled even if 0 written */
> + s->ctrl = val | (s->ctrl & AES_EN);
> + break;
> +
> + case FIFO:
> + for (i = 0; i < 4; i++) {
> + s->data[(12 - s->data_index) + i] =
> + (val >> ((3 - i) * 8)) & 0xff;
> + }
Similarly here this is
stl_be_p(&s->data[12 - s->data_index], val);
There should be some kind of check here that s->data_index is
in range here before we write to s->data[] (either an assert,
if the device code is supposed to maintain data_index in range
at all times, or else some kind of error handling path if
guest software can do funny things to put it out of range).
> + s->data_index += 4;
> + if (s->data_index >= 16) {
> + s->data_index = 0;
> + max78000_aes_do_crypto(s);
> + }
> + break;
> +
> + case KEY_BASE ... KEY_END - 4:
> + for (i = 0; i < 4; i++) {
> + s->key[(KEY_END - KEY_BASE - 4) - (addr - KEY_BASE) + i] =
> + (val >> ((3 - i) * 8)) & 0xff;
stl_be_p(&s->key[...something...], val);
> + }
> + break;
> +
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"
> + HWADDR_PRIx "\n", __func__, addr);
> + break;
> +
> + }
> + max78000_aes_set_status(s);
> +}
thanks
-- PMM
