From: Thomas Huth
These tests currently fail if VNC support has not been compiled into
the QEMU binary. Let's add some checks to skip the tests in that
case instead.
Signed-off-by: Thomas Huth
---
tests/functional/test_vnc.py | 26 ++
1 file changed, 22 insertions(+), 4
Hello,
I am attempting to simulate a system with multiple CPU
architectures. To do this I am starting a unique QEMU process for each
CPU architecture that is needed. I'm also developing some QEMU code
that aids in transporting MMIO transactions across the process
boundaries using sockets.
The de
If the dont-log flag is set in the 'timer use' field for the
'set watchdog' command, a watchdog timeout will not get logged as
a timer use expiration.
Signed-off-by: Nicholas Piggin
---
hw/ipmi/ipmi_bmc_sim.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-
Hello Jamin,
On 3/21/25 10:25, Jamin Lin wrote:
v1:
1. Added support for 64-bit DMA in the HACE model
2. Refactored the do_hash operation in the HACE model
3. Fixed a crash caused by out-of-bound memory access in HACE
4. Added more trace events and implemented dumping of source hash data
A qemu_log_mask!() macro is provided which expects similar arguments as the C
version. However, the formatting works as one would expect from Rust.
To maximize code reuse the macro is just a thin wrapper around qemu_log().
Also, just the bare minimum of logging masks is provided which should suffi
On Thu, Apr 03, 2025 at 01:16:33AM -0700, Pinku Deb Nath wrote:
> The testing with "-t writeback" works for turning on enable_write_cache.
> I renamed the function to qemu_pwritev_fua() and fixed any typos.
>
> I moved the handle_aiocb_flush() into the qemu_pwritev_fua() and
> removed from the pre
We only use qemu_get_betls() and qemu_put_betls() once in
the whole code base. Inline them (checking TARGET_MIPS64
instead of TARGET_LONG_BITS == 64) so we can remove them
later as unused.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/system/machine.c | 12 ++--
1 file changed, 1
On 3/24/25 10:39, Richard Henderson wrote:
On 3/24/25 03:21, Alex Bennée wrote:
+#ifdef TARGET_BIG_ENDIAN
+MemOp end = MO_BE;
+#else
+MemOp end = MO_LE;
+#endif
+#endif
That's what MO_TE is for.
+/*
+ * Helpers copied from helpers.h just for handling target_ulong values
+
On 25/03/25 20:08, Cédric Le Goater wrote:
On 3/25/25 12:23, Aditya Gupta wrote:
Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
From: YannickV
The CX7200 has one Gigabit Ethernet MAC connected to address
0xE000C000. The one connected to address 0xE000B000 can be
removed.
Signed-off-by: Yannick Voßen
---
hw/arm/beckhoff_CX7200.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/arm/beckhoff_CX7200.c b/hw/arm/beckhof
On 3/18/25 15:45, Richard Henderson wrote:
On 3/17/25 21:51, Pierrick Bouvier wrote:
To eliminate TARGET_AARCH64, we need to make various definitions common
between 32 and 64 bit Arm targets.
Added registers are used only by aarch64 code, and the only impact is on
the size of CPUARMState, and ad
On 3/27/2025 8:27 PM, Steven Sistare wrote:
On 3/26/2025 5:34 PM, Michael Roth wrote:
On Wed, Mar 26, 2025 at 05:13:50PM -0300, Fabiano Rosas wrote:
Michael Roth writes:
Quoting Tom Lendacky (2025-03-26 14:21:31)
On 3/26/25 13:46, Tom Lendacky wrote:
On 3/7/25 12:15, Fabiano Rosas wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 16acc4ecb92..833a93d37af 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -176,6 +176,7 @@ static con
On 3/20/25 15:29, Pierrick Bouvier wrote:
Now we made sure important defines are included using their direct
path, we can remove cpu.h from cpu-all.h.
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 2 --
accel/tcg/cpu-exec.c | 1 +
2 files changed, 1 insertion(+), 2 deletions
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 4
cpu-target.c | 4
2 files changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
r~
Increase TARGET_PHYS_ADDR_SPACE_BITS to allow flexibility in the page
size without triggering an assert. Select the page size based on the
size of sram. This leaves sram on exactly one page and minimizes the
number of pages required to span the flash.
Signed-off-by: Richard Henderson
---
targe
From: Zhu Yangyang
Calling qmp_block_set_io_throttle() will be blocked for a long time
when a network disk is configured and the network failure is just about
to occur.
Therefore, we add a timeout parameter for qmp_block_set_io_throttle to control
its execution duration.
The default value of ti
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
accel/tcg/tb-internal.h | 1 -
include/exec/cpu-all.h | 22 --
include/hw/core/cpu.h | 2 +-
include/qemu/bswap.h| 2 +-
target/alpha/cpu.h | 2 --
target/arm/cpu.h| 2
Citing Gustavo [*]:
Gating IORT table generation entirely based on the presence
of ITS looks wrong because IORT table has data beyond GIC ITS,
like for SMMUv3 etc..
[*]
https://lore.kernel.org/qemu-devel/bae6e29a-7290-47d2-8caf-14702ee09...@linaro.org/
Reported-by: Gustavo Romero
Signed-
On Thu, Mar 20, 2025 at 1:59 AM Jason Wang wrote:
>
> Adding Cindy and Eugenio
>
> On Thu, Mar 20, 2025 at 12:34 AM Konstantin Shkolnyy
> wrote:
> >
> > I’m observing a problem while testing VDPA with Nvidia ConnectX-6 (mlx5)
> > on s390.
> >
> > Upon start, virtio_net_device_realize() tries to
On 3/28/25 13:04, Richard Henderson wrote:
The CPU_TLB_DYN_{MIN,MAX}_BITS definitions are not required
outside of cputlb.c and translate-all.c.
Signed-off-by: Richard Henderson
---
accel/tcg/tb-internal.h | 27 ---
accel/tcg/tlb-bounds.h| 32
On 3/23/25 10:37, Richard Henderson wrote:
Integrate the i/o 0x00-0x1f and 0x38-0x3f loopbacks into
the cpu registers with normal address space accesses.
We no longer need to trap accesses to the first page within
avr_cpu_tlb_fill but can wait until a write occurs.
Signed-off-by: Richard Henders
On Thu, Mar 20, 2025 at 09:34:26AM +0100, Jörg Rödel wrote:
> On Tue, Mar 18, 2025 at 12:11:02PM +0100, Gerd Hoffman wrote:
> > Open questions:
> >
> > - Does the idea to use igvm parameters for the kernel hashes makes
> >sense? Are parameters part of the launch measurement?
>
> Parameters
Dear Alex Bennée,
Thank you for your response and for the provided documentation link.
To clarify, when we refer to energy consumption, we are specifically looking at
CPU core utilization. Our goal is to ensure that when we turn off CPU cores on
the emulated Raspberry Pi 3B, the host machine do
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 2 --
include/exec/cpu_ldst.h | 1 +
target/alpha/cpu.h | 1 +
target/arm/cpu.h| 1 +
target/avr/cpu.h| 1 +
target/hexagon/cpu.h| 1 +
target/hppa/cpu.h | 1 +
target/i386/cpu.h | 1 +
target/loong
On Tue, Mar 18, 2025 at 10:54:12AM +0100, Cédric Le Goater wrote:
> Rename these routines :
>
> vfio_put_group -> vfio_group_put
> vfio_get_group -> vfio_group_get
> vfio_kvm_device_del_group -> vfio_group_del_kvm_device
> vfio_kvm_device_add_group -> vfio_group_add_kvm_device
> vfio_ge
On 2025-04-02 07:48, Thomas Huth wrote:
On 31/03/2025 16.00, Shalini Chellathurai Saroja wrote:
Implement the Service-Call Logical Processor (SCLP) event
type Control-Program Identification (CPI) in QEMU. This
event is used to send CPI identifiers from the guest to the
host. The CPI identifiers
Trivial fix for issue #2861.
Philippe Mathieu-Daudé (2):
hw/pci-host/designware: Fix access to ATU_UPPER_TARGET register
hw/pci-host/designware: Use deposit/extract API
hw/pci-host/designware.c | 47 ++--
1 file changed, 16 insertions(+), 31 deletions(-)
On 3/31/25 14:49, Joao Martins wrote:
On 21/03/2025 11:22, Cédric Le Goater wrote:
On 3/19/25 13:21, Joao Martins wrote:
On 18/03/2025 09:54, Cédric Le Goater wrote:
Rename these routines :
vfio_devices_all_device_dirty_tracking_started ->
vfio_dirty_tracking_devices_is_started_all
vf
On 18/03/2025 09:53, Cédric Le Goater wrote:
> This routine is only used in file "migration.c". Move it there.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joao Martins
> ---
> include/hw/vfio/vfio-common.h | 1 -
> hw/vfio/common.c | 6 --
> hw/vfio/migration.c
Power8E and Power8NVL variants are not of much use in QEMU now, and not
being maintained either.
Newer skiboot might not be able to boot Power8NVL since skiboot v7.0
Deprecate the 8E and 8NVL variants.
After deprecation, QEMU will print a warning like below when the
CPU/Chips are used:
$ ./
On Thu, 20 Mar 2025 at 19:30, wrote:
> To clarify, when we refer to energy consumption, we are specifically looking
> at CPU core utilization. Our goal is to ensure that when we turn off CPU
> cores on the emulated Raspberry Pi 3B, the host machine does not keep its
> corresponding cores runnin
On Tue, Apr 01, 2025 at 09:42:01AM +1000, Nicholas Piggin wrote:
> On Mon Mar 31, 2025 at 11:25 PM AEST, Corey Minyard wrote:
> > On Mon, Mar 31, 2025 at 10:57:24PM +1000, Nicholas Piggin wrote:
> >> +static void get_channel_info(IPMIBmcSim *ibs,
> >> + uint8_t *cmd, uns
pci_host_data_be_ops became unused after endianness fixes
Suggested-by: Paolo Bonzini
Signed-off-by: Rakesh Jeyasingh
Reviewed-by: Philippe Mathieu-Daudé
---
hw/pci/pci_host.c | 6 --
include/hw/pci-host/dino.h | 4
include/hw/pci/pci_host.h | 1 -
3 files changed, 11 delet
On Tue, Mar 18, 2025 at 10:53:56AM +0100, Cédric Le Goater wrote:
> VFIOAddressSpace is a common object used by VFIOContainerBase which is
> declared in "hw/vfio/vfio-container-base.h". Move the VFIOAddressSpace
> related services into "container-base.c".
>
> While at it, rename :
>
> vfio_get
On Tue, Mar 18, 2025 at 10:54:13AM +0100, Cédric Le Goater wrote:
> Rename these routines :
>
> vfio_devices_all_device_dirty_tracking_started ->
> vfio_dirty_tracking_devices_is_started_all
> vfio_devices_all_dirty_tracking_started->
> vfio_dirty_tracking_devices_is_started
> vfi
On 4/5/25 07:25, Philippe Mathieu-Daudé wrote:
Hi Guenter,
On 5/4/25 16:00, Guenter Roeck wrote:
This series is needed to support the USB interface on imx8mp-evk when
booting the Linux kernel.
According to the XHCI specification, ERSTBA should be written in Low-High
order. The Linux kernel wri
The following changes since commit 1dae461a913f9da88df05de6e2020d3134356f2e:
Update version for v10.0.0-rc0 release (2025-03-18 10:18:14 -0400)
are available in the Git repository at:
https://gitlab.com/mjt0k/qemu.git tags/pull-trivial-patches
for you to fetch changes up to a028e04c89ea782f
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.c | 2 ++
target/arm/cpu64.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 377791c84dd..b1aa482c726 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -50,6 +50,7 @@
#include "disas
On 18/03/2025 11:53, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
Gather all VFIO migration related declarations into "migration.h" to
reduce exposure of VFIO internals in "hw/vfio/vfio-common.h".
Reviewed-by: Avihai Horon
Two nits below.
Signed-off-
Hi, Richard,
On Tue, Apr 1, 2025 at 9:39 PM Richard Henderson
wrote:
>
> On 3/31/25 20:15, Huacai Chen wrote:
> >> # define TARGET_VIRT_ADDR_SPACE_BITS 32
> >> #endif
> >> #endif
> >> -#ifdef CONFIG_USER_ONLY
> >> #define TARGET_PAGE_BITS 12
> >> -#else
> >> -#define TARGET_PAGE_BITS_VAR
On 3/19/2025 19:58, Jason Wang wrote:
Adding Cindy and Eugenio
On Thu, Mar 20, 2025 at 12:34 AM Konstantin Shkolnyy wrote:
I’m observing a problem while testing VDPA with Nvidia ConnectX-6 (mlx5)
on s390.
Upon start, virtio_net_device_realize() tries to set a new MAC address
by VHOST_VDPA_SE
On 4/2/25 14:23, Philippe Mathieu-Daudé wrote:
Since commit f9ba56a03c2 ("user: Introduce 'user/guest-host.h' header")
cpu_untagged_addr() is only needed in "user/guest-host.h".
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index e5d852fbe2c..db44c0d3016 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -23,7 +23,6 @@
#include "hw/core/cpu.h"
Hi,
If ieee754 equals EMULATED, then the variables mips_use_nan_2008 and
mips_use_nan_legacy are set to true
(
https://elixir.bootlin.com/linux/v6.13.6/source/arch/mips/kernel/fpu-probe.c#L208
)
and any binaries are accepted regardless of whether supported by the FPU
( https://elixir.bootlin.com
On Sat, Mar 29, 2025 at 1:43 PM David Woodhouse wrote:
>
> On Fri, 2025-02-07 at 14:34 +, David Woodhouse wrote:
> > From: David Woodhouse
> >
> > The vmclock device only has a reset method in order to plug its memory
> > region into the system memory. It was originally done this way in order
> -Original Message-
> From: Sid Manning
> Sent: Tuesday, March 18, 2025 1:34 PM
> To: ltaylorsimp...@gmail.com; 'Brian Cain'
> ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; phi...@linaro.org; Matheus Bernardino
> (QUIC) ; a...@rev.ng; a...@rev.ng; Marco
> Liebel (QUIC) ;
On 4/3/25 08:18, Philippe Mathieu-Daudé wrote:
GIC ITS is checked for the MADT and IORT tables.
Factor the checks out to the its_enabled() helper.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Gustavo Romero
---
hw/arm/virt-acpi-build.c | 12 +---
1 file changed, 9 insertions(+),
Mask out unsupported bits and return failure if attempting to set
any. This is not required by the IPMI spec, but it does require that
system software not change bits it isn't aware of.
Signed-off-by: Nicholas Piggin
---
hw/ipmi/ipmi_bmc_sim.c | 10 +-
1 file changed, 9 insertions(+), 1
Hi Shaoqin,
Thank you very much for testing!
> I tried your series on ARM64, but it reports error at compile time, here is
> the error output:
>
> qapi/kvm.json:59:Unexpected indentation.
I guess this is caused by my invalid format and sphinx complains that,
as Markus figured out :-(
What abou
"Marco Cavenati" writes:
> Hello Fabiano,
>
> First of all thanks a lot for the quick follow up to my issue!
>
> I just want to point out that with only mapped-ram enabled (without
> multifd) savevm/loadvm do not lead to a crash but just to an error
> according to my (few) experiments (on upstrea
Citing Gustavo [*]:
Gating IORT table generation entirely based on the presence
of ITS looks wrong because IORT table has data beyond GIC ITS,
like for SMMUv3 etc..
[*]
https://lore.kernel.org/qemu-devel/bae6e29a-7290-47d2-8caf-14702ee09...@linaro.org/
Reported-by: Gustavo Romero
Signed-
On 3/19/25 12:54, Avihai Horon wrote:
On 18/03/2025 11:53, Cédric Le Goater wrote:
External email: Use caution opening links or attachments
vfio_mig_active() is part of the VFIO migration API. Move the
definitions where VFIO migration is implemented.
Signed-off-by: Cédric Le Goater
Review
On 4/2/25 20:05, Huacai Chen wrote:
On Thu, Apr 3, 2025 at 2:11 AM Richard Henderson
wrote:
On 4/1/25 20:04, Huacai Chen wrote:
Hi, Richard,
On Tue, Apr 1, 2025 at 9:39 PM Richard Henderson
wrote:
On 3/31/25 20:15, Huacai Chen wrote:
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endi
Pierrick Bouvier writes:
> We first fix the issue reported in [1].
> We then add a test plugin making sure we don't regress in the future.
>
> [1] https://gitlab.com/qemu-project/qemu/-/issues/2901
Queued to plugins/next, thanks.
>
> Pierrick Bouvier (2):
> plugins/loader: fix deadlock when r
Hi Jiaxun,
On 21/1/25 13:16, Thomas Huth wrote:
On 21/01/2025 13.07, Jiaxun Yang wrote:
在2025年1月21日一月 上午10:36，Thomas Huth写道：
We are not aware of anybody still using this machine, support for it
has been withdrawn from the Linux kernel (i.e. there also won't be
any future development anymore)
On 3/24/25 11:46, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (7):
cpus: IntroduceCPUClass::list_cpus() callback
target/i386: RegisterCPUClass:list_cpus
target/ppc: RegisterCPUClass:list_cpus
target/sparc: RegisterCPUClass:list_cpus
target/s390x: Declare s390_set_qemu_cpu_
From: Nikita Shubin
Add GPIO device front end with helper functions to provide information
about GPIO Port to Backends and to allow Frontend to set data.
To use it GPIO device should register with qemu_gpio_fe_init()
and provide handlers with qemu_gpio_fe_set_handlers().
Notifications about con
On Thu, Apr 3, 2025 at 12:35 AM Michael S. Tsirkin wrote:
>
> On Wed, Mar 26, 2025 at 09:19:32PM +0800, Cindy Lu wrote:
> > For VDPA devices, Allow configurations where the hardware MAC address
> > is non-zero while the MAC address in the QEMU command line is zero.
> >
> > Signed-off-by: Cindy Lu
On 2025-04-02 08:05, Thomas Huth wrote:
On 31/03/2025 16.00, Shalini Chellathurai Saroja wrote:
Register Control-Program Identification data with the live
migration infrastructure.
Signed-off-by: Shalini Chellathurai Saroja
Reviewed-by: Nina Schoetterl-Glausch
---
hw/s390x/sclpcpi.c | 27 ++
On 3/21/25 05:57, Philippe Mathieu-Daudé wrote:
Add theTCGCPUOps::guest_default_memory_order field and have
each target initialize it.
Use it to setTCGContext::guest_mo in tb_gen_code(), removing
the need for the TCG_GUEST_DEFAULT_MO definition.
Signed-off-by: Philippe Mathieu-Daudé
---
Revie
Now that TCG_GUEST_DEFAULT_MO is always defined,
simplify the tcg_req_mo() macro.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Reviewed-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
---
accel/tcg/internal-target.h | 9 +
accel/tcg/tcg-all.c | 3 ---
From: Wei Liu
Add myself as a reviewer.
Signed-off-by: Wei Liu
Link:
https://lore.kernel.org/r/1741377325-28175-15-git-send-email-li...@linux.microsoft.com
Signed-off-by: Paolo Bonzini
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
On 3/3/2025 6:26 AM, Philippe Mathieu-Daudé wrote:
Hi Brian and Sid,
On 1/3/25 18:20, Brian Cain wrote:
From: Sid Manning
Co-authored-by: Matheus Tavares Bernardino
Co-authored-by: Damien Hedde
Signed-off-by: Brian Cain
---
MAINTAINERS | 2 +
docs/devel/hexagon-l2
Hardware accelerators depends on the host, not the guest.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/poison.h | 4
scripts/make-config-poison.sh | 4
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/exec/poison.
Add the TCGCPUOps::guest_default_memory_order field and have
each target initialize it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
Reviewed-by: Richard Henderson
Reviewed-by: Pierrick Bouvier
---
include/accel/tcg/cpu-ops.h | 8
target/alpha/cpu.c | 2
Signed-off-by: Richard Henderson
---
target/avr/cpu-param.h | 8 +--
hw/avr/atmega.c| 54 ++
2 files changed, 35 insertions(+), 27 deletions(-)
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index 81f3f49ee1..f5248ce9e7 100644
--
Add register read operation emulation in generic read function
loongarch_pch_pic_read(), and use this function for iomem32_high region.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 27 ---
1 file changed, 8 insertions(+), 19 deletions(-)
diff --git a/hw/intc
From: Pierrick Bouvier
This test was randomly failing on our CI, and on dev machines,
especially with QEMU debug builds.
>From the information collected, it's related to an implementation choice
in edk2 QEMU virt support. The workaround is to disable KASLR, to avoid
accessing protected memory.
N
On 3/21/25 10:26, Jamin Lin wrote:
The HACE model in AST2600 and AST1030 is identical. Referencing the AST2600
test cases, new tests have been created for AST1030.
Implemented test functions for SHA-256, SHA-384, SHA-512, and MD5.
Added scatter-gather and accumulation test variants.
For AST1030,
We want to be able to do more common work on MachineClass.
Pass the class name as a string in .class_data.
Signed-off-by: Richard Henderson
---
hw/avr/arduino.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/hw/avr/arduino.c b/hw/avr/arduino.c
index 48ef478
On Fri, Mar 21, 2025 at 12:29 PM Konstantin Shkolnyy wrote:
>
> On 3/20/2025 20:22, Jason Wang wrote:
> > On Fri, Mar 21, 2025 at 12:45 AM Konstantin Shkolnyy
> > wrote:
> >>
> >> On 3/19/2025 19:58, Jason Wang wrote:
> >>> On Thu, Mar 20, 2025 at 12:34 AM Konstantin Shkolnyy
> >>> wrote:
> >>
On 23/3/25 18:37, Richard Henderson wrote:
Prepare for offset_io being non-zero when accessing from gdb.
Signed-off-by: Richard Henderson
---
target/avr/cpu.c | 30 ++
1 file changed, 30 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 3/24/25 03:21, Alex Bennée wrote:
Mainly as an aid to myself getting confused too many bswaps deep into
the code.
Reviewed-by: Pierrick Bouvier
Signed-off-by: Alex Bennée
---
target/ppc/cpu.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
Some targets define cpu_list to a method listing their
CPUs on stdout. In order to make list_cpus() generic,
introduce the CPUClass::list_cpus() callback.
When no callback is registered, list_cpus() defaults
to the cpu_list definition.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cp
On 20/3/25 07:19, Akihiko Odaki wrote:
On 2025/03/20 3:22, Alex Bennée wrote:
The current helper.h functions rely on hard coded assumptions about
target endianess to use the tswap macros. We also end up double
swapping a bunch of values if the target can run in multiple endianess
modes. Avoid th
The following macros:
- qemu_put_betl()
- qemu_get_betl()
- qemu_put_betls()
- qemu_get_betls()
- qemu_put_sbetl()
- qemu_get_sbetl()
- qemu_put_sbetls()
- qemu_get_sbetls()
are not used in the whole code base, remove them.
Signed-off-by: Philippe Mathieu-Daudé
---
include/migration/cp
On 4/2/2025 11:49 PM, Daniel P. Berrangé wrote:
On Wed, Apr 02, 2025 at 11:26:11PM +0800, Xiaoyao Li wrote:
Sorry for the late response.
KVM part of TDX attestation support is submitting again. QEMU part will
follow and we need to settle dowm this topic before QEMU patches submission.
On 10/4/
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
1 file changed, 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On Tue, Mar 18, 2025 at 01:06:17PM +, Peter Maydell wrote:
> On Tue, 18 Mar 2025 at 12:43, Daniel P. Berrangé wrote:
> >
> > On Tue, Mar 18, 2025 at 01:34:57PM +0100, Andreas Schwab wrote:
> > > On Mär 18 2025, Daniel P. Berrangé wrote:
> > >
> > > > Whereever practical, it is preferrable to c
Integrate the i/o 0x00-0x1f and 0x38-0x3f loopbacks into
the cpu registers with normal address space accesses.
We no longer need to trap accesses to the first page within
avr_cpu_tlb_fill but can wait until a write occurs.
Signed-off-by: Richard Henderson
---
target/avr/cpu.h | 7 ++
tar
With this, TARGET_PAGE_BITS_MIN no longer exists outside of
page-vary-target.c, as that's the only place that needs the
information.
Based-on: 20250318213209.2579218-1-richard.hender...@linaro.org
("[PATCH v2 00/42] accel/tcg, codebase: Build once patches")
Based-on: 20250325224403.4011975-1-richa
On 25/2/25 17:30, Gerd Hoffmann wrote:
Signed-off-by: Gerd Hoffmann
---
docs/devel/index-internals.rst | 1 +
docs/devel/uefi-vars.rst | 68 ++
Missing MAINTAINERS update:
F: docs/devel/uefi-vars.rst
hw/uefi/LIMITATIONS.md | 7
3 f
On Wed, Mar 26, 2025 at 09:19:29PM +0800, Cindy Lu wrote:
> When using a VDPA device, it is important to ensure that the MAC address
> is correctly set. In this patch series, we add a new parameter to
> enable this check.
> Only three MAC setup configurations are acceptable; any other will
> fail t
Well, there isn't much else to say. And there is a Fixes tag. I don't think
we have strict rules about commit message, but I am fine adding more
context on each commit.
Le jeu. 20 mars 2025, 12:39, Prasad Pandit a écrit :
> On Tue, 11 Mar 2025 at 21:44, wrote:
> > From: Marc-André Lureau
> >
>
Hi,
On 6/1/22 22:00, Frédéric Pétrot wrote:
This series of patches provides partial 128-bit support for the riscv
target architecture, namely RVI and RVM, with minimal csr support.
Frédéric Pétrot (18):
exec/memop: Adding signedness to quad definitions
exec/memop: Adding signed quad an
When pass a varray to vmstate_struct, the `type` parameter should be the
type of the element in the varray, for example:
vmstate_struct!(HPETState, timers, [0 .. num_timers], VMSTATE_HPET_TIMER,
BqlRefCell).with_version_id(0)
But this breaks current type check, because it checks t
On 2025/03/21 13:34, Yui Washizu wrote:
I tested the following features with this patch series, and there were
not issues:
- Creation and deletion of VFs
- Communication with an external machine through VFs
Thank you.
Can you reply with:
Tested-by: Your Name
This tag means:
- you have t
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/alpha/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 935ad2ee1ae..99d839a2792 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -239,
Those files will be compiled once per base architecture ("arm" in this
case), instead of being compiled for every variant/bitness of
architecture.
We make sure to not include target cpu definitions (exec/cpu-defs.h) by
defining header guard directly. This way, a given compilation unit can
access a
On 23/3/25 18:37, Richard Henderson wrote:
We want to be able to do more common work on MachineClass.
Pass the class name as a string in .class_data.
Signed-off-by: Richard Henderson
---
hw/avr/arduino.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
Reviewed-by: P
On Wed, Mar 19, 2025 at 09:26:29AM +, Shameerali Kolothum Thodi wrote:
> Having said that, current code only allows pxb-pcie root complexes avoiding
> the pcie.0. The idea behind this was, user can use pcie.0 with a non accel
> SMMUv3
> for any emulated devices avoiding the performance bottle
Rust cannot infer the type (it should be VMStateField) after
Zeroable::ZERO, which cause the compiling error.
To fix this error, call with_varray_flag() after VMStateField's
initialization.
Signed-off-by: Zhao Liu
---
rust/qemu-api/src/vmstate.rs | 16 +---
1 file changed, 9 inserti
This patch adds the OTP memory and its controller as part of the
Secure Boot Controller (SBC) device model. The OTP memory content is
persisted to a file named 'otpmem', which is created if it does not
already exist.
Signed-off-by: Kane-Chen-AS
---
hw/misc/aspeed_sbc.c | 304
On 3/23/25 10:37, Richard Henderson wrote:
Increase TARGET_PHYS_ADDR_SPACE_BITS to allow flexibility in the page
size without triggering an assert. Select the page size based on the
size of sram. This leaves sram on exactly one page and minimizes the
number of pages required to span the flash.
While the first kernel boots, it registers memory regions for fadump
such as:
* CPU state data (has to be populated by the platform)
* HPTE state data (has to be populated by the platform)
* Real Mode Regions (platform should copy it to requested
destination addresses)
* OS d
On Tue, 11 Mar 2025, Cornelia Huck wrote:
+++ b/scripts/gen-cpu-sysregs-header.awk
[...]
+BEGIN {
+print ""
+} END {
+print ""
+}
+
+# skip blank lines and comment lines
+/^$/ { next }
+/^[\t ]*#/ { next }
+
+/^Sysreg\t/ || /^Sysreg /{
+
+ reg = $2
+ op0 = $3
+ op1 = $
On 4/3/25 08:18, Philippe Mathieu-Daudé wrote:
Since commit cc5e719e2c8 ("kvm: require KVM_CAP_SIGNAL_MSI"),
its_class_name() single implementation doesn't return NULL
anymore. Update the prototype docstring, and remove the
pointless checks.
Reported-by: Gustavo Romero
Signed-off-by: Philippe Ma
When using a VDPA device, it's important to ensure that the MAC
address is correctly set.
Add a new parameter in qemu cmdline to enable this check, default value
is false
The usage is:
-netdev
type=vhost-vdpa,vhostdev=/dev/vhost-vdpa-0,id=vhost-vdpa0,check-mac=true\
-device virtio-net-pci,ne
On 1/4/25 00:49, Philippe Mathieu-Daudé wrote:
Hi Joel,
On 19/11/24 11:29, Peter Maydell wrote:
On Tue, 19 Nov 2024 at 02:53, Joel Stanley wrote:
On Mon, 18 Nov 2024 at 20:40, Peter Maydell
wrote:
Have you reviewed all the device read/write function
implementations for these devices to ch
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