Re: [PATCH] target/rx: Fix copy/paste typo (riscv -> rx)

On 4/1/25 02:20, Philippe Mathieu-Daudé wrote: Rename riscv_cpu_mmu_index() -> rx_cpu_mmu_index(). Fixes: ef5cc166da1 ("target/rx: Populate CPUClass.mmu_index") Signed-off-by: Philippe Mathieu-Daudé --- target/rx/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by:

[PATCH 1/3] aio-posix: treat io_uring setup failure as fatal

In the early days of io_uring it was possible for io_uring_setup(2) to fail due to exhausting RLIMIT_MEMLOCK. QEMU's solution was to fall back to epoll(7) or ppoll(2) when io_uring could not be used in an AioContext. Nowadays io_uring memory is accounted differently so io_uring_setup(2) won't fail

[PATCH-for-10.0] tcg: Allocate TEMP_VAL_MEM frame in temp_load()

Be sure to allocate the temp frame if it wasn't. Fixes: c896fe29d6c ("TCG code generator") Reported-by: Michael Tokarev Reported-by: Helge Konetzka Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2891 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2899 Signed-off-by: Philippe Ma

[PATCH v8 38/55] i386/tdx: Set and check kernel_irqchip mode for TDX

KVM mandates kernel_irqchip to be split mode. Set it to split mode automatically when users don't provide an explicit value, otherwise check it to be the split mode. Suggested-by: Daniel P. Berrangé Signed-off-by: Xiaoyao Li --- target/i386/kvm/tdx.c | 8 1 file changed, 8 insertions(

Re: [PATCH 11/15] fuse: Manually process requests (without libfuse)

On Tue, Mar 25, 2025 at 05:06:51PM +0100, Hanna Czenczek wrote: > Manually read requests from the /dev/fuse FD and process them, without > using libfuse. This allows us to safely add parallel request processing > in coroutines later, without having to worry about libfuse internals. > (Technically,

Re: [PATCH v2 09/42] include/exec: Inline *_data memory operations

On 18/3/25 22:31, Richard Henderson wrote: These need to be per-target for 'abi_ptr'. Expand inline to the *_data_ra api with ra == 0. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 123 ++-- accel/tcg/ldst_c

Re: [PATCH] bsd-user: add option to enable plugins

On 1/4/25 16:33, Pierrick Bouvier wrote: On 3/31/25 23:15, Philippe Mathieu-Daudé wrote: Hi Pierrick, On 1/4/25 01:42, Pierrick Bouvier wrote: Nothing prevent plugins to be enabled on this platform for user binaries, only the option in the driver is missing. Per commit 903e870f245 ("plugins/

Re: [PATCH qemu 1/1] Add IOURING_SETUP_SINGLE_ISSUER flag to improve iouring performance

On Thu, Mar 27, 2025 at 02:14:25PM +0100, Kevin Wolf wrote: > Am 26.03.2025 um 18:46 hat Stefan Hajnoczi geschrieben: > > On Wed, Mar 26, 2025 at 06:13:44PM +0100, Kevin Wolf wrote: > > > Am 25.03.2025 um 21:49 hat ~h0lyalg0rithm geschrieben: > > > > From: Suraj Shirvankar > > > > > > > > Signed-

[PATCH 3/3] block/io_uring: use aio_add_sqe()

AioContext has its own io_uring instance for file descriptor monitoring. The disk I/O io_uring code was developed separately. Originally I thought the characteristics of file descriptor monitoring and disk I/O were too different, requiring separate io_uring instances. Now it has become clear to me

[PATCH 0/3] [RESEND] block: unify block and fdmon io_uring

For some reason the patch series didn't reach the mailing list. Resending. Every AioContext has an io_uring context for file descriptor monitoring. In addition, block/io_uring.c also has an io_uring context for disk I/O. This patch series eliminates the extra io_uring context so that AioContext ha

[PATCH 2/3] aio-posix: add aio_add_sqe() API for user-defined io_uring requests

Introduce the aio_add_sqe() API for submitting io_uring requests in the current AioContext. This allows other components in QEMU, like the block layer, to take advantage of io_uring features without creating their own io_uring context. This API supports nested event loops just like file descriptor

[PATCH v8 15/55] i386/tdx: Implement user specified tsc frequency

Reuse "-cpu,tsc-frequency=" to get user wanted tsc frequency and call VM scope VM_SET_TSC_KHZ to set the tsc frequency of TD before KVM_TDX_INIT_VM. Besides, sanity check the tsc frequency to be in the legal range and legal granularity (required by TDX module). Signed-off-by: Xiaoyao Li Acked-by

Re: [PATCH v3 2/5] ipmi: add fwinfo to pci ipmi devices

On 1/4/25 16:01, Nicholas Piggin wrote: This requires some adjustments to callers to avoid possible behaviour changes for PCI devices. Signed-off-by: Nicholas Piggin --- include/hw/ipmi/ipmi.h | 5 + hw/acpi/ipmi.c | 3 ++- hw/ipmi/isa_ipmi_bt.c | 1 + hw/ipmi/i

Re: [PATCH] bsd-user: add option to enable plugins

On 4/1/25 07:44, Philippe Mathieu-Daudé wrote: On 1/4/25 16:33, Pierrick Bouvier wrote: On 3/31/25 23:15, Philippe Mathieu-Daudé wrote: Hi Pierrick, On 1/4/25 01:42, Pierrick Bouvier wrote: Nothing prevent plugins to be enabled on this platform for user binaries, only the option in the driver

Re: [PATCH 14/15] fuse: Implement multi-threading

On Tue, Mar 25, 2025 at 05:06:54PM +0100, Hanna Czenczek wrote: > FUSE allows creating multiple request queues by "cloning" /dev/fuse FDs > (via open("/dev/fuse") + ioctl(FUSE_DEV_IOC_CLONE)). > > We can use this to implement multi-threading. > > Note that the interface presented here differs fro

Re: [PATCH-for-10.1 3/3] exec: Do not include 'accel/tcg/cpu-ldst.h' in 'exec-all.h'

On 4/1/25 01:32, Philippe Mathieu-Daudé wrote: Only 2 files requiring "accel/tcg/cpu-ldst.h" API do not include it: - accel/tcg/cpu-exec.c - target/arm/tcg/sve_helper.c Include it there and remove it from "exec/exec-all.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier

Re: [PATCH-for-10.1 2/3] exec: Restrict 'cpu_ldst.h' to accel/tcg/

On 4/1/25 01:32, Philippe Mathieu-Daudé wrote: Mechanical change using: $ sed -i -e 's,exec/cpu_ldst,accel/tcg/cpu-ldst,' \ $(git grep -l exec/cpu_ldst.h) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier

[PATCH v8 08/55] i386/tdx: Initialize TDX before creating TD vcpus

Invoke KVM_TDX_INIT_VM in kvm_arch_pre_create_vcpu() that KVM_TDX_INIT_VM configures global TD configurations, e.g. the canonical CPUID config, and must be executed prior to creating vCPUs. Use kvm_x86_arch_cpuid() to setup the CPUID settings for TDX VM. Note, this doesn't address the fact that Q

Re: [PATCH v4] target/ppc: Deprecate Power8E and Power8NVL

On 1/4/25 11:54, Aditya Gupta wrote: On 25/03/31 01:37PM, Philippe Mathieu-Daudé wrote: On 30/3/25 23:10, Aditya Gupta wrote: <...snip...> Reviewed-by: Philippe Mathieu-Daudé Thanks for the tag, Philippe ! I will be posting a v5 with this patch split into 2 as suggested by Cedric (one int

[PATCH v4 1/3] system/runstate: add VM state change cb with return value

This patch adds the new VM state change cb type `VMChangeStateHandlerWithRet`, which has return value for `VMChangeStateEntry`. Thus, we can register a new VM state change cb with return value for device. Note that `VMChangeStateHandler` and `VMChangeStateHandlerWithRet` are mutually exclusive and

[PATCH v4 0/3] vhost: fix the IO error after live migration

At the end of the VM live migration, the vhost device will be stopped. Currently, if the vhost-user backend crashes, vhost device's set_status() would not return failure, live migration won't perceive the disconnection with the backend. After the live migration is successful, the stale inflight IO

[PATCH v8 04/55] i386/tdx: Implement tdx_kvm_init() to initialize TDX VM context

Implement TDX specific ConfidentialGuestSupportClass::kvm_init() callback, tdx_kvm_init(). Mark guest state is proctected for TDX VM. More TDX specific initialization will be added later. Signed-off-by: Xiaoyao Li --- Changes in v6: - remove Acked-by from Gerd since the patch changed due to us

[PATCH-for-10.1 00/24] cpus: Restrict SoftMMU mmu_index() to TCG

mmu_index() is specific to TCG SoftMMU, move CPUClass::mmu_index() to TCGCPUOps::mmu_index(). Philippe Mathieu-Daudé (24): hw/core/cpu: Update CPUClass::mmu_index docstring accel/tcg: Introduce TCGCPUOps::mmu_index() callback target/alpha: Restrict SoftMMU mmu_index() to TCG target/arm: Re

[PATCH-for-10.1 1/3] exec: Restrict 'cpu-ldst-common.h' to accel/tcg/

Signed-off-by: Philippe Mathieu-Daudé --- include/{exec => accel/tcg}/cpu-ldst-common.h | 6 +++--- include/exec/cpu_ldst.h | 2 +- accel/tcg/translator.c| 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) rename include/{exec => accel/tcg}/cpu-

Re: [PATCH] vhost: Don't set vring call if guest notifier is unused

On Wed, Mar 26, 2025 at 04:25:37PM +0800, oen...@gmail.com wrote: From: Huaitong Han The vring call fd is set even when the guest does not use msix (e.g., in the case of virtio pmd), leading to unnecessary CPU overhead for processing interrupts. The previous patch optimized the condition where

[PATCH-for-10.1 3/3] exec: Do not include 'accel/tcg/cpu-ldst.h' in 'exec-all.h'

Only 2 files requiring "accel/tcg/cpu-ldst.h" API do not include it: - accel/tcg/cpu-exec.c - target/arm/tcg/sve_helper.c Include it there and remove it from "exec/exec-all.h". Signed-off-by: Philippe Mathieu-Daudé --- include/exec/exec-all.h | 3 --- accel/tcg/cpu-exec.c| 1 + targe

[PATCH v8 02/55] i386: Introduce tdx-guest object

Introduce tdx-guest object which inherits X86_CONFIDENTIAL_GUEST, and will be used to create TDX VMs (TDs) by qemu -machine ...,confidential-guest-support=tdx0 \ -object tdx-guest,id=tdx0 It has one QAPI member 'attributes' defined, which allows user to set TD's attributes directly.

[PATCH v8 19/55] i386/tdx: Don't initialize pc.rom for TDX VMs

For TDX, the address below 1MB are entirely general RAM. No need to initialize pc.rom memory region for TDs. Signed-off-by: Xiaoyao Li --- This is more as a workaround of the issue that for q35 machine type, the real memslot update (which requires memslot deletion )for pc.rom happens after tdx_in

[PATCH v8 14/55] i386/tdx: Set APIC bus rate to match with what TDX module enforces

TDX advertises core crystal clock with cpuid[0x15] as 25MHz for TD guests and it's unchangeable from VMM. As a result, TDX guest reads the APIC timer as the same frequency, 25MHz. While KVM's default emulated frequency for APIC bus is 1GHz, set the APIC bus rate to match with TDX explicitly to ens

[PATCH v8 32/55] i386/tdx: implement tdx_cpu_instance_init()

Currently, pmu is not supported for TDX by KVM. Signed-off-by: Xiaoyao Li --- chanegs in v6: - new patch; --- target/i386/kvm/tdx.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 282cdbd775c5..49e748af3949 100644 --- a/target/i386/k

Re: [PATCH 1/3] target/mips: Revert TARGET_PAGE_BITS_VARY

On 3/31/25 20:15, Huacai Chen wrote: # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif #endif -#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 -#else -#define TARGET_PAGE_BITS_VARY -#define TARGET_PAGE_BITS_MIN 12 -#endif I'm a bit confused about TARGET_PAGE_BITS and other macros. In

Re: [PATCH 01/15] fuse: Copy write buffer content before polling

On Tue, Mar 25, 2025 at 05:06:35PM +0100, Hanna Czenczek wrote: > Polling in I/O functions can lead to nested read_from_fuse_export() > calls, overwriting the request buffer's content. The only function > affected by this is fuse_write(), which therefore must use a bounce > buffer or corruption ma

Re: [PATCH 6/6] tests/qtest: Enable bios-tables-test for LoongArch

On Fri, 28 Feb 2025 17:27:29 +0800 Bibo Mao wrote: > Enable bios-tables-test for LoongArch virt machine, it passes to run > with command "make check-qtest-loongarch64". > > Signed-off-by: Bibo Mao I suggest merging it into of 3/6 > --- > tests/qtest/meson.build | 3 ++- > 1 file changed, 2 i

[PATCH v8 07/55] kvm: Introduce kvm_arch_pre_create_vcpu()

Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent work prior to create any vcpu. This is for i386 TDX because it needs call TDX_INIT_VM before creating any vcpu. The specific implemnet of i386 will be added in the future patch. Signed-off-by: Xiaoyao Li Acked-by: Gerd Hoffmann ---

Re: [PATCH v2 2/3] include: Add a header to define PCI MMIO functions

On 3/31/2025 6:46 AM, Stefan Hajnoczi wrote: On Fri, Mar 28, 2025 at 12:06:26PM -0700, Farhan Ali wrote: Add a generic QEMU API for PCI MMIO reads/writes. The functions access little endian memory and returns the result in host cpu endianness. Signed-off-by: Farhan Ali --- include/qemu/pci

[PATCH v8 22/55] headers: Add definitions from UEFI spec for volumes, resources, etc...

Add UEFI definitions for literals, enums, structs, GUIDs, etc... that will be used by TDX to build the UEFI Hand-Off Block (HOB) that is passed to the Trusted Domain Virtual Firmware (TDVF). All values come from the UEFI specification [1], PI spec [2] and TDVF design guide[3]. [1] UEFI Specificat

[PATCH v8 17/55] i386/tdvf: Introduce function to parse TDVF metadata

From: Isaku Yamahata TDX VM needs to boot with its specialized firmware, Trusted Domain Virtual Firmware (TDVF). QEMU needs to parse TDVF and map it in TD guest memory prior to running the TDX VM. A TDVF Metadata in TDVF image describes the structure of firmware. QEMU refers to it to setup memor

[PATCH v8 20/55] i386/tdx: Track mem_ptr for each firmware entry of TDVF

For each TDVF sections, QEMU needs to copy the content to guest private memory via KVM API (KVM_TDX_INIT_MEM_REGION). Introduce a field @mem_ptr for TdxFirmwareEntry to track the memory pointer of each TDVF sections. So that QEMU can add/copy them to guest private memory later. TDVF sections can

[PATCH v8 21/55] i386/tdx: Track RAM entries for TDX VM

The RAM of TDX VM can be classified into two types: - TDX_RAM_UNACCEPTED: default type of TDX memory, which needs to be accepted by TDX guest before it can be used and will be all-zeros after being accepted. - TDX_RAM_ADDED: the RAM that is ADD'ed to TD guest before running, and can be

[PATCH v8 46/55] i386/tdx: Add supported CPUID bits related to TD Attributes

For TDX, some CPUID feature bit is configured via TD attributes. They are not covered by tdx_caps.cpuid (which only contians the configurable bits), but they are actually supported when the related attributre bit is supported. Signed-off-by: Xiaoyao Li --- target/i386/cpu.h | 4 +++ target/

[PATCH v8 30/55] kvm: Check KVM_CAP_MAX_VCPUS at vm level

KVM with TDX support starts to report different KVM_CAP_MAX_VCPUS per different VM types. So switch to check the KVM_CAP_MAX_VCPUS at vm level. KVM still returns the global KVM_CAP_MAX_VCPUS when the KVM is old that doesn't report different value at vm level. Signed-off-by: Xiaoyao Li --- accel

[PATCH v8 24/55] i386/tdx: Add TDVF memory via KVM_TDX_INIT_MEM_REGION

From: Isaku Yamahata TDVF firmware (CODE and VARS) needs to be copied to TD's private memory via KVM_TDX_INIT_MEM_REGION, as well as TD HOB and TEMP memory. If the TDVF section has TDVF_SECTION_ATTRIBUTES_MR_EXTEND set in the flag, calling KVM_TDX_EXTEND_MEMORY to extend the measurement. After

[PATCH v8 33/55] i386/cpu: Introduce enable_cpuid_0x1f to force exposing CPUID 0x1f

Currently, QEMU exposes CPUID 0x1f to guest only when necessary, i.e., when topology level that cannot be enumerated by leaf 0xB, e.g., die or module level, are configured for the guest, e.g., -smp xx,dies=2. However, TDX architecture forces to require CPUID 0x1f to configure CPU topology. Introd

[PATCH v8 10/55] i386/tdx: Make sept_ve_disable set by default

From: Isaku Yamahata For TDX KVM use case, Linux guest is the most major one. It requires sept_ve_disable set. Make it default for the main use case. For other use case, it can be enabled/disabled via qemu command line. Signed-off-by: Isaku Yamahata Signed-off-by: Xiaoyao Li --- target/i38

[PATCH v8 52/55] i386/tdx: Don't treat SYSCALL as unavailable

Signed-off-by: Xiaoyao Li --- Changes in v7: - fix CPUID_EXT2_SYSCALL by adding it to actual; --- target/i386/kvm/tdx.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 58797470ba7e..cd8e96d476b8 100644 --- a/target/i386/kvm/t

[PATCH v8 06/55] i386/tdx: Introduce is_tdx_vm() helper and cache tdx_guest object

It will need special handling for TDX VMs all around the QEMU. Introduce is_tdx_vm() helper to query if it's a TDX VM. Cache tdx_guest object thus no need to cast from ms->cgs every time. Signed-off-by: Xiaoyao Li Acked-by: Gerd Hoffmann Reviewed-by: Isaku Yamahata --- changes in v3: - replace

Re: [PATCH 3/6] tests/qtest/bios-tables-test: Add basic testing for LoongArch64

On Fri, 28 Feb 2025 17:27:26 +0800 Bibo Mao wrote: > Add basic ACPI table test case for LoongArch64. > > Signed-off-by: Bibo Mao > --- > tests/qtest/bios-tables-test.c | 62 ++ > 1 file changed, 62 insertions(+) > > diff --git a/tests/qtest/bios-tables-test.c b

[PATCH v8 18/55] i386/tdx: Parse TDVF metadata for TDX VM

After TDVF is loaded to bios MemoryRegion, it needs parse TDVF metadata. Signed-off-by: Xiaoyao Li Acked-by: Gerd Hoffmann --- hw/i386/pc_sysfw.c | 7 +++ target/i386/kvm/tdx-stub.c | 5 + target/i386/kvm/tdx.c | 5 + target/i386/kvm/tdx.h | 3 +++ 4 files changed,

[PATCH v8 03/55] i386/tdx: Implement tdx_kvm_type() for TDX

TDX VM requires VM type to be KVM_X86_TDX_VM. Implement tdx_kvm_type() as X86ConfidentialGuestClass->kvm_type. Signed-off-by: Xiaoyao Li --- Changes in v6: - new added patch; --- target/i386/kvm/kvm.c | 1 + target/i386/kvm/tdx.c | 12 2 files changed, 13 insertions(+) diff --git

[PATCH v8 37/55] i386/tdx: Disable PIC for TDX VMs

Legacy PIC (8259) cannot be supported for TDX VMs since TDX module doesn't allow directly interrupt injection. Using posted interrupts for the PIC is not a viable option as the guest BIOS/kernel will not do EOI for PIC IRQs, i.e. will leave the vIRR bit set. Hence disable PIC for TDX VMs and erro

[PATCH v8 54/55] i386/tdx: Validate phys_bits against host value

For TDX guest, the phys_bits is not configurable and can only be host/native value. Validate phys_bits inside tdx_check_features(). Signed-off-by: Xiaoyao Li --- target/i386/host-cpu.c | 2 +- target/i386/host-cpu.h | 1 + target/i386/kvm/tdx.c | 8 3 files changed, 10 insertions(+),

[PATCH v8 25/55] i386/tdx: Call KVM_TDX_INIT_VCPU to initialize TDX vcpu

TDX vcpu needs to be initialized by SEAMCALL(TDH.VP.INIT) and KVM provides vcpu level IOCTL KVM_TDX_INIT_VCPU for it. KVM_TDX_INIT_VCPU needs the address of the HOB as input. Invoke it for each vcpu after HOB list is created. Signed-off-by: Xiaoyao Li Acked-by: Gerd Hoffmann --- target/i386/kv

[PATCH v8 51/55] i386/tdx: Fetch and validate CPUID of TD guest

Use KVM_TDX_GET_CPUID to get the CPUIDs that are managed and enfored by TDX module for TD guest. Check QEMU's configuration against the fetched data. Print wanring message when 1. a feature is not supported but requested by QEMU or 2. QEMU doesn't want to expose a feature while it is enforced ena

[PATCH v8 34/55] i386/tdx: Force exposing CPUID 0x1f

TDX uses CPUID 0x1f to configure TD guest's CPU topology. So set enable_cpuid_0x1f for TDs. Signed-off-by: Xiaoyao Li --- target/i386/kvm/tdx.c | 4 1 file changed, 4 insertions(+) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index 49e748af3949..b0616eb3d371 100644 --- a/targ

[PATCH v8 43/55] i386/cgs: Rename *mask_cpuid_features() to *adjust_cpuid_features()

Because for TDX case, there are also fixed-1 bits that enfored by TDX module. Signed-off-by: Xiaoyao Li --- target/i386/confidential-guest.h | 20 ++-- target/i386/kvm/kvm.c| 2 +- target/i386/sev.c| 4 ++-- 3 files changed, 13 insertions(+), 13 dele

Re: [PATCH 0/6] Add bios-tables-test for LoongArch64 system

On Fri, 28 Feb 2025 17:27:23 +0800 Bibo Mao wrote: > This patchset add bios-tables-test for LoongArch64 virt machine > system. It works with UEFI bios, with uefi-test-tools LoongArch64 > support is added to build bios-tables-test.loongarch64.iso. > > Also with test case bios-tables-test, LoongAr

Re: [PATCH 4/6] tests/acpi: Add empty ACPI data files for LoongArch64

On Fri, 28 Feb 2025 17:27:27 +0800 Bibo Mao wrote: > Add empty acpi table for LoongArch64 virt machine, it is only empty > file and there is no data in these files. this patch after 3/6 doesn't make sense, either drop. Adding empty blobs, can be useful (as then you can get ACPI diff during test

[PATCH v8 48/55] i386/tdx: Add XFD to supported bit of TDX

Just mark XFD as always supported for TDX. This simple solution relies on the fact KVM will report XFD as 0 when it's not supported by the hardware. Signed-off-by: Xiaoyao Li --- target/i386/cpu.h | 1 + target/i386/kvm/tdx.c | 5 + 2 files changed, 6 insertions(+) diff --git a/target/i

[PATCH v8 53/55] i386/tdx: Make invtsc default on

Because it's fixed1 bit that enforced by TDX module. Signed-off-by: Xiaoyao Li --- target/i386/kvm/tdx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index cd8e96d476b8..8f075ba5a4de 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/

[PATCH v8 40/55] i386/tdx: Only configure MSR_IA32_UCODE_REV in kvm_init_msrs() for TDs

For TDs, only MSR_IA32_UCODE_REV in kvm_init_msrs() can be configured by VMM, while the features enumerated/controlled by other MSRs except MSR_IA32_UCODE_REV in kvm_init_msrs() are not under control of VMM. Only configure MSR_IA32_UCODE_REV for TDs. Signed-off-by: Xiaoyao Li Acked-by: Gerd Hoff

[PATCH v8 50/55] i386/cgs: Introduce x86_confidential_guest_check_features()

To do cgs specific feature checking. Note the feature checking in x86_cpu_filter_features() is valid for non-cgs VMs. For cgs VMs like TDX, what features can be supported has more restrictions. Signed-off-by: Xiaoyao Li --- target/i386/confidential-guest.h | 13 + target/i386/kvm/kvm

[PATCH v3 3/5] ipmi/bmc-sim: Add 'Get Channel Info' command

Linux issues this command when booting a powernv machine. Signed-off-by: Nicholas Piggin --- include/hw/ipmi/ipmi.h | 10 +++ hw/ipmi/ipmi_bmc_sim.c | 68 -- hw/ipmi/ipmi_bt.c | 2 ++ hw/ipmi/ipmi_kcs.c | 1 + 4 files changed, 79 insertions(

[PATCH v3 0/5] ipmi: bmc-sim improvements

These little things came up when looking at behaviour of IPMI with the bmc-sim implementation running the ppc powernv machine, and trying to clean up error messages and missing features. Since v1 (thanks to Corey for review and suggestions): - Added fwinfo to PCI devices - Report interrupt number

[PATCH v8 26/55] i386/tdx: Finalize TDX VM

Invoke KVM_TDX_FINALIZE_VM to finalize the TD's measurement and make the TD vCPUs runnable once machine initialization is complete. Signed-off-by: Xiaoyao Li Acked-by: Gerd Hoffmann --- target/i386/kvm/tdx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/i386/kvm/tdx.c b/target/i

[PATCH v8 41/55] i386/apic: Skip kvm_apic_put() for TDX

KVM neithers allow writing to MSR_IA32_APICBASE for TDs, nor allow for KVM_SET_LAPIC[*]. Note, KVM_GET_LAPIC is also disallowed for TDX. It is called in the path do_kvm_cpu_synchronize_state() -> kvm_arch_get_registers() -> kvm_get_apic() and it's already disllowed for confidential gues

Re: [PATCH v1 05/22] hw/misc/aspeed_hace: Introduce 64-bit digest_addr variable for AST2700

On 3/21/25 10:26, Jamin Lin wrote: The AST2700 CPU, based on the Cortex-A35, is a 64-bit processor with a 64-bit DRAM address space. To support future AST2700 updates, a new "digest_addr" variable is introduced with a 64-bit data type. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 4 ++

[PATCH v8 47/55] i386/tdx: Add supported CPUID bits relates to XFAM

Some CPUID bits are controlled by XFAM. They are not covered by tdx_caps.cpuid (which only contians the directly configurable bits), but they are actually supported when the related XFAM bit is supported. Add these XFAM controlled bits to TDX supported CPUID bits based on the supported_xfam. Besi

[PATCH v3 5/5] ipmi/bmc-sim: add error handling for 'Set BMC Global Enables' command

Mask out unsupported bits and return failure if attempting to set any. This is not required by the IPMI spec, but it does require that system software not change bits it isn't aware of. Signed-off-by: Nicholas Piggin --- hw/ipmi/ipmi_bmc_sim.c | 10 +- 1 file changed, 9 insertions(+), 1

Re: [PATCH v3 2/4] hw/s390x: add Control-Program Identification to QOM

On Mon, 2025-03-31 at 16:00 +0200, Shalini Chellathurai Saroja wrote: > Add Control-Program Identification data to the QEMU Object > Model (QOM), along with the timestamp in which the data was received. > > Example: > virsh # qemu-monitor-command vm --pretty '{ > "execute": "qom-get", > "arguments

[PATCH v8 29/55] i386/tdx: Wire TDX_REPORT_FATAL_ERROR with GuestPanic facility

Integrate TDX's TDX_REPORT_FATAL_ERROR into QEMU GuestPanic facility Originated-from: Isaku Yamahata Signed-off-by: Xiaoyao Li Acked-by: Markus Armbruster --- Changes in v8: - use g_strdup() for copy string; - use the new data ABI of KVM_SYSTEM_EVENT_TDX_FATAL to grab gpa info; Changes in v6:

[PATCH v8 23/55] i386/tdx: Setup the TD HOB list

The TD HOB list is used to pass the information from VMM to TDVF. The TD HOB must include PHIT HOB and Resource Descriptor HOB. More details can be found in TDVF specification and PI specification. Build the TD HOB in TDX's machine_init_done callback. Co-developed-by: Isaku Yamahata Signed-off-b

Re: [PATCH 1/2] vfio/migration: Add also max in-flight VFIO device state buffers size limit

On 11.03.2025 14:04, Cédric Le Goater wrote: On 3/7/25 14:45, Maciej S. Szmigiero wrote: On 7.03.2025 13:03, Cédric Le Goater wrote: On 3/7/25 11:57, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" There's already a max in-flight VFIO device state buffers *count* limit, no. there is

[PATCH v3 2/5] ipmi: add fwinfo to pci ipmi devices

This requires some adjustments to callers to avoid possible behaviour changes for PCI devices. Signed-off-by: Nicholas Piggin --- include/hw/ipmi/ipmi.h | 5 + hw/acpi/ipmi.c | 3 ++- hw/ipmi/isa_ipmi_bt.c | 1 + hw/ipmi/isa_ipmi_kcs.c | 1 + hw/ipmi/pci_ipmi_bt.

Re: [PATCH v1 06/22] hw/misc/aspeed_hace: Support accumulative mode for direct access mode

On 3/21/25 10:26, Jamin Lin wrote: Enable accumulative mode for direct access mode operations. In direct access mode, only a single source buffer is used, so the "iovec" count is set to 1. If "acc_mode" is enabled: 1. Accumulate "total_req_len" with the current request length ("plen"). 2. Check f

Re: [PATCH v2] target/ppc: Deprecate Power8E and Power8NVL

Also, we have time : the QEMU 10.1 development phase has not started and the soft freeze should be around July. No rush needed. Pre-release period is normally OK to deprecate things (Cc'ing Thomas in doubt...). I thought this was a fixes-only period, which might warrant spending some time on

[PATCH-for-10.1 03/24] target/alpha: Restrict SoftMMU mmu_index() to TCG

Signed-off-by: Philippe Mathieu-Daudé --- target/alpha/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 935ad2ee1ae..99d839a2792 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -239,6 +239,7 @@ static const TCGCPUO

[PATCH-for-10.1 24/24] exec: Restrict cpu-mmu-index.h to accel/tcg/

Signed-off-by: Philippe Mathieu-Daudé --- include/{exec => accel/tcg}/cpu-mmu-index.h | 6 +++--- include/exec/cpu_ldst.h | 2 +- accel/tcg/translator.c | 2 +- semihosting/uaccess.c | 2 +- target/arm/gdbstub64.c

[PATCH-for-10.1 04/24] target/arm: Restrict SoftMMU mmu_index() to TCG

Move arm_cpu_mmu_index() within CONFIG_TCG #ifdef'ry, convert CPUClass::mmu_index() to TCGCPUOps::mmu_index(). Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f2

[PATCH-for-10.1 07/24] target/i386: Remove unused cpu_(ldub, stb)_kernel macros

Signed-off-by: Philippe Mathieu-Daudé --- target/i386/tcg/seg_helper.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/target/i386/tcg/seg_helper.h b/target/i386/tcg/seg_helper.h index ebf10352778..6b8606cd6d8 100644 --- a/target/i386/tcg/seg_helper.h +++ b/target/i386/tcg/seg_helper.h @

[PATCH-for-10.1 12/24] target/microblaze: Restrict SoftMMU mmu_index() to TCG

Signed-off-by: Philippe Mathieu-Daudé --- target/microblaze/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f3bebea856e..88baeb6807a 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -431,6 +431,

[RFC PATCH-for-10.0] hw/vmapple: Allow running QTest framework on macOS

First, the VMapple machine only works with the ARM 'host' CPU type, which isn't accepted for QTest: $ qemu-system-aarch64 -M vmapple -accel qtest qemu-system-aarch64: The 'host' CPU type can only be used with KVM or HVF Second, the QTest framework expects machines to be createable without spe

[PATCH-for-10.1 05/24] target/avr: Restrict SoftMMU mmu_index() to TCG

Signed-off-by: Philippe Mathieu-Daudé --- target/avr/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 11218224704..feb73e722b3 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -228,6 +228,7 @@ static const TCGCPUOps avr_tcg

[PATCH-for-10.1 23/24] hw/core/cpu: Remove CPUClass::mmu_index()

All targets have been converted to TCGCPUOps::mmu_index(), remove the now unused CPUClass::mmu_index(). Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu-mmu-index.h | 4 +--- include/hw/core/cpu.h| 2 -- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/include/exec

[PATCH-for-10.1 20/24] target/sparc: Restrict SoftMMU mmu_index() to TCG

Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 1bf00407af7..072d5da5736 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -1005,6 +1005,7 @@ static const TCGCP

[PATCH-for-10.1 18/24] target/s390x: Restrict SoftMMU mmu_index() to TCG

Signed-off-by: Philippe Mathieu-Daudé --- target/s390x/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 1f75629ddc2..320ace67198 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -348,6 +348,7 @@ static const TCGCPUO

[PATCH-for-10.1 22/24] target/xtensa: Restrict SoftMMU mmu_index() to TCG

Signed-off-by: Philippe Mathieu-Daudé --- target/xtensa/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index ec6a0a8b662..51f9ee9e89a 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -236,6 +236,7 @@ static const TC

[PATCH] target/arm: Update comment around cpu_untagged_addr()

Since commit f9ba56a03c2 ("user: Introduce 'user/guest-host.h' header") cpu_untagged_addr() is only needed in "user/guest-host.h". Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h in

Re: [RFC PATCH 1/3] accel/tcg: Option to permit incoherent translation block cache vs stores

On Tue Apr 1, 2025 at 5:51 AM AEST, Richard Henderson wrote: > On 3/31/25 10:54, Nicholas Piggin wrote: >> Add an option TARGET_HAS_LAZY_ICACHE that does not invalidate TBs upon >> store, but instead tracks that the icache has become incoherent, and >> provides a tb_flush_incoherent() function that

[PATCH] target/rx: Fix copy/paste typo (riscv -> rx)

Rename riscv_cpu_mmu_index() -> rx_cpu_mmu_index(). Fixes: ef5cc166da1 ("target/rx: Populate CPUClass.mmu_index") Signed-off-by: Philippe Mathieu-Daudé --- target/rx/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 65e26e7a6b6.

[PATCH v4 1/3] io/block: Refactoring the bdrv_drained_begin() function and implement a timeout mechanism.

From: Zhu Yangyang The bdrv_drained_begin() function is a blocking function. In scenarios where network storage is used and network links fail, it may block for a long time. Therefore, we add a timeout parameter to control the duration of the block. Since bdrv_drained_begin() has been widely ad

[PATCH v4 0/3] qapi: Fix some command blocked for too long

From: Zhu Yangyang QMP may will be blocked for a long time on bdrv_drained_begin() when a network disk is configured and the network failure is just about to occur. In theory, any command may be blocked if it calls bdrv_drained_begin(). This series add a timeout parameter for qmp_block_set_io_t

Re: [PATCH v2 4/5] ipmi/bmc-sim: implement watchdog dont log flag

On Tue, Apr 01, 2025 at 09:44:11PM +1000, Nicholas Piggin wrote: > If the dont-log flag is set in the 'timer use' field for the > 'set watchdog' command, a watchdog timeout will not get logged as > a timer use expiration. > > Signed-off-by: Nicholas Piggin > --- > hw/ipmi/ipmi_bmc_sim.c | 32 +++

Re: [PATCH v2] target/ppc: Deprecate Power8E and Power8NVL

On 1/4/25 12:01, Aditya Gupta wrote: On 25/03/31 08:41AM, Cédric Le Goater wrote: On 3/29/25 15:26, Aditya Gupta wrote: Power8E and Power8NVL variants are not of much use in QEMU now, and not being maintained either. Newer skiboot might not be able to boot Power8NVL since skiboot v7.0 It is

Re: [PULL 23/29] ui & main loop: Redesign of system-specific main thread event handling

Hi David, On 8/1/25 14:51, David Woodhouse wrote: On Tue, 2024-12-31 at 21:22 +0100, Philippe Mathieu-Daudé wrote: This change tidies up main thread management to be more flexible.  * The qemu_main global function pointer is a custom function for the    main thread, and it may now be NULL.

[PATCH v2 0/5] ipmi: bmc-sim improvements

These little things came up when looking at behaviour of IPMI with the bmc-sim implementation running the ppc powernv machine, and trying to clean up error messages and missing features. Since v1 (thanks to Corey for review and suggestions): - Added fwinfo to PCI devices - Report interrupt number

Re: [PULL 23/29] ui & main loop: Redesign of system-specific main thread event handling

On Tue, 2025-04-01 at 13:30 +0200, Philippe Mathieu-Daudé wrote: > On 1/4/25 13:18, Philippe Mathieu-Daudé wrote: > > Hi David, > > > > On 8/1/25 14:51, David Woodhouse wrote: > > > On Tue, 2024-12-31 at 21:22 +0100, Philippe Mathieu-Daudé wrote: > > > > > > > > This change tidies up main thread

[PATCH v2 2/5] ipmi: add fwinfo to pci ipmi devices

This requires some adjustments to callers to avoid possible behaviour changes for PCI devices. Signed-off-by: Nicholas Piggin --- include/hw/ipmi/ipmi.h | 5 + hw/acpi/ipmi.c | 2 +- hw/ipmi/isa_ipmi_bt.c | 1 + hw/ipmi/isa_ipmi_kcs.c | 1 + hw/ipmi/pci_ipmi_bt.c

[PATCH v2 1/5] ipmi/pci-ipmi-bt: Rename copy-paste variables

IPMI drivers use p/k suffix in variable names depending on bt or kcs. The pci bt driver must have come from the kcs driver because it's still using k suffixes in some cases. Rename. Signed-off-by: Nicholas Piggin --- hw/ipmi/pci_ipmi_bt.c | 38 +++--- 1 file chang

[PATCH v2 3/5] ipmi/bmc-sim: Add 'Get Channel Info' command

Linux issues this command when booting a powernv machine. Signed-off-by: Nicholas Piggin --- include/hw/ipmi/ipmi.h | 14 + hw/ipmi/ipmi_bmc_sim.c | 65 -- hw/ipmi/ipmi_bt.c | 2 ++ hw/ipmi/ipmi_kcs.c | 1 + 4 files changed, 80 insertion

Re: [PULL 23/29] ui & main loop: Redesign of system-specific main thread event handling

On 1/4/25 13:18, Philippe Mathieu-Daudé wrote: Hi David, On 8/1/25 14:51, David Woodhouse wrote: On Tue, 2024-12-31 at 21:22 +0100, Philippe Mathieu-Daudé wrote: This change tidies up main thread management to be more flexible.   * The qemu_main global function pointer is a custom function f

  1   2   >