> 2025年3月24日 22:31，Stefano Garzarella 写道：
>
> On Thu, Mar 20, 2025 at 08:21:30PM +0800, Haoqian He wrote:
>>
>>
>>> 2025年3月19日 23:20，Stefano Garzarella 写道：
>>>
>>> On Fri, Mar 14, 2025 at 06:15:34AM -0400, Haoqian He wrote:
Live migration should be terminated if the backend crashes bef
On 2025/3/24 下午8:33, Xianglai Li wrote:
When the cpu is created, qemu_add_vm_change_state_handler
is called in the kvm_arch_init_vcpu function to create
the VMChangeStateEntry resource.
However, the resource is not released when the cpu is destroyed.
This results in a qemu process segment err
From: Thomas Huth
It is possible nowadays to compile QEMU without pixman support - in that
case the screendump command is not available and the related tests fail.
Thus skip these tests if the screendump command could not be executed.
Signed-off-by: Thomas Huth
---
tests/functional/test_arm_in
John Snow writes:
> This patch changes the qapidoc transmogrifier to generate Return value
> documentation for any command that has a return value but hasn't
> explicitly documented that return value.
>
> Signed-off-by: John Snow
A number of commands lack return value documentation before the p
Introduce Power11 ChipTod. The code has been copied from Power10 ChipTod
code as the Power11 core is same as Power10 core.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c
Overview
Add support for Power11 powernv machine type.
As Power11 core is same as Power10, hence much of the code has been reused
from Power10.
Split Powernv11 chip/machine code into commits introducing:
chip,machine,xive,phb
This is to try to keep the code smaller in each commit,
Add a XIVE2 controller to Power11 chip and machine.
The controller has the same logic as Power10.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 132 +
Power11 core is same as Power10, declare PNV11_HOMER as a child
class of PNV10_HOMER, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
Power11 core is same as Power10, reuse PNV10_SBER initialisation, by
declaring PNV11_PSI as child class of PNV10_PSI
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
hw
Power11 core is same as Power10 core, declare PNV11_LPC as a child
class of PNV10_LPC, so it goes through same class init
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
--
Power11 also uses PHB5, same as Power10.
Add Power11 PHBs with similar code as the corresponding Power10 implementation.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya Gupta
---
hw/ppc/pnv.c | 57 ++
Power11 core is same as Power10, reuse PNV10_OCC initialisation,
by declaring `PNV11_OCC` as child class of `PNV10_OCC`
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
The Powernv11 machine doesn't have XIVE & PHBs as of now
XIVE2 interface and PHB5 added in later patches to Powernv11 machine
Also add mention of Power11 to powernv documentation
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Sig
Hi Cedric,
On 24/03/25 13:11, Cédric Le Goater wrote:
Hello Aditya,
On 3/8/25 21:51, Aditya Gupta wrote:
Overview
Add support for Power11 powernv machine type, to emulate PowerNV VMs
running on Power11.
Could you please consider deprecating the POWER8NVL and POWER8E CPUs
and as
Hi,
> > While digging around in the igvm spec I've seen there is the
> > concept of 'parameters'. Can this be used to pass on the memory
> > location of kernel + initrd + cmdline? Maybe the kernel hashes too?
>
> The find the locations of the kernel, initrd, cmdline, ... I thin
On 3/23/25 10:37, Richard Henderson wrote:
Do not unconditionally attempt to read 4 bytes, as there
may only be 2 bytes remaining in the translator cache.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Richard Henderson
---
target/avr/disas.c | 21 ++---
1 file changed, 14 inserti
On 24.03.25 18:53, Gerd Hoffman wrote:
On Mon, Mar 24, 2025 at 05:31:30PM +0100, Alexander Graf wrote:
What does all this mean for the hypervisor interface ?
That means we'll go scratch the region list idea and depend on igvm
instead.
Which means we are back to the single firmware image.
So
Hi,
I'm observing intermittent failures when enabling the HNS3 network port in VM
using
QEMU with the mainline kernel.
HNS3 drive in kernel:
static int hns3_nic_net_up(struct net_device *netdev)
{
..
/* enable the vectors */
for (i = 0; i < vector_num; i++)
{
napi_enable(napi);
John Snow writes:
> The pylint config is being left in place because the settings differ
> enough from the python/ directory settings that we need a chit-chat on
> how to merge them O:-)
>
> Everything else can go.
>
> Signed-off-by: John Snow
> ---
> scripts/qapi/.flake8| 3 ---
> scripts/
From: Thomas Huth
It is possible nowadays to compile QEMU without pixman support - in that
case the screendump command is not available and the related tests fail.
Thus skip these tests if the screendump command could not be executed.
Signed-off-by: Thomas Huth
---
tests/functional/test_arm_in
John Snow writes:
> The new qapidoc transmogrifier can generate "Returns" statements with
> type information just fine, so we can remove it from the source where it
> doesn't add anything particularly novel or helpful and just repeats the
> type info.
>
> This patch does not touch Returns: lines
On Tue, Mar 18, 2025 at 10:54:01AM +0100, Cédric Le Goater wrote:
> vfio_get_device_info() is a low level routine. Move it with the other
> helpers.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: John Levon
regards
john
John Snow writes:
> This patch changes the qapidoc transmogrifier to generate Return value
> documentation for any command that has a return value but hasn't
> explicitly documented that return value.
>
> Signed-off-by: John Snow
[...]
> diff --git a/scripts/qapi/parser.py b/scripts/qapi/parse
On Tue, Mar 25, 2025 at 04:39:46PM +0800, Haoqian He wrote:
2025年3月24日 22:31，Stefano Garzarella 写道：
On Thu, Mar 20, 2025 at 08:21:30PM +0800, Haoqian He wrote:
2025年3月19日 23:20，Stefano Garzarella
写道：
On Fri, Mar 14, 2025 at 06:15:34AM -0400, Haoqian He wrote:
[...]
diff --git a/include/hw/
Hello Fabiano,
On Tue, 18 Mar 2025 at 18:10, Prasad Pandit wrote:
> * This series (v8) splits earlier patch-2 which enabled multifd and
> postcopy options together into two separate patches. One modifies
> the channel discovery in migration_ioc_process_incoming() function,
> and second one
On Tue, Mar 25, 2025 at 04:36:53PM +0800, Haoqian He wrote:
2025年3月24日 22:25，Stefano Garzarella 写道：
On Thu, Mar 20, 2025 at 08:21:25PM +0800, Haoqian He wrote:
2025年3月19日 23:11，Stefano Garzarella 写道：
On Fri, Mar 14, 2025 at 06:15:33AM -0400, Haoqian He wrote:
The backend maybe crash when v
John Snow writes:
> This restores the linting baseline in qapidoc. The order of some imports
> have changed slightly due to configuring isort a little better: isort
Changed since when / what?
> was having difficulty understanding that "compat" and "qapidoc_legacy"
> were local modules because d
John Snow writes:
> Update the python tests to also check qapi. No idea why I didn't do this
> before. I guess I was counting on moving it under python/ and then just
> forgot after that was NACKed. Oops, this turns out to be really easy.
>
> flake8, isort and mypy use the tool configuration from
Sorry for accidentaly sending this patch twice.
My mail system reports that it can't be delivered to Peter Maydell
and I am trying to solve it.
On 3/25/25 1:17 PM, Anastasia Belova wrote:
From: Anastasia Belova
Add an assertion similar to that in the do_shr_narrow().
This will make sure th
From: Konstantin Shkolnyy
Add .set_vnet_le() function that always returns success, assuming that
vDPA h/w always implements LE data format. Otherwise, QEMU disables vDPA and
outputs the message:
"backend does not support LE vnet headers; falling back on userspace virtio"
Reviewed-by: Michael S.
From: Jamin Lin
The maximum padding size is either 64 or 128 bytes and should always be smaller
than "req_len". If "padding_size" exceeds "req_len", then
"req_len - padding_size" underflows due to "uint32_t" data type, leading to a
large incorrect value (e.g., `0xFFXX`). This causes an out-of
The following patches are queued for QEMU stable v8.2.10:
https://gitlab.com/qemu-project/qemu/-/commits/staging-8.2
Patch freeze is 2025-03-24 (frozen), and the release is planned for 2025-03-26:
https://wiki.qemu.org/Planning/8.2
Please respond here or CC qemu-sta...@nongnu.org on any add
From: Anastasia Belova
Add an assertion similar to that in the do_shr_narrow().
This will make sure that functions from sshll_ops
have correct arguments.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Anastasia Belova
---
target/arm/tcg/translate-sve.c | 1 +
Thomas Huth writes:
> From: Thomas Huth
>
> This test currently fails if the "dbus" display has not been compiled
> into the binary (which can happen when CFI has been enabled, for example).
> Check for the error message to skip the test in that case.
>
> While we're at it, also make sure that t
Xianglai,
Thanks for your patch, some comments inline.
On 2025/3/19 下午4:32, Xianglai Li wrote:
When only the -kernel parameter is used to load the elf kernel,
the initrd is loaded in the ram. If the initrd size is too large,
the loading fails, resulting in a VM startup failure.
This patch first
Am 06.03.2025 um 11:33 hat Kevin Wolf geschrieben:
> Am 04.03.2025 um 16:52 hat Alberto Faria geschrieben:
> > Avoid emulating FUA when the driver supports it natively. This should
> > provide better performance than a full flush after the write.
> >
> > Signed-off-by: Alberto Faria
>
> Did you
Keep CPUSPARCState for architectural fields, move Leon3
hardware specific fields to SPARCCPU.
Reset the Leon3 specific 'cache_control' field in
leon3_cpu_reset() instead of sparc_cpu_reset_hold().
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/cpu.h | 10 +-
hw/sparc/le
Following commit 554abe47c7b ("target/sparc: Partition cpu
features"), avoid compiling SPARC64 specific code on 32-bit
binary.
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/cpu-feature.h.inc | 20
target/sparc/translate.c | 10 --
2 files changed, 20 i
On 3/25/25 16:03, Philippe Mathieu-Daudé wrote:
On 25/3/25 23:43, Richard Henderson wrote:
This define isn't used.
Signed-off-by: Richard Henderson
---
target/avr/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 84a8f5cc8c..b49e7a7056 1006
On 3/25/25 06:48, Richard Henderson wrote:
On 3/24/25 18:07, Pierrick Bouvier wrote:
A simple nit, maybe we could define constant for register names. This way, it
can be used
in the two switch for read/access.
Which constant?
- The absolute address (0x58-0x5f)
- The i/o port address
From: Thomas Huth
The test checks some entries in /proc and the output of some commands ...
we put these checks into exportable functions now so that they can
be reused more easily.
Additionally the linux_ssh_mips_malta.py uses SSH to test the networking
of the guest. Since we don't have a SSH m
From: Thomas Huth
Reuse the test function from the big endian test to easily
convert the 32-bit little endian Wheezy mips test.
Signed-off-by: Thomas Huth
---
tests/avocado/linux_ssh_mips_malta.py | 8
tests/functional/meson.build | 1 +
tests/functional/test_mipsel_malta.p
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
target/alpha/cpu.h | 1 +
target/arm/cpu.h| 1 +
target/avr/cpu.h| 1 +
target/hppa/cpu.h | 1 +
target/i386/cpu.h | 1 +
target/loongarch/cpu.h | 1 +
target/m68k/cpu.h | 1 +
target/microb
On Tue, Mar 25, 2025 at 07:08:29PM +0100, Eric Auger wrote:
> > +static int
> > +smmuv3_accel_dev_install_nested_ste(SMMUv3AccelDevice *accel_dev,
> > +uint32_t data_type, uint32_t data_len,
> > +void *data)
> > +{
> > +SMM
On 3/25/25 16:13, Philippe Mathieu-Daudé wrote:
On 25/3/25 23:43, Richard Henderson wrote:
The comment about not being able to define a field with
zero bits is out of date since 94597b6146f3
("decodetree: Allow !function with no input bits").
This fixes the missing load of imm in the disassembl
Newer versions of Spice server should be able to accept dmabuf
fds from Qemu for clients that are connected via the network.
In other words, when this option is enabled, Qemu would share
a dmabuf fd with Spice which would encode and send the data
associated with the fd to a client that could be loc
In the specific case where the display layer (virtio-gpu) is using
dmabuf, and if remote clients are enabled (-spice gl=on,port=),
it makes sense to limit the maximum (streaming) rate to 60 FPS
using the GUI timer. This matches the behavior of GTK UI where the
display updates are submitted at 6
Giving users an option to choose a particular codec will enable
them to make an appropriate decision based on their hardware and
use-case.
Cc: Gerd Hoffmann
Cc: Marc-André Lureau
Cc: Dmitry Osipenko
Cc: Frediano Ziglio
Cc: Dongwon Kim
Signed-off-by: Vivek Kasireddy
---
qemu-options.hx | 5
Since most encoders/decoders (invoked by Spice) may not work with
tiled memory associated with a texture, we need to create another
texture that has linear memory layout and use that instead.
Note that, there does not seem to be a direct way to indicate to the
GL implementation that a texture's ba
In cases where the scanout buffer is provided as a texture (e.g. Virgl)
we need to check to see if it has a linear memory layout or not. If
it doesn't have a linear layout, then blitting it onto the texture
associated with the display surface (which already has a linear layout)
seems to ensure that
There are cases where we do not want the memory layout of a texture to
be tiled as the component processing the texture would not know how to
de-tile either via software or hardware. Therefore, ensuring that the
memory backing the texture has a linear layout is absolutely necessary
in these situati
On Mon, Mar 24, 2025 at 10:02 PM Marc-André Lureau
wrote:
>
> On Mon, Mar 24, 2025 at 5:35 PM Qiang Yu wrote:
> >
> > On Mon, Mar 24, 2025 at 5:30 PM Marc-André Lureau
> > wrote:
> > >
> > > Hi
> > >
> > > On Mon, Mar 24, 2025 at 12:20 PM wrote:
> > > >
> > > > From: Qiang Yu
> > > >
> > > > S
This device is part of SoC components thus can not
be created manually.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/nvram/xlnx-efuse.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
index 29e7dd539ec..176e88fcd17 100644
--- a/hw/nvram/xlnx-ef
On Tue, Mar 25, 2025 at 11:43:04PM +0100, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/i2c/i2c_mux_pca954x.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
Looks ok to me.
Acked-by: Corey Minyard
>
> diff --git a/hw/i2c/i2c_mux_pca954x.c b/
Integrate the i/o 0x00-0x1f and 0x38-0x3f loopbacks into
the cpu registers with normal address space accesses.
We no longer need to trap accesses to the first page within
avr_cpu_tlb_fill but can wait until a write occurs.
Signed-off-by: Richard Henderson
---
target/avr/cpu.h | 7 ++
tar
Signed-off-by: Richard Henderson
---
target/avr/cpu.h| 10 ++
target/avr/helper.c | 36 ++--
2 files changed, 28 insertions(+), 18 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index b49e7a7056..ebcdda20ac 100644
--- a/target/avr/cpu.h
Do not unconditionally attempt to read 4 bytes, as there
may only be 2 bytes remaining in the translator cache.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/avr/disas.c | 21 ++---
1 file changed, 14 insertions(+), 7 deleti
The comment about not being able to define a field with
zero bits is out of date since 94597b6146f3
("decodetree: Allow !function with no input bits").
This fixes the missing load of imm in the disassembler.
Cc: qemu-sta...@nongnu.org
Fixes: 9d8caa67a24 ("target/avr: Add support for disassembling
If i/o does not cover the entire first page, allocate a portion
of ram as an i/o device, so that the entire first page is i/o.
While memory_region_init_ram_device_ptr is happy to allocate
the RAMBlock, it does not register the ram for migration.
Do this by hand.
Signed-off-by: Richard Henderson
On Tue, Mar 25, 2025 at 5:41 AM Markus Armbruster wrote:
> John Snow writes:
>
> > This patch changes the qapidoc transmogrifier to generate Return value
> > documentation for any command that has a return value but hasn't
> > explicitly documented that return value.
> >
> > Signed-off-by: John
From: Deepak Gupta
Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds
`ssamoswap` instruction. `ssamoswap` takes the code-point from existing
reserved encoding (and not a zimop like other shadow stack instructions).
If shadow stack is not enabled (via xenvcfg.SSE) and effec
On Tue, Mar 25, 2025 at 4:54 AM Markus Armbruster wrote:
> John Snow writes:
>
> > This patch changes the qapidoc transmogrifier to generate Return value
> > documentation for any command that has a return value but hasn't
> > explicitly documented that return value.
> >
> > Signed-off-by: John
Hi,
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Allocates a s1 HWPT for the Guest s1 stage and attaches that
> to the dev. This will be invoked in a subsequent patch when
> Guest issues SMMU_CMD_CFGI_STE.
CMD_CFGI_STE ...
or CMD_CFGI_STE_RANGE
>
> While at it, we are also
Hi,
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Allocate and associate a vDEVICE object for the Guest device
> with the vIOMMU. This will help the kernel to do the
> vSID --> sid translation whenever required (eg: device specific
s/sid/SID
> invalidations).
>
> Signed-off
Power11 core is same as Power10, reuse PNV10_PSI initialisation, by
declaring 'PNV11_PSI' as child class of 'PNV10_PSI'
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Signed-off-by: Aditya Gupta
---
On 25/3/25 21:00, Thomas Huth wrote:
From: Thomas Huth
Now that all Avocado tests have been converted to or been replaced by
other functional tests, we can delete the remainders of the Avocado
tests from the QEMU source tree.
Signed-off-by: Thomas Huth
---
MAINTAINERS
On 3/24/25 21:36, Michael Tokarev wrote:
23.03.2025 20:45, Cédric Le Goater wrote:
Jamin Lin (1):
hw/misc/aspeed_hace: Fix buffer overflow in has_padding function
Steven Lee (1):
hw/intc/aspeed: Fix IRQ handler mask check
Troy Lee (1):
aspeed: Fix maximum number of spi con
From: Chao Liu
Recently, when I was writing a RISCV test, I found that when VL is set to 0, the
instruction should be nop, but when I tested it, I found that QEMU will treat
all elements as tail elements, and in the case of VTA=1, write all elements
to 1.
After troubleshooting, it was found that
On 25/03/25 22:50, Cédric Le Goater wrote:
On 3/25/25 12:23, Aditya Gupta wrote:
Implement Pnv11Chip, currently without chiptod, xive and phb.
Chiptod, XIVE, PHB are implemented in later patches.
Since Power11 core is same as Power10, the implementation of Pnv11Chip
is a duplicate of correspo
From: Thomas Huth
This way we can do a full boot in record-replay mode and
should get a similar test coverage compared to the old
replay test from tests/avocado/replay_linux.py. Thus remove
the x86 avocado replay_linux test now.
Signed-off-by: Thomas Huth
---
tests/avocado/replay_linux.py
From: Thomas Huth
We are going to move the remaining Avocado tests step by step
into the functional test framework. Unfortunately, Avocado fails
with an error if it cannot determine a test to run, so disable
the tests here now to avoid failures in the Gitlab-CI during the
next steps.
Signed-off-
From: Thomas Huth
test_x86_64_pc in tests/avocado/boot_linux_console.py only checks
whether the kernel parameters have correctly been passed to the
kernel in the guest by looking for them in the console output of the
guest. Let's move that to the functional test framework now, but
instead of doin
From: Thomas Huth
All tests that used this class have been converted to the functional
framework, so we can remove the boot_linux_console.py file now.
Signed-off-by: Thomas Huth
---
tests/avocado/boot_linux_console.py | 62 -
1 file changed, 62 deletions(-)
delete
From: Thomas Huth
Now that all Avocado tests have been converted to or been replaced by
other functional tests, we can delete the remainders of the Avocado
tests from the QEMU source tree.
Signed-off-by: Thomas Huth
---
MAINTAINERS | 8 +-
docs/about/build-platfor
On 3/20/25 15:29, Pierrick Bouvier wrote:
This does not hurt, even if they are not used.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a8a1a8faf6b..ab7412772bc 100644
--- a/target/arm/cpu.h
On 25/3/25 23:43, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/avr/cpu.h| 10 ++
target/avr/helper.c | 36 ++--
2 files changed, 28 insertions(+), 18 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 25/3/25 23:43, Richard Henderson wrote:
This define isn't used.
Signed-off-by: Richard Henderson
---
target/avr/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 84a8f5cc8c..b49e7a7056 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
Hi Shameer, Nicolin,
On 3/25/25 7:26 PM, Nicolin Chen wrote:
> On Tue, Mar 25, 2025 at 03:43:29PM +, Shameerali Kolothum Thodi wrote:
>>> For the record I tested the series with host VFIO device and a
>>> virtio-blk-pci device put behind the same pxb-pcie/smmu protection and
>>> it works just
From: Thomas Huth
These tests are based on the cloudinit functions from Avocado.
The cloudinit is very, very slow compared to our other tests,
so most of these Avocado tests have either been disabled by default
with a decorator, or have been marked to only run with KVM.
We won't include this slu
These patches convert the remaining Avocado tests bit by bit to the
functional framework, or replace them with a test that has similar
test coverage. This way we are finally able to get rid of the
test/avocado folder in the end, everything is then integrated with
the meson test runner. It should be
From: Thomas Huth
This way we can do a full boot in record-replay mode and
should get a similar test coverage compared to the old
replay test from tests/avocado/replay_linux.py.
Since the aarch64 test was the last avocado test in the
tests/avocado/replay_linux.py file, we can remove this
file no
From: Thomas Huth
Reuse the test function from the 32-bit big endian test to easily
convert the 64-bit big endian Wheezy mips test.
Since this was the last test in tests/avocado/linux_ssh_mips_malta.py,
we can remove this avocado file now, too.
Signed-off-by: Thomas Huth
---
MAINTAINERS
From: Thomas Huth
Since this was the last test in tests/avocado/replay_kernel.py,
we can remove that Avocado file now.
Signed-off-by: Thomas Huth
-#
-# This work is licensed under the terms of the GNU GPL, version 2 or
-# later. See the COPYING file in the top-level directory.
-
-import os
-im
From: Thomas Huth
Reuse the test function from the 32-bit big endian test to easily
convert the 64-bit little endian Wheezy mips test.
Signed-off-by: Thomas Huth
---
tests/avocado/linux_ssh_mips_malta.py | 8
tests/functional/meson.build| 1 +
tests/functional/test_mip
From: Thomas Huth
These tests are using the gdb-related library functions from the
Avocado framework which we don't have in the functional framework
yet. So for the time being, keep those imports and skip the test
if the Avocado framework is not installed on the host.
Signed-off-by: Thomas Huth
Suggestion by Stefan Hajnoczi to improve io_uring performance
Suraj Shirvankar (1):
Add IOURING_SETUP_SINGLE_ISSUER flag to improve iouring performance
util/fdmon-io_uring.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
--
2.45.3
From: Suraj Shirvankar
Signed-off-by: Suraj Shirvankar
---
util/fdmon-io_uring.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/util/fdmon-io_uring.c b/util/fdmon-io_uring.c
index b0d68bdc44..235837abcb 100644
--- a/util/fdmon-io_uring.c
+++ b/util/fdmon-io_uring.c
@
mips_cpu_is_64bit() returns whether the CPU is a
32-bit or a 64-bit one.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu-qom.h | 2 ++
target/mips/cpu.c | 6 ++
2 files changed, 8 insertions(+)
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 9acf647420c..52996
On 25/3/25 23:43, Richard Henderson wrote:
The comment about not being able to define a field with
zero bits is out of date since 94597b6146f3
("decodetree: Allow !function with no input bits").
This fixes the missing load of imm in the disassembler.
Cc: qemu-sta...@nongnu.org
Fixes: 9d8caa67a2
On 25/3/25 23:43, Richard Henderson wrote:
Do not unconditionally attempt to read 4 bytes, as there
may only be 2 bytes remaining in the translator cache.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/avr/disas.c | 21 ++-
On Tue, 25 Mar 2025, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/rtc/ds1338.c | 2 ++
hw/rtc/m41t80.c | 2 ++
hw/rtc/rs5c372.c | 2 ++
3 files changed, 6 insertions(+)
diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c
index 8dd17fdc07c..56162917c1b 100644
--- a/hw/rtc
On Tue, Mar 25, 2025 at 03:43:29PM +, Shameerali Kolothum Thodi wrote:
> > For the record I tested the series with host VFIO device and a
> > virtio-blk-pci device put behind the same pxb-pcie/smmu protection and
> > it works just fine
> >
> > -+-[:0a]-+-01.0-[0b]00.0 Mellanox Technol
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> When nested translation is enabled, there are 2-stage translation
> occuring to two different address spaces: stage-1 in the iommu as,
> while stage-2 in the system as.
>
> If a device attached to the vSMMU doesn't enable stag
On Fri, Jan 24, 2025 at 08:20:48AM -0500, Xiaoyao Li wrote:
> Add docs/system/i386/tdx.rst for TDX support, and add tdx in
> confidential-guest-support.rst
>
> Signed-off-by: Xiaoyao Li
> ---
> ---
> docs/system/confidential-guest-support.rst | 1 +
> docs/system/i386/tdx.rst
On 3/25/25 12:23, Aditya Gupta wrote:
Power11 also uses PHB5, same as Power10.
Add Power11 PHBs with similar code as the corresponding Power10 implementation.
Cc: Cédric Le Goater
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan Srinivasan
Cc: Nicholas Piggin
Signed-off-by: Aditya
On 3/25/25 08:49, Philippe Mathieu-Daudé wrote:
Replace the few ldtul_p() calls by a generic ldn_p() ones.
No logical change.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/gdbstub.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 3/25/25 08:45, Philippe Mathieu-Daudé wrote:
When TARGET_LONG_BITS == 64, ldtul_p() expand to ldq_p().
Directly use the expanded form for clarity.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/gdbstub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richar
Quoting Michael Roth (2025-03-19 07:08:40)
> Hello,
>
> On behalf of the QEMU Team, I'd like to announce the availability of the
> first release candidate for the QEMU 10.0 release. This release is meant
> for testing purposes and should not be used in a production environment.
>
> http://downl
Signed-off-by: Philippe Mathieu-Daudé
---
hw/gpio/pca9552.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/gpio/pca9552.c b/hw/gpio/pca9552.c
index 1ac0cf6c464..b152872f6c6 100644
--- a/hw/gpio/pca9552.c
+++ b/hw/gpio/pca9552.c
@@ -459,6 +459,8 @@ static void pca9552_class_init(ObjectCl
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 7d6954ec26..f23fa3e8ba 100644
--- a/target/
1 - 100 of 219 matches
Mail list logo
