Re: [PATCH v6 09/10] ppc/pnv: Add PHB5 PCIe Host bridge to Power11

[Cédric Le Goater]

On 3/25/25 12:23, Aditya Gupta wrote:

Power11 also uses PHB5, same as Power10.

Add Power11 PHBs with similar code as the corresponding Power10 implementation.

Cc: Cédric Le Goater <c...@kaod.org>
Cc: Frédéric Barrat <fbar...@linux.ibm.com>
Cc: Mahesh J Salgaonkar <mah...@linux.ibm.com>
Cc: Madhavan Srinivasan <ma...@linux.ibm.com>
Cc: Nicholas Piggin <npig...@gmail.com>
Signed-off-by: Aditya Gupta <adit...@linux.ibm.com>

LGTM,

Reviewed-by: Cédric Le Goater <c...@redhat.com>

Thanks,

C.

---
  hw/ppc/pnv.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++-
  1 file changed, 56 insertions(+), 1 deletion(-)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index ae2c1dcd4684..0b741fd4076f 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -973,6 +973,8 @@ static void pnv_chip_power11_pic_print_info(PnvChip *chip, 
GString *buf)

pnv_psi_pic_print_info(&chip11->psi, buf);

      pnv_xive2_pic_print_info(&chip11->xive, buf);
+    object_child_foreach_recursive(OBJECT(chip),
+                         pnv_chip_power9_pic_print_info_child, buf);
  }

/* Always give the first 1GB to chip 0 else we won't boot */

@@ -2373,6 +2375,7 @@ static void pnv_chip_power10_realize(DeviceState *dev, 
Error **errp)

static void pnv_chip_power11_instance_init(Object *obj)

  {
+    PnvChip *chip = PNV_CHIP(obj);
      Pnv11Chip *chip11 = PNV11_CHIP(obj);
      PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
      int i;
@@ -2389,6 +2392,13 @@ static void pnv_chip_power11_instance_init(Object *obj)
      object_initialize_child(obj, "n1-chiplet", &chip11->n1_chiplet,
                              TYPE_PNV_N1_CHIPLET);

+ chip->num_pecs = pcc->num_pecs;

+
+    for (i = 0; i < chip->num_pecs; i++) {
+        object_initialize_child(obj, "pec[*]", &chip11->pecs[i],
+                                TYPE_PNV_PHB5_PEC);
+    }
+
      for (i = 0; i < pcc->i2c_num_engines; i++) {
          object_initialize_child(obj, "i2c[*]", &chip11->i2c[i], TYPE_PNV_I2C);
      }
@@ -2421,6 +2431,38 @@ static void pnv_chip_power11_quad_realize(Pnv11Chip 
*chip11, Error **errp)
      }
  }

+static void pnv_chip_power11_phb_realize(PnvChip *chip, Error **errp)

+{
+    Pnv11Chip *chip11 = PNV11_CHIP(chip);
+    int i;
+
+    for (i = 0; i < chip->num_pecs; i++) {
+        PnvPhb4PecState *pec = &chip11->pecs[i];
+        PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
+        uint32_t pec_cplt_base;
+        uint32_t pec_nest_base;
+        uint32_t pec_pci_base;
+
+        object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
+        object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
+                                &error_fatal);
+        object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
+                                 &error_fatal);
+        if (!qdev_realize(DEVICE(pec), NULL, errp)) {
+            return;
+        }
+
+        pec_cplt_base = pecc->xscom_cplt_base(pec);
+        pec_nest_base = pecc->xscom_nest_base(pec);
+        pec_pci_base = pecc->xscom_pci_base(pec);
+
+        pnv_xscom_add_subregion(chip, pec_cplt_base,
+                 &pec->nest_pervasive.xscom_ctrl_regs_mr);
+        pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
+        pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
+    }
+}
+
  static void pnv_chip_power11_realize(DeviceState *dev, Error **errp)
  {
      PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
@@ -2550,7 +2592,12 @@ static void pnv_chip_power11_realize(DeviceState *dev, 
Error **errp)
      pnv_xscom_add_subregion(chip, PNV11_XSCOM_N1_PB_SCOM_ES_BASE,
                             &chip11->n1_chiplet.xscom_pb_es_mr);

- /* WIP: PHB added in future patch */

+    /* PHBs */
+    pnv_chip_power11_phb_realize(chip, &local_err);
+    if (local_err) {
+        error_propagate(errp, local_err);
+        return;
+    }

/*

       * I2C
@@ -2684,6 +2731,7 @@ static void pnv_chip_power11_class_init(ObjectClass 
*klass, void *data)
      k->xscom_core_base = pnv_chip_power11_xscom_core_base;
      k->xscom_pcba = pnv_chip_power11_xscom_pcba;
      dc->desc = "PowerNV Chip Power11";
+    k->num_pecs = PNV10_CHIP_MAX_PEC;
      k->i2c_num_engines = PNV10_CHIP_MAX_I2C;
      k->i2c_ports_per_engine = i2c_ports_per_engine;

@@ -3274,6 +3322,13 @@ static void pnv_machine_power11_class_init(ObjectClass *oc, void *data)

      XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
      static const char compat[] = "qemu,powernv11\0ibm,powernv";

+ static GlobalProperty phb_compat[] = {

+        { TYPE_PNV_PHB, "version", "5" },
+        { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
+    };
+
+    compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
+
      pmc->compat = compat;
      pmc->compat_size = sizeof(compat);
      pmc->max_smt_threads = 4;