The reg isn't validated to be a possible register before
it's dereferenced for one case. The mmio space registered
for the gpio device is 4KiB but there aren't that many
registers in the struct.
Google-Bug-Id: 397469048
Change-Id: I2fb8d0d3d41422baab22e8fc7e9fadd0f2ee7068
Signed-off-by: Patrick V
On Tue, Feb 25, 2025 at 7:28 AM Conor Dooley wrote:
>
> On Mon, Feb 24, 2025 at 03:14:00PM +1000, Alistair Francis wrote:
> > On Fri, Feb 21, 2025 at 4:31 AM Conor Dooley wrote:
> > >
> > > +cc qemu-riscv, Alistar.
> > >
> > > On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote:
> > >
r_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu
into staging (2025-02-22 05:06:39 +0800)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20250225
for you to fetch changes up to 1aaf3478684ff1cd02d1b36c32a00b
The boston machine doesn't set MachineState::fdt to the DTB blob that
it has loaded or created, which means that the QMP/HMP dumpdtb
monitor commands don't work.
Setting MachineState::fdt is easy in the non-FIT codepath: we can
simply do so immediately before loading the DTB into guest memory.
The
From: "Matthew R. Ochs"
The MMIO region size required to support virtualized environments with
large PCI BAR regions can exceed the hardcoded limit configured in QEMU.
For example, a VM with multiple NVIDIA Grace-Hopper GPUs passed through
requires more MMIO memory than the amount provided by VIR
The vfp_helper.c in the target/arm directory now only has
code for handling FPSCR/FPCR/FPSR in it, and no helper
functions. Rename it to vfp_fpscr.c; this helps keep it
distinct from tcg/vfp_helper.c.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20250221190957.811948-5
On 2/25/25 03:08, Alex Bennée wrote:
We have a function we can call for this, lets not rely on macros that
stop us building once.
Signed-off-by: Alex Bennée
---
plugins/loader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/plugins/loader.c b/plugins/loader.c
index 9968
From: Nicolin Chen
When we fill in the SMMUEventInfo for SMMU_EVT_F_CD_FETCH we write
the address into the f_ste_fetch member of the union, but then when
we come to read it back in smmuv3_record_event() we will (correctly)
be using the f_cd_fetch member.
This is more like a cosmetics fix since t
From: Pierrick Bouvier
Regression introduced by cf76c4
(hw/misc: Add nr_regs and cold_reset_values to NPCM CLK)
cold_reset_values has a different size, depending on device used
(NPCM7xx vs NPCM8xx). However, s->regs has a fixed size, which matches
NPCM8xx. Thus, when initializing a NPCM7xx, we g
In Intel terminology, a floatx80 Infinity with the explicit integer
bit clear is a "pseudo-infinity"; for x86 these are not valid
infinity values. m68k is looser and does not care whether the
Integer bit is set or clear in an infinity.
Move this setting to runtime rather than using an ifdef in
fl
From: Bernhard Beschow
Fixes quite a few stack traces during the Linux boot process. Also provides the
clocks for devices added later, e.g. enet1.
Signed-off-by: Bernhard Beschow
Message-id: 20250223114708.1780-6-shen...@gmail.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
M
From: Bernhard Beschow
The USDHC emulation allows for running real-world images such as those generated
by Buildroot. Convert the board documentation accordingly instead of running a
Linux kernel with ephemeral storage.
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
Message-id: 202
In hmp_dumpdtb(), we print a message when the command succeeds. This
message is missing the trailing \n, so the HMP command prompt is
printed immediately after it. We also weren't capitalizing 'DTB', or
quoting the filename in the message. Fix these nits.
Signed-off-by: Peter Maydell
Reviewed-
From: Bernhard Beschow
The move of the Kconfig bits to hw/gpio is fixing a bug in 6328d8ffa6cb9d
("misc/pca955*: Move models under hw/gpio"), which moved the code but forgot to
move the Kconfig sections.
Fixes: 6328d8ffa6cb9d "misc/pca955*: Move models under hw/gpio"
Signed-off-by: Bernhard Besc
From: Bernhard Beschow
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
Message-id: 20250223114708.1780-10-shen...@gmail.com
[PMM: drop static const from gpio_table for GCC 7.5]
Signed-off-by: Peter Maydell
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h|
From: Joelle van Dyne
In the syndrome value for a data abort, bit 21 is SSE, which is
set to indicate that the abort was on a sign-extending load. When
we handle the data abort from the guest via address_space_read(),
we forgot to handle this and so would return the wrong value if
the guest did a
From: Bernhard Beschow
Split the USB MMIO regions to better keep track of the implemented vs.
unimplemented regions.
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
Message-id: 20250223114708.1780-16-shen...@gmail.com
[PMM: drop "static const" from usb_table for GCC 7.5]
Signed-off-
Currently the helper_vfp_get_fpscr() and helper_vfp_set_fpscr()
functions do the actual work of updating the FPSCR, and we have
wrappers vfp_get_fpscr() and vfp_set_fpscr() which we use for calls
from other QEMU C code.
Flip these around so that it is vfp_get_fpscr() and vfp_set_fpscr()
which do t
From: Joelle van Dyne
macOS 15.2's Hypervisor.framework exposes SME feature on M4 Macs.
However, QEMU's hvf accelerator code does not properly support it
yet, causing QEMU to fail to start when hvf accelerator is used on
these systems, with the error message:
qemu-aarch64-softmmu: cannot disab
Currently we have a compile-time shortcut where we
return false from no_signaling_nans() on everything except
Xtensa, because we know that's the only target that
might ever set status->no_signaling_nans.
Remove the ifdef, so we always look at the status flag;
this has no behavioural change, but wi
The definition of which floatx80 encodings are invalid is
target-specific. Currently we handle this with an ifdef, but we
would like to defer this decision to runtime. In preparation, pass a
float_status argument to floatx80_invalid_encoding().
We will change the implementation from ifdef to loo
Currently we handle the 'dumpdtb' machine sub-option ad-hoc in every
board model that has an FDT. It's up to the board code to make sure
it calls qemu_fdt_dumpdtb() in the right place.
This means we're inconsistent and often just ignore the user's
command line argument:
* if the board doesn't ha
Unlike the other float formats, whether a floatx80 value is
considered to be an Infinity is target-dependent. (On x86 if the
explicit integer bit is clear this is a "pseudo-infinity" and not a
valid infinity; m68k does not care about the value of the integer
bit.)
Currently we select this target-
The function boston_fdt_filter() can return NULL on errors (in which
case it will print an error message). When we call this from the
non-FIT-image codepath, we aren't checking the return value, so we
will plough on with a NULL pointer, and segfault in fdt_totalsize().
Check for errors here.
Sign
The openrisc machines don't set MachineState::fdt to point to their
DTB blob. This means that although the command line '-machine
dumpdtb=file.dtb' option works, the equivalent QMP and HMP monitor
commands do not, but instead produce the error "This machine doesn't
have a FDT".
Set MachineState::
From: Bernhard Beschow
As a first step, implement the bare minimum: CPUs, RAM, interrupt controller,
serial. All other devices of the A53 memory map are represented as
TYPE_UNIMPLEMENTED_DEVICE, i.e. the whole memory map is provided. This allows
for running Linux without it crashing due to invali
From: Bernhard Beschow
On the real device, the PCIe root bus is only connected to a PCIe bridge and
does not allow for direct attachment of devices. Doing so in QEMU results in no
PCI devices being detected by Linux. Instead, PCI devices should plug into the
secondary PCIe bus spawned by the inte
Currently we hardcode at compile time whether the floatx80 default
Infinity value has the explicit integer bit set or not (x86 sets it;
m68k does not). To be able to compile softfloat once for all targets
we'd like to move this setting to runtime.
Define a new FloatX80Behaviour enum which is a se
The global const floatx80_infinity is (unlike all the other
float*_infinity values) target-specific, because whether the explicit
Integer bit is set or not varies between m68k and i386. We want to
be able to compile softfloat once for multiple targets, so we can't
continue to use a single global w
From: Bernhard Beschow
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
Message-id: 20250223114708.1780-14-shen...@gmail.com
[PMM: drop static const from gpt_attrs for GCC 7.5]
Signed-off-by: Peter Maydell
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h| 1
From: Bernhard Beschow
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
Message-id: 20250223114708.1780-13-shen...@gmail.com
[PMM: drop static const from wdog_table for GCC 7.5]
Signed-off-by: Peter Maydell
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h|
Most of the target/arm/vfp_helper.c file is purely TCG helper code,
guarded by #ifdef CONFIG_TCG. Move this into a new file in
target/arm/tcg/.
This leaves only the code relating to getting and setting the
FPCR/FPSR/FPSCR in the original file. (Some of this also is
TCG-only, but that needs more c
On 2/25/25 03:08, Alex Bennée wrote:
hwaddr is a fixed size on all builds.
Signed-off-by: Alex Bennée
---
include/qemu/plugin-memory.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/qemu/plugin-memory.h b/include/qemu/plugin-memory.h
index 71c1123308..6065ec7aaf 100644
--- a/incl
From: Bernhard Beschow
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
Message-id: 20250223114708.1780-18-shen...@gmail.com
Signed-off-by: Peter Maydell
---
include/hw/arm/fsl-imx8mp.h | 1 +
hw/arm/fsl-imx8mp.c | 11 +++
2 files changed, 12 insertions(+)
diff --g
From: Bernhard Beschow
While at it add missing GUSB2RHBCTL register as found in i.MX 8M Plus reference
manual.
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
Message-id: 20250223114708.1780-2-shen...@gmail.com
Signed-off-by: Peter Maydell
---
include/hw/usb/hcd-dwc3.h | 2 +-
hw/
From: Bernhard Beschow
SNVS contains an RTC which allows Linux to deal correctly with time. This is
particularly useful when handling persistent storage which will be done in the
next patch.
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
Message-id: 20250223114708.1780-7-shen...@gm
Currently we compile-time set an 'm68k_denormal' flag in the FloatFmt
for floatx80 for m68k. This controls our handling of what the Intel
documentation calls a "pseudo-denormal": a value where the exponent
field is zero and the explicit integer bit is set.
For x86, the x87 FPU is supposed to acce
From: Bernhard Beschow
Linux checks for the PLLs in the PHY to be locked, so implement a model
emulating that.
Signed-off-by: Bernhard Beschow
Message-id: 20250223114708.1780-9-shen...@gmail.com
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
MAINTAINERS |
Because floatx80 has an explicit integer bit, this permits some
odd encodings where the integer bit is not set correctly for the
floating point value type. In In Intel terminology the
categories are:
exp == 0, int = 0, mantissa == 0 : zeroes
exp == 0, int = 0, mantissa != 0 : denormals
exp =
The global const floatx80_infinity is (unlike all the other
float*_infinity values) target-specific, because whether the explicit
Integer bit is set or not varies between m68k and i386. We want to
be able to compile softfloat once for multiple targets, so we can't
continue to use a single global w
From: Bernhard Beschow
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
Message-id: 20250223114708.1780-12-shen...@gmail.com
[PMM: drop static const from spi_table for GCC 7.5]
Signed-off-by: Peter Maydell
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h|
Now we have removed all the target-specifics from the softfloat code,
we can switch to building it once for the whole system rather than
once per target.
Signed-off-by: Peter Maydell
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20250224111524.1101196-13-peter.may
From: Bernhard Beschow
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
Message-id: 20250223114708.1780-11-shen...@gmail.com
[PMM: drop static const from i2c_table for GCC 7.5]
Signed-off-by: Peter Maydell
---
docs/system/arm/imx8mp-evk.rst | 1 +
include/hw/arm/fsl-imx8mp.h| 1
We happen to know that for the PPC target the FP status flags (and in
particular float_flag_inexact) will always be cleared before a
floating point operation, and so can_use_fpu() will always return
false. So we speed things up a little by forcing QEMU_NO_HARDFLOAT
to true on that target.
We woul
On 2/25/25 03:08, Alex Bennée wrote:
Thanks to re-factoring and clean-up work (especially to exec-all) we
no longer need such broad headers for the api.
Signed-off-by: Alex Bennée
---
plugins/api.c | 3 ---
1 file changed, 3 deletions(-)
Reviewed-by: Richard Henderson
r~
The softfloat (i.e. TCG) specific handling for the FPCR
and FPSR is abstracted behind five functions:
arm_set_default_fp_behaviours
arm_set_ah_fp_behaviours
vfp_get_fpsr_from_host
vfp_clear_float_status_exc_flags
vfp_set_fpsr_to_host
Currently we rely on the first two calling softfloat functi
On 2/25/25 03:08, Alex Bennée wrote:
Headers should bring in what they need so don't rely on getting
queue.h by side effects. This will help with clean-ups in the
following patches.
Signed-off-by: Alex Bennée
---
plugins/plugin.h | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Richard He
Currently if the user requests via -machine dumpdtb=file.dtb that we
dump the DTB, but the machine doesn't have a DTB, we silently ignore
the option. This is confusing to users, and is a legacy of the old
board-specific implementation of the option, where if the execution
codepath didn't go via a
On 2/25/25 03:08, Alex Bennée wrote:
To move the main api.c to a single build compilation object we need to
start splitting out user and system specific code. As we need to grob
around host headers we move these particular helpers into the *-user
mode directories.
The binary/start/end/entry help
From: Bernhard Beschow
The i.MX 8M Plus SoC actually has two ethernet controllers, the usual ENET one
and a Designware one. There is no device model for the latter, so only add the
ENET one.
Reviewed-by: Peter Maydell
Signed-off-by: Bernhard Beschow
Message-id: 20250223114708.1780-15-shen...@g
On 17/2/25 00:07, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 4 +++
tcg/aarch64/tcg-target.c.inc | 31 ++
tcg/arm/tcg-target.c.inc | 41 +---
tcg/i386/tcg-target.c.inc| 27
On 2/25/25 03:08, Alex Bennée wrote:
These only work for system-mode and are NOPs for user-mode.
Signed-off-by: Alex Bennée
---
plugins/api-system.c | 58
plugins/api-user.c | 40 +
plugins/api.c| 70 -
On 2/25/25 03:08, Alex Bennée wrote:
These are only usable in system mode where we control the timer. For
user-mode make them NOPs.
Signed-off-by: Alex Bennée
---
plugins/api-system.c | 34 ++
plugins/api-user.c | 17 +
plugins/api.c
On 25/02/2025 18.57, Daniel P. Berrangé wrote:
On Tue, Feb 25, 2025 at 06:52:43PM +0100, Thomas Huth wrote:
On 25/02/2025 18.44, Thomas Huth wrote:
On 25/02/2025 11.12, Kevin Wolf wrote:
Am 25.02.2025 um 08:20 hat Thomas Huth geschrieben:
Hi!
I'm facing a weird hang in iotest 233 on my F
On 2/25/25 05:41, Peter Maydell wrote:
On Mon, 24 Feb 2025 at 20:51, Pierrick Bouvier
wrote:
Regression introduced by cf76c4
(hw/misc: Add nr_regs and cold_reset_values to NPCM CLK)
cold_reset_values has a different size, depending on device used
(NPCM7xx vs NPCM8xx). However, s->regs has a f
On 25/02/2025 21.35, Thomas Huth wrote:
On 25/02/2025 18.57, Daniel P. Berrangé wrote:
On Tue, Feb 25, 2025 at 06:52:43PM +0100, Thomas Huth wrote:
On 25/02/2025 18.44, Thomas Huth wrote:
On 25/02/2025 11.12, Kevin Wolf wrote:
Am 25.02.2025 um 08:20 hat Thomas Huth geschrieben:
Hi!
I'm
From: Jamin Lin
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin
Reviewed-by: Andrew Jeffery
---
include/hw/misc/aspeed_hace.h | 1 +
hw/misc/aspeed_hace.c | 20
2 files changed, 21 insertions(+)
diff --git a/include/hw/misc/aspeed_hace
This patch adds support for the AARCH64 ILP32 ABI [1] to the QEMU
linux-user AARCH64 port.
The ILP32 ABI was initially developed quite some time ago [2] to
facilitate porting legacy code to the new AARCH64 architecture. However,
it appears that most legacy code is still used as ARMv7 (ARM 32-bit)
From: Jamin Lin
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_hace.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c
index e3f7df2e86..18b8508
From: Jamin Lin
Currently, it does not support the CRYPT command. Instead, it only sends an
interrupt to notify the firmware that the crypt command has completed.
It is a temporary workaround to resolve the boot issue in the Crypto Manager
Self Test.
Introduce a new "use_crypt_workaround" class
From: Jamin Lin
The HACE controller between AST2600 and AST2700 are almost identical.
The HACE controller registers base address starts at 0x1207_ and
its alarm interrupt is connected to GICINT4.
Signed-off-by: Jamin Lin
Reviewed-by: Andrew Jeffery
---
hw/arm/aspeed_ast27x0.c | 15 +++
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2625
This change intends to support an ARM64 server like platform that has TPM
support to unlock more power for sbsa_ref.
The idea is to add a TPM create routine during sbsa machine initialization.
The backend can be the same as the rest of
On Sun, 23 Feb 2025 at 11:47, Bernhard Beschow wrote:
>
> As a first step, implement the bare minimum: CPUs, RAM, interrupt controller,
> serial. All other devices of the A53 memory map are represented as
> TYPE_UNIMPLEMENTED_DEVICE, i.e. the whole memory map is provided. This allows
> for running
From: Jamin Lin
This patch series is from
https://patchwork.kernel.org/project/qemu-devel/cover/20250213033531.3367697-1-jamin_...@aspeedtech.com/.
To expedite the review process, I have separated the HACE patches portion from
the
https://patchwork.kernel.org/project/qemu-devel/cover/20250213
On Sun, 23 Feb 2025 at 11:47, Bernhard Beschow wrote:
>
> Fixes quite a few stack traces during the Linux boot process. Also provides
> the
> clocks for devices added later, e.g. enet1.
>
> Signed-off-by: Bernhard Beschow
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, Feb 24, 2025 at 04:05:49PM -0700, Simon Glass wrote:
> U-Boot can start and boot an OS in both qemu-x86 and qemu-x86_64 but it
> is not perfect.
>
> With both builds, executing the VESA ROM causes an intermittent hang, at
> least on some AMD CPUs.
>
> With qemu-x86_64 kvm cannot be used
On Sun, 23 Feb 2025 at 11:47, Bernhard Beschow wrote:
>
> Linux checks for the PLLs in the PHY to be locked, so implement a model
> emulating that.
>
> Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
thanks
-- PMM
On Tue, 25 Feb 2025 12:00:12 +0100
Gerd Hoffman wrote:
> Hi,
>
> > > See
> > > https://lore.kernel.org/qemu-devel/20250219071431.50626-2-kra...@redhat.com/
> > >
> >
> > After looking at it, it seems to me that data will be in host byte order
> > and guest has no idea what that is.
> > Pr
On Tue, Feb 25, 2025 at 11:05:25AM +, Daniel P. Berrangé wrote:
> When gitlab initializes the repo checkout for a CI job, it will have
> done a shallow clone with only partial history. Periodically the objects
> that are omitted cause trouble with the check-patch/check-dco jobs. This
> is exhib
On Tue, 25 Feb 2025 at 12:44, Marek Szyprowski wrote:
>
> This patch adds support for the AARCH64 ILP32 ABI [1] to the QEMU
> linux-user AARCH64 port.
>
> The ILP32 ABI was initially developed quite some time ago [2] to
> facilitate porting legacy code to the new AARCH64 architecture. However,
> i
Prasad Pandit writes:
> Hello Fabiano,
>
> On Tue, 18 Feb 2025 at 19:58, Fabiano Rosas wrote:
>> >> > +static void test_multifd_postcopy_tcp_cancel(void)
>> >> > +{
>> >> > +postcopy_ram = true;
>> >> > +test_multifd_tcp_cancel();
>> >> > +postcopy_ram = false;
>> >>
>> >> You could
On Tue, 25 Feb 2025 18:19:03 +0100
Igor Mammedov wrote:
> On Tue, 25 Feb 2025 12:42:24 +
> Alex Bennée wrote:
>
> > Igor Mammedov writes:
> >
> > > 1)
> > > This reverts commit 30933c4fb4f3df95ae44c4c3c86a5df049852c01.
> > > ("tcg/cputlb: remove other-cpu capability from TLB flushing"
Add UEFI_VARS config option, enable by default for x86_64 and aarch64.
Signed-off-by: Gerd Hoffmann
---
hw/Kconfig | 1 +
hw/uefi/Kconfig | 3 +++
2 files changed, 4 insertions(+)
create mode 100644 hw/uefi/Kconfig
diff --git a/hw/Kconfig b/hw/Kconfig
index 1b4e9bb07f7d..c4dfe2e7af7c 1006
Implement variable policies (Edk2VariablePolicyProtocol).
This EFI protocol allows to define restrictions for variables.
It also allows to lock down variables (disallow write access).
Signed-off-by: Gerd Hoffmann
---
hw/uefi/var-service-policy.c | 370 +++
1 file
Add and register function to create an device tree entry when
the device is added to the qemu platform bus.
Signed-off-by: Gerd Hoffmann
---
hw/core/sysbus-fdt.c | 24
hw/uefi/var-service-sysbus.c | 1 +
2 files changed, 25 insertions(+)
diff --git a/hw/core/sy
This implements authenticated variable handling (see AuthVariableLib in
edk2).
The by far most common use case for auth variables is secure boot. The
secure boot certificate databases ('PK', 'KEK', 'db' and 'dbx') are
authenticated variables, with update rules being specified in the UEFI
specific
On 2/25/2025 11:36 AM, David Hildenbrand wrote:
+ * Return true if ram is compatible with CPR. Do not exclude rom,
+ * because the rom file could change in new QEMU.
+ */
+static bool ram_is_cpr_compatible(RAMBlock *rb)
+{
+ MemoryRegion *mr = rb->mr;
+
+ if (!mr || !memory_region_is_ram(m
Hi Alex,
On 2/25/25 03:08, Alex Bennée wrote:
As we move towards a more modular build this series converts both
loader and api to build once objects. For both objects the only real
difference is between user mode and system emulation so those bits
have been hived off into those source sets.
The
On 2/25/25 10:17, Philippe Mathieu-Daudé wrote:
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index a0f050ff9c..08106b6e4c 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
+static const TCGOutOpBinary outop_add = {
+ .b
On 2/25/25 10:40, Philippe Mathieu-Daudé wrote:
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 1115d1e38d..01010dfdc0 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
+static void tgen_andi(TCGContext *s, TCGType type,
+ TCG
On 2/25/25 10:46, Alex Bennée wrote:
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 062a6e85fb..f987b75c4f 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7242,9 +7242,6 @@ static void ppc_cpu_reset_hold(Object *obj, ResetType
type)
if (tcg_enabled()) {
Am 25. Februar 2025 14:29:15 UTC schrieb Peter Maydell
:
>On Sun, 23 Feb 2025 at 11:47, Bernhard Beschow wrote:
>>
>> On a real device, the boot ROM contains the very first instructions the CPU
>> executes. Also, U-Boot calls into the ROM to determine the boot device. While
>> we're not actual
Am 25. Februar 2025 14:43:32 UTC schrieb Peter Maydell
:
>On Sun, 23 Feb 2025 at 11:47, Bernhard Beschow wrote:
>>
>> This series adds a new aarch64 machine to QEMU: i.MX 8M Plus EVK [1]. It
>> allows
>> for running Linux distributions such as Buildroot
>> (freescale_imx8mpevk_defconfig) and
On 2/25/25 10:46, Alex Bennée wrote:
@@ -191,7 +199,7 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error
**errp)
cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
hppa_cpu_alarm_timer, cpu);
-hppa_ptlbe(&cpu->env);
+
A bunch of #defines and structs copied over from edk2,
mostly needed to decode and encode the messages in the
communication buffer.
Signed-off-by: Gerd Hoffmann
---
include/hw/uefi/var-service-edk2.h | 227 +
1 file changed, 227 insertions(+)
create mode 100644 inclu
Signed-off-by: Gerd Hoffmann
---
docs/devel/index-internals.rst | 1 +
docs/devel/uefi-vars.rst | 68 ++
hw/uefi/LIMITATIONS.md | 7
3 files changed, 76 insertions(+)
create mode 100644 docs/devel/uefi-vars.rst
create mode 100644 hw/uefi/LIMI
edk2 looks for the etc/hardware-info fw_cfg file to discover hardware
which can not easily be found in other ways. Entries consist of a
header with hardware type and entry size (HARDWARE_INFO_HEADER),
followed by the actual hardware description (which is type specific).
The file can have multiple
On Tue, 25 Feb 2025 at 15:42, Peter Maydell wrote:
> The C compiler for the OpenSUSE CI job doesn't seem to like this:
> https://gitlab.com/pm215/qemu/-/jobs/9239416833
>
> ../hw/arm/fsl-imx8mp.c: In function ‘fsl_imx8mp_realize’:
> ../hw/arm/fsl-imx8mp.c:382:15: error: initializer element is not
On Tue, Feb 25, 2025 at 06:52:43PM +0100, Thomas Huth wrote:
> On 25/02/2025 18.44, Thomas Huth wrote:
> > On 25/02/2025 11.12, Kevin Wolf wrote:
> > > Am 25.02.2025 um 08:20 hat Thomas Huth geschrieben:
> > > >
> > > > Hi!
> > > >
> > > > I'm facing a weird hang in iotest 233 on my Fedora 41 l
Signed-off-by: Gerd Hoffmann
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1911949526ce..451fc33306dc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2807,6 +2807,12 @@ F: hw/misc/ivshmem-flat.c
F: include/hw/misc/ivshmem-flat.h
F: docs
Add state structs and function declarations for the uefi-vars device.
Signed-off-by: Gerd Hoffmann
---
include/hw/uefi/var-service.h | 191 ++
1 file changed, 191 insertions(+)
create mode 100644 include/hw/uefi/var-service.h
diff --git a/include/hw/uefi/var-ser
pkcs7 stub which is used in case gnutls is not available.
It throws EFI_WRITE_PROTECTED errors unconditionally, so all
authenticated variables are readonly for the guest.
Signed-off-by: Gerd Hoffmann
---
hw/uefi/var-service-pkcs7-stub.c | 16
1 file changed, 16 insertions(+)
c
+ * Return true if ram is compatible with CPR. Do not exclude rom,
+ * because the rom file could change in new QEMU.
+ */
+static bool ram_is_cpr_compatible(RAMBlock *rb)
+{
+MemoryRegion *mr = rb->mr;
+
+if (!mr || !memory_region_is_ram(mr)) {
+return true;
+}
+
+/* Ram
This adds sysbus bindings for the variable service.
Signed-off-by: Gerd Hoffmann
---
hw/uefi/var-service-sysbus.c | 91
hw/uefi/meson.build | 3 +-
2 files changed, 93 insertions(+), 1 deletion(-)
create mode 100644 hw/uefi/var-service-sysbus.c
di
Define qapi schema for the uefi variable store state.
Use it and the generated visitor helper functions to store persistent
(EFI_VARIABLE_NON_VOLATILE) variables in JSON format on disk.
Signed-off-by: Gerd Hoffmann
---
hw/uefi/var-service-json.c | 243 +
qapi
Add trace events for debugging and trouble shooting.
Signed-off-by: Gerd Hoffmann
---
hw/uefi/trace-events | 17 +
1 file changed, 17 insertions(+)
create mode 100644 hw/uefi/trace-events
diff --git a/hw/uefi/trace-events b/hw/uefi/trace-events
new file mode 100644
index 00
The x86 variant of the device is mapped on the fixed address 0xfef1
and uses etc/hardware-info instead of FDT to pass the mapping location
to the edk2 firmware. The latter allows to move the device to a
different location should that turn out to be necessary in the future.
Signed-off-by: Gerd
Hi Alistair,
On 2025-02-24 14:10:19+1000, Alistair Francis wrote:
> On Mon, Feb 3, 2025 at 8:58 AM Thomas Weißschuh wrote:
> >
> > Linux on riscv does not support SA_RESTORER.
> > Currently QEMU thinks there is a field 'sa_restorer' in the middle of
> > 'struct sigaction' which does not actually
Currently we have a compile-time shortcut where we return a hardcode
value from snan_bit_is_one() on everything except MIPS, because we
know that's the only target that needs to change
status->no_signaling_nans at runtime.
Remove the ifdef, so we always look at the status flag. This means
we must
On 17/2/25 00:07, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target-con-set.h | 1 +
tcg/tcg.c| 40 ++-
tcg/aarch64/tcg-target.c.inc | 51 +++---
tcg/arm/tcg-target.c.inc | 43
tcg/i386
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