Re: [PATCH v3 006/162] tcg: Convert and to TCGOutOpBinary

[Philippe Mathieu-Daudé]

On 17/2/25 00:07, Richard Henderson wrote:

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
  tcg/tcg.c                        |  4 +++
  tcg/aarch64/tcg-target.c.inc     | 31 ++++++++++--------
  tcg/arm/tcg-target.c.inc         | 41 +++++++++++++++++-------
  tcg/i386/tcg-target.c.inc        | 27 ++++++++++++----
  tcg/loongarch64/tcg-target.c.inc | 29 ++++++++++-------
  tcg/mips/tcg-target.c.inc        | 55 +++++++++++++++++++-------------
  tcg/ppc/tcg-target.c.inc         | 40 ++++++++++++-----------
  tcg/riscv/tcg-target.c.inc       | 29 ++++++++++-------
  tcg/s390x/tcg-target.c.inc       | 48 +++++++++++++++-------------
  tcg/sparc64/tcg-target.c.inc     | 23 ++++++++++---
  tcg/tci/tcg-target.c.inc         | 14 ++++++--
  11 files changed, 216 insertions(+), 125 deletions(-)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 1115d1e38d..01010dfdc0 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc

+static void tgen_andi(TCGContext *s, TCGType type,
+                      TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+    int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
+    tgen_arithi(s, ARITH_AND + rexw, a0, a2, 0);

We could s/0/false/ in preparation of tgen_arithi() taking a boolean
for the CF bit.

+}
+
+static const TCGOutOpBinary outop_and = {
+    .base.static_constraint = C_O1_I2(r, 0, reZ),
+    .out_rrr = tgen_and,
+    .out_rri = tgen_andi,
+};

diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index f5441d2033..d60bdaba25 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -2196,6 +2196,31 @@ static const TCGOutOpBinary outop_add = {
      .out_rri = tgen_addi,
  };

+static void tgen_and(TCGContext *s, TCGType type,

+                     TCGReg a0, TCGReg a1, TCGReg a2)
+{
+    if (type != TCG_TYPE_I32) {
+        tcg_out_insn(s, RRFa, NGRK, a0, a1, a2);
+    } else if (a0 == a1) {
+        tcg_out_insn(s, RR, NR, a0, a2);
+    } else {
+        tcg_out_insn(s, RRFa, NRK, a0, a1, a2);
+    }
+}
+
+static void tgen_andi_3(TCGContext *s, TCGType type,
+                        TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+    tcg_out_mov(s, type, a0, a1);
+    tgen_andi(s, type, a0, a2);
+}
+
+static const TCGOutOpBinary outop_and = {
+    .base.static_constraint = C_O1_I2(r, r, rNKR),

So INDEX_op_and_i32 gets more constraints (ri -> rNKR):

CONST('K', TCG_CT_CONST_P32)
CONST('N', TCG_CT_CONST_INV)
CONST('R', TCG_CT_CONST_INVRISBG)

IIUC this doesn't affect anything, as these constraints are only
useful for 64-bit ops, right?

+    .out_rrr = tgen_and,
+    .out_rri = tgen_andi_3,
+};

diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
index f43d95b025..b3fbe127c0 100644
--- a/tcg/sparc64/tcg-target.c.inc
+++ b/tcg/sparc64/tcg-target.c.inc

+static const TCGOutOpBinary outop_and = {
+    .base.static_constraint = C_O1_I2(r, r, rJ),

Again, missing 'z', so C_O1_I2(r, rz, rJ)?

+    .out_rrr = tgen_and,
+    .out_rri = tgen_andi,
+};