Re: [PATCH] hw/i386: introduce x86_firmware_reconfigure api

On Mon, Feb 24, 2025 at 9:01 PM Gerd Hoffmann wrote: > > Hi, > > > /* should only be called once */ > > -if (ovmf_flash_parsed) { > > +if (ovmf_flash_parsed && !force) { > > I think it makes more sense to clear ovmf_flash_parsed when replacing > the firmware (instead of adding the f

Re: [PATCH v6] hw/misc/vmfwupdate: Introduce hypervisor fw-cfg interface support

On Mon, Feb 24, 2025 at 9:17 PM Gerd Hoffman wrote: > > On Fri, Feb 14, 2025 at 09:04:07PM +0530, Ani Sinha wrote: > > VM firmware update is a mechanism where the virtual machines can use their > > preferred and trusted firmware image in their execution environment without > > having to depend on

Re: [PATCH 1/5] hw/pci: Basic support for PCI power management

On Mon, 24 Feb 2025 20:03:56 +0100 Eric Auger wrote: > Hi Alex, > > On 2/20/25 11:48 PM, Alex Williamson wrote: > > The memory and IO BARs for devices are only accessible in the D0 > > power state. In other power states the PCI spec defines that the > > device should respond to TLPs and message

Re: [RFC 0/2] python: integrate linter tests natively with meson

John, how does this mix with the linting parts of your "[PATCH 00/10] qapi: misc testing and doc patches"?

Problem with iotest 233

Hi! I'm facing a weird hang in iotest 233 on my Fedora 41 laptop. When running ./check -raw 233 the test simply hangs. Looking at the log, the last message is "== check plain client to TLS server fails ==". I added some debug messages, and it seems like the previous NBD server is not corr

Re: [PATCH v6 4/4] tests/qtest/migration: add postcopy tests with multifd

Hello Fabiano, On Tue, 18 Feb 2025 at 19:58, Fabiano Rosas wrote: > >> > +static void test_multifd_postcopy_tcp_cancel(void) > >> > +{ > >> > +postcopy_ram = true; > >> > +test_multifd_tcp_cancel(); > >> > +postcopy_ram = false; > >> > >> You could pass this in, there's just one other

[PATCH] iotests: Stop NBD server in test 162 before starting the next one

Test 162 recently started failing for me for no obvious reasons (I did not spot any suspicious commits in this area), but looking in the 162.out.bad log file, there was a suspicious message at the end: qemu-nbd: Cannot lock pid file: Resource temporarily unavailable And indeed, the test starts t

Re: [PATCH 07/15] rust: qemu_api_macros: add Wrapper derive macro

> +fn derive_opaque_or_error(input: DeriveInput) -> > Result { > +is_transparent_repr(&input, "#[derive(Wrapper)]")?; > + > +let name = &input.ident; > +let field = &get_unnamed_field(&input, "#[derive(Wrapper)]")?; > +let typ = &field.ty; > + > +// TODO: how to add "::qemu_api

Re: [PATCH 08/15] rust: timer: wrap QEMUTimer with Opaque<>

On Fri, Feb 21, 2025 at 06:03:35PM +0100, Paolo Bonzini wrote: > Date: Fri, 21 Feb 2025 18:03:35 +0100 > From: Paolo Bonzini > Subject: [PATCH 08/15] rust: timer: wrap QEMUTimer with Opaque<> > X-Mailer: git-send-email 2.48.1 > > Signed-off-by: Paolo Bonzini > --- > meson.build|

RE: [PATCH v4 0/4] Support HACE to AST2700

Hi All, > From: cy_liu > Sent: Tuesday, February 25, 2025 3:34 PM > To: cyliu0926 ; Cédric Le Goater ; > Peter Maydell ; Steven Lee > ; Troy Lee ; Jamin Lin > ; Andrew Jeffery > ; Joel Stanley ; open > list:ASPEED BMCs ; open list:All patches CC here > > Subject: [PATCH v4 0/4] Support HACE to A

[PATCH v4 2/4] hw/misc/aspeed_hace: Add AST2700 support

Introduce a new ast2700 class to support AST2700. Signed-off-by: Jamin Lin Reviewed-by: Andrew Jeffery --- include/hw/misc/aspeed_hace.h | 1 + hw/misc/aspeed_hace.c | 20 2 files changed, 21 insertions(+) diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/mi

[PATCH v4 1/4] hw/misc/aspeed_hace: Fix coding style

Fix coding style issues from checkpatch.pl. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater --- hw/misc/aspeed_hace.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index e3f7df2e86..18b85081c7 100644 --- a/h

[PATCH v4 0/4] Support HACE to AST2700 (resend)

This patch series is from https://patchwork.kernel.org/project/qemu-devel/cover/20250213033531.3367697-1-jamin_...@aspeedtech.com/. To expedite the review process, I have separated the HACE patches portion from the https://patchwork.kernel.org/project/qemu-devel/cover/20250213033531.3367697-1-j

[PATCH v4 3/4] hw/arm/aspeed_ast27x0: Add HACE support for AST2700

The HACE controller between AST2600 and AST2700 are almost identical. The HACE controller registers base address starts at 0x1207_ and its alarm interrupt is connected to GICINT4. Signed-off-by: Jamin Lin Reviewed-by: Andrew Jeffery --- hw/arm/aspeed_ast27x0.c | 15 +++ 1 file c

[PATCH v4 4/4] hw/misc/aspeed_hace: Fix boot issue in the Crypto Manager Self Test

Currently, it does not support the CRYPT command. Instead, it only sends an interrupt to notify the firmware that the crypt command has completed. It is a temporary workaround to resolve the boot issue in the Crypto Manager Self Test. Introduce a new "use_crypt_workaround" class attribute and set

Re: [PATCH v2 7/8] migration/rdma: Remove redundant migration_in_postcopy checks

On 25/02/2025 04:00, Peter Xu wrote: > On Fri, Feb 21, 2025 at 02:36:11PM +0800, Li Zhijian wrote: >> Since we have disabled RDMA + postcopy, it's safe to remove >> the migration_in_postcopy() that follows the migration_rdma(). >> >> Signed-off-by: Li Zhijian >> --- >> migration/ram.c | 2 +-

Re: [PATCH v2 5/8] migration: Add migration_capabilities_and_transport_compatible() helper

On 25/02/2025 03:58, Peter Xu wrote: > On Fri, Feb 21, 2025 at 02:36:09PM +0800, Li Zhijian wrote: >> Similar to migration_channels_and_transport_compatible(), introduce a >> new helper migration_capabilities_and_transport_compatible() to check if >> the capabilites is compatible with the transpo

[PATCH 0/2] hw/ufs: Add temperature event support and test cases

This patch series introduces temperature event notification support in the UFS emulation and adds corresponding test cases to validate the feature. The first patch enables the UFS emulation to generate temperature-related events, including high and low temperature notifications, following the UFS

Re: [PATCH 06/15] rust: cell: add wrapper for FFI types

> +/// Creates a new opaque object with zeroed contents. > +/// > +/// # Safety > +/// > +/// Ultimately the pointer to the returned value will be dereferenced > +/// in another unsafe block, for example when passing it to a C function. > +/// However, this function is u

[PATCH 1/2] hw/ufs: Add temperature event notification support

This patch introduces temperature event notification support to the UFS emulation. It enables the emulated UFS device to generate temperature-related events, including high and low temperature notifications, in compliance with the UFS specification. With this feature, UFS drivers can now handle te

[PATCH 2/2] tests/qtest/ufs-test: Add test code for the temperature feature

This commit adds tests to verify the correctness of query attribute results related to the temperature feature. It ensures that querying temperature attributes returns expected values. Signed-off-by: Keoseong Park --- tests/qtest/ufs-test.c | 24 1 file changed, 24 inser

Re: Seeking help on implementing sync over ivshmem shared memory

Thanks for your support . It will be a great help for us . On Mon, 24 Feb 2025 at 3:03 PM, Philippe Mathieu-Daudé wrote: > Cc'ing Gustavo who maintains the IVSHMEM device. > > On 23/2/25 15:48, Jayakrishnan A wrote: > > Hi Team , > > > > Seeking help on implementing sync over ivshmem shared memo

[PATCH v2 09/11] hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap

From: Tomasz Jeznach Now that we have every piece in place we can advertise CAP_HTM to software, allowing any HPM aware driver to make use of the counters. HPM is enabled/disabled via the 'hpm-counters' attribute. Default value is 31, max value is also 31. Setting it to zero will disable HPM sup

[PATCH v2 01/11] hw/riscv/riscv-iommu.h: add missing headers

This header is incomplete, i.e. it is using definitions that are being supplied by the .c files that are including it. Adding this header into a fresh .c file will result in errors: /home/danielhb/work/qemu/hw/riscv/riscv-iommu.h:30:17: error: field ‘parent_obj’ has incomplete type 30 | D

[PATCH v2 10/11] hw/riscv: add IOMMU HPM trace events

Add a handful of trace events to allow for an easier time debugging the HPM feature. Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- hw/riscv/riscv-iommu-hpm.c | 10 ++ hw/riscv/trace-events | 5 + 2 files changed, 15 insertions(+) diff --git a/hw/riscv/

[PATCH v2 02/11] hw/riscv/riscv-iommu-bits.h: HPM bits

From: Tomasz Jeznach Add the relevant HPM (High Performance Monitor) bits that we'll be using in the next patches. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- hw/riscv/riscv-iommu-bits.h | 47 + 1 fil

[PATCH v2 08/11] hw/riscv/riscv-iommu: add hpm events mmio write

From: Tomasz Jeznach To support hpm events mmio writes, done via riscv_iommu_process_hpmevt_write(), we're also adding the 'hpm-counters' IOMMU property that are used to determine the amount of counters available in the IOMMU. Note that everything we did so far didn't change any IOMMU behavior b

[PATCH v2 04/11] hw/riscv/riscv-iommu: add riscv_iommu_hpm_incr_ctr()

From: Tomasz Jeznach This function will increment a specific counter, generating an interrupt when an overflow occurs. Some extra changes in riscv-iommu.c were required to add this new helper in riscv-iommu-hpm.c: - RISCVIOMMUContext was moved to riscv-iommu.h, making it visible in riscv-iom

[PATCH v2 00/11] riscv: IOMMU HPM support

Hi, In this version no major changes were made. Just a rebase with alistair/riscv-to-apply.next and acks from Alistair. All patches acked. v1 link: https://lore.kernel.org/qemu-riscv/20241205133003.184581-1-dbarb...@ventanamicro.com/ Daniel Henrique Barboza (3): hw/riscv/riscv-iommu.h: add m

[PATCH v2 03/11] hw/riscv/riscv-iommu: add riscv-iommu-hpm file

From: Tomasz Jeznach The HPM (Hardware Performance Monitor) support consists of almost 7 hundred lines that would be put on top of the base riscv-iommu emulation. To avoid clogging riscv-iommu.c, add a separated riscv-iommu-hpm file that will contain HPM specific code. We'll start by adding ris

[PATCH v2 05/11] hw/riscv/riscv-iommu: instantiate hpm_timer

From: Tomasz Jeznach The next HPM related changes requires the HPM overflow timer to be initialized by the riscv-iommu base emulation. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- hw/riscv/riscv-iommu-hpm.c | 36 +

[RFC 2/2] python: integrate linter tests natively with meson

This creates meson test targets for the python linters which has a number of benefits: * They can be invoked in the same manner as all other tests using meson or ninja, or the top level Makefile wrappers * They avoid the extra indirection of running via avocado * They get run by default when

[RFC 0/2] python: integrate linter tests natively with meson

It seems everytime I post some new patches which touch python code I end up forgetting to run the extra non-default 'make check' target from the python/ subdir. IMHO, if we're going to pick up on linter failures in review feedback (which is a reasonable thing to want to do), then we should be runn

[RFC 1/2] python: be more selective in hiding mypy subclassing warning

Use an annotation inline to the file instead of in setup.cfg This has the added advantage that the mypy checks now pass when using 'mypy /path/to/python/qemu' as well as 'mypy -p qemu'. Signed-off-by: Daniel P. Berrangé --- python/qemu/qmp/qmp_tui.py| 12 ++-- python/qemu/utils/qom_

[PATCH 03/10] vfio/igd: Remove rombar check for legacy mode

Legacy VBIOS support was removed in Gen 11 and later IGD devices. While we usually uses romfile for IGD-related DXE drivers, it's not always necessary. Remove the ROM BAR requirement for legacy mode to support newer devices without a specified romfile. Signed-off-by: Tomita Moeko --- hw/vfio/igd

[PATCH v2] qapi: pluggable backend code generators

The 'qapi.backend.QAPIBackend' class defines an API contract for code generators. The current generator is put into a new class 'qapi.backend.QAPICBackend' and made to be the default impl. A custom generator can be requested using the '-k' arg which takes a fully qualified python class name qa

[PATCH v2 06/11] hw/riscv/riscv-iommu: add IOCOUNTINH mmio writes

From: Tomasz Jeznach RISCV_IOMMU_REG_IOCOUNTINH is done by riscv_iommu_process_iocntinh_cy(), which is called during riscv_iommu_mmio_write() callback via a new riscv_iommu_pricess_hpm_writes() helper. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Fran

[PATCH 06/10] vfio/igd: Consolidate OpRegion initialization into a single function

Both x-igd-opregion option and legacy mode require identical steps to set up OpRegion for IGD devices. Consolidate these steps into a single vfio_pci_igd_setup_opregion function. The function call in pci.c is wrapped with ifdef temporarily to prevent build error for non-x86 archs, it will be remov

[PATCH] iotests: Limit qsd-migrate to working formats

qsd-migrate is currently only working for raw, qcow2 and qed. Other formats are failing, e.g. because they don't support migration. Thus let's limit this test to the three usable formats now. Suggested-by: Kevin Wolf Signed-off-by: Thomas Huth --- tests/qemu-iotests/tests/qsd-migrate | 2 +- 1

[PATCH v4 06/24] target/m68k: Introduce M68K_FEATURE_FPU_PACKED_DECIMAL

Set for 68020 and 68030, but does nothing so far. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 2 ++ target/m68k/cpu.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 7b90e1e58f..b394d8bbb9 100644

[PATCH 00/10] vfio/igd: Remove legacy mode

This patchset removes some legacy checks and converts the legacy mode implicitly enabled by BDF 00:02.0 into x-igd-* options, including: * Removing PCI ROM BAR and VGA IO/MMIO range check before applying quirk * Using unified x-igd-opregion option for OpRegion access. * Introducing new x-igd-lpc op

[PATCH v2 07/11] hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write

From: Tomasz Jeznach RISCV_IOMMU_REG_IOHPMCYCLES writes are done by riscv_iommu_process_hpmcycle_write(), called by the mmio write callback via riscv_iommu_process_hpm_writes(). Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- hw/riscv/ri

Re: [PATCH 4/5] pcie, virtio: Remove redundant pm_cap

On 2/20/25 11:48 PM, Alex Williamson wrote: > The pm_cap on the PCIExpressDevice object can be distilled down > to the new instance on the PCIDevice object. > > Cc: Michael S. Tsirkin > Cc: Marcel Apfelbaum > Signed-off-by: Alex Williamson Reviewed-by: Eric Auger Eric > --- > hw/pci-bridg

Re: [PATCH V2 28/45] vfio: return mr from vfio_get_xlat_addr

On Mon, Feb 24, 2025 at 11:50:50AM -0500, Steven Sistare wrote: > > > I can do that, but it would add cycles. Is this considered a high > > > performance > > > path that may be called frequently? > > > > AFAICT, any vIOMMU mapping isn't high perf path. In this specific path, > > the refcount op

Re: [PATCH 0/4] ppc/amigaone patches

Am 22. Februar 2025 17:52:27 UTC schrieb BALATON Zoltan : >Hello, > >This series adds NVRAM and support for -kernel, -initrd and -append >options to the amigaone machine. This makes it easier to boot AmigaOS >and avoids a crash in the guest when it tries to access NVRAM. Looks like the above in

[ANNOUNCE] QEMU 9.2.2 Stable released

Hi everyone, The QEMU v9.2.2 stable release is now available. You can grab the tarball from our download page here: https://www.qemu.org/download/#source https://download.qemu.org/qemu-9.2.2.tar.xz https://download.qemu.org/qemu-9.2.2.tar.xz.sig (signature) v9.2.2 is now tagged in the o

[PATCH v2 11/11] docs/specs/riscv-iommu.rst: add HPM support info

Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- docs/specs/riscv-iommu.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst index b1538c9ead..000c7e1f57 100644 --- a/docs/specs/riscv-iommu.rst +++ b/docs/specs/

Re: [PATCH 00/61] target/arm: Implement FEAT_SME2

On 2/24/25 12:27, Richard Henderson wrote: On 2/6/25 11:56, Richard Henderson wrote: Based-on:20250201164012.1660228-1-peter.mayd...@linaro.org ("[PATCH v2 00/69] target/arm: FEAT_AFP and FEAT_RPRES") This implements the Scalar Matrix Extensions, version 2, plus two trivial extensions for float

Re: [PATCH 0/5] Improve Microchip Polarfire SoC customization

On Mon, Feb 24, 2025 at 03:14:00PM +1000, Alistair Francis wrote: > On Fri, Feb 21, 2025 at 4:31 AM Conor Dooley wrote: > > > > +cc qemu-riscv, Alistar. > > > > On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote: > > > Booting the microchip-icicle-kit machine using the latest PolarFir

[PATCH 05/10] vfio/pci: Make vfio_populate_vga static

vfio_populate_vga is no longer called in igd.c. Make it static. Signed-off-by: Tomita Moeko --- hw/vfio/pci.c | 2 +- hw/vfio/pci.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 89d900e9cf..1c45e3987e 100644 --- a/hw/vfio/pci.c +++ b/hw

[PATCH 07/10] vfio/igd: Move LPC bridge initialization to a separate function

A new option will soon be introduced to control whether to apply the LPC bridge/Host bridge ID quirk for the removal of implicit legacy mode. To prepare for this, move the LPC bridge initialization into a separate function. Signed-off-by: Tomita Moeko --- hw/vfio/igd.c | 125

[PATCH 01/10] vfio/igd: Remove GTT write quirk in IO BAR 4

The IO BAR4 of IGD devices contains a pair of 32-bit address/data registers, MMIO_Index (0x0) and MMIO_Data (0x4), which provide access to the MMIO BAR0 (GTTMMADR) from IO space. These registers are probably only used by the VBIOS, and are not documented by intel. The observed layout of MMIO_Index

[PATCH 02/10] vfio/igd: Do not include GTT stolen size in etc/igd-bdsm-size

Though GTT Stolen Memory (GSM) is right below Data Stolen Memory (DSM) in host address space, direct access to GSM is prohibited, and it is not mapped to guest address space. Both host and guest accesses GSM indirectly through the second half of MMIO BAR0 (GTTMMADR). Guest firmware only need to re

Re: [PATCH 3/5] vfio/pci: Delete local pm_cap

On 2/20/25 11:48 PM, Alex Williamson wrote: > This is now redundant to PCIDevice.pm_cap. > > Cc: Cédric Le Goater > Signed-off-by: Alex Williamson Reviewed-by: Eric Auger Eric > --- > hw/vfio/pci.c | 9 - > hw/vfio/pci.h | 1 - > 2 files changed, 4 insertions(+), 6 deletions(-) > >

[PATCH 08/10] vfio/pci: Add placeholder for device-specific config space quirks

IGD devices require device-specific quirk to be applied to their PCI config space. Currently, it is put in the BAR4 quirk that does nothing to BAR4 itself. Add a placeholder for PCI config space quirks to hold that quirk later. Signed-off-by: Tomita Moeko --- hw/vfio/pci-quirks.c | 5 + hw/v

Re: [PATCH 0/4] ppc/amigaone patches

On Mon, 24 Feb 2025, Bernhard Beschow wrote: Am 22. Februar 2025 17:52:27 UTC schrieb BALATON Zoltan : Hello, This series adds NVRAM and support for -kernel, -initrd and -append options to the amigaone machine. This makes it easier to boot AmigaOS and avoids a crash in the guest when it tries t

[PATCH] hw/misc/npcm_clk: fix buffer-overflow

Regression introduced by cf76c4 (hw/misc: Add nr_regs and cold_reset_values to NPCM CLK) cold_reset_values has a different size, depending on device used (NPCM7xx vs NPCM8xx). However, s->regs has a fixed size, which matches NPCM8xx. Thus, when initializing a NPCM7xx, we go past cold_reset_values

Re: [PATCH v5 06/17] hw/misc: Add nr_regs and cold_reset_values to NPCM GCR

Hello, This patch introduces a buffer-overflow, now reported by address sanitizer. I sent a patch: https://lore.kernel.org/qemu-devel/20250224205053.104959-1- pierrick.bouv...@linaro.org/T/#u You're welcome to review it, or fix the problem differently if there is a better approach. Regards,

Re: [PATCH] hw/misc/npcm_clk: fix buffer-overflow

Thanks! On Mon, Feb 24, 2025 at 12:51 PM Pierrick Bouvier < pierrick.bouv...@linaro.org> wrote: > Regression introduced by cf76c4 > (hw/misc: Add nr_regs and cold_reset_values to NPCM CLK) > > cold_reset_values has a different size, depending on device used > (NPCM7xx vs NPCM8xx). However, s->reg

Re: [PATCH v5 06/17] hw/misc: Add nr_regs and cold_reset_values to NPCM GCR

Thanks! I can review the patch. On Mon, Feb 24, 2025 at 12:52 PM Pierrick Bouvier < pierrick.bouv...@linaro.org> wrote: > Hello, > > This patch introduces a buffer-overflow, now reported by address sanitizer. > > I sent a patch: > https://lore.kernel.org/qemu-devel/20250224205053.104959-1- > pier

Re: [PATCH] hw/ppc/e500: Partial implementation of local access window registers

On Thu, 20 Feb 2025, Bernhard Beschow wrote: Am 13. Februar 2025 00:13:24 UTC schrieb BALATON Zoltan : Yes, your DTB based board code is a nice way to create different machines as the DTB already describes these offsets and irq connections and your code seems to be quite simple so I think it's

[PATCH 04/10] vfio/igd: Remove implicit VGA access enabled by legacy mode

Modern EFI-based system and drivers like i915 no longer use VGA IO/MMIO registers. Currently, legacy mode checks if the VGA decoding cycle is claimed by IGD, and implicitly exposes VGA address spaces for device. As we are going to remove legacy mode, remove this implicit behavior. If users want to

Re: [PATCH V2 28/45] vfio: return mr from vfio_get_xlat_addr

On 2/24/2025 2:20 PM, Peter Xu wrote: On Mon, Feb 24, 2025 at 11:50:50AM -0500, Steven Sistare wrote: I can do that, but it would add cycles. Is this considered a high performance path that may be called frequently? AFAICT, any vIOMMU mapping isn't high perf path. In this specific path, the

[PATCH 09/10] vfio/igd: Refactor vfio_probe_igd_bar4_quirk into pci config quirk

The actual IO BAR4 write quirk in vfio_probe_igd_bar4_quirk was removed in previous change, leaving the function not matching its name, so move it into the newly introduced vfio_config_quirk_setup. There is no functional change in this commit. For now, to align with current legacy mode behavior, i

[PATCH 10/10] vfio/igd: Replace legacy mode with options

IGD-specific quirks are implicitly enabled by legacy mode, which is toggled by assigning IGD to 00:02.0. This patch replaces legacy mode with explicit options for these quirks. The OpRegion quirk is merged to the exisiting x-igd-opregion option, while a new option x-igd-lpc is defined for the LPC b

Re: [PATCH v2 1/8] migration: Prioritize RDMA in ram_save_target_page()

On Fri, Feb 21, 2025 at 02:36:05PM +0800, Li Zhijian wrote: > Address an error in RDMA-based migration by ensuring RDMA is prioritized > when saving pages in `ram_save_target_page()`. > > Previously, the RDMA protocol's page-saving step was placed after other > protocols due to a refactoring in co

Re: [PATCH v2 5/8] migration: Add migration_capabilities_and_transport_compatible() helper

On Fri, Feb 21, 2025 at 02:36:09PM +0800, Li Zhijian wrote: > Similar to migration_channels_and_transport_compatible(), introduce a > new helper migration_capabilities_and_transport_compatible() to check if > the capabilites is compatible with the transport. > > Currently, only move the capabiliti

Re: [PATCH v2 7/8] migration/rdma: Remove redundant migration_in_postcopy checks

On Fri, Feb 21, 2025 at 02:36:11PM +0800, Li Zhijian wrote: > Since we have disabled RDMA + postcopy, it's safe to remove > the migration_in_postcopy() that follows the migration_rdma(). > > Signed-off-by: Li Zhijian > --- > migration/ram.c | 2 +- > migration/rdma.c | 5 +++-- > 2 files chang

Re: [PATCH v2 6/8] migraion: disable RDMA + postcopy-ram

On Fri, Feb 21, 2025 at 02:36:10PM +0800, Li Zhijian wrote: > It's believed that RDMA + postcopy-ram has been broken for a while. > Rather than spending time re-enabling it, let's simply disable it as a > trade-off. > > Signed-off-by: Li Zhijian Reviewed-by: Peter Xu -- Peter Xu

Re: [PATCH v2 8/8] migration: Add qtest for migration over RDMA

On Fri, Feb 21, 2025 at 02:36:12PM +0800, Li Zhijian wrote: > This qtest requires there is a RDMA(RoCE) link in the host. > In order to make the test work smoothly, introduce a > scripts/rdma-migration-helper.sh to > - setup a new Soft-RoCE(aka RXE) if it's root > - detect existing RoCE link > > T

[PATCH v4 20/24] target/m68k: Merge gen_store_fp, gen_store_mode_fp

This enables the exceptions raised by the actual store to be reflected as a failure. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/translate.c | 107 1 file changed, 53 insertions(+), 54 deletions(-) diff --git a/t

[PATCH v2] hvf: arm: sign extend when SSE=1

According to the ARM manual, when SSE=1 the data item must be sign extended. Signed-off-by: Joelle van Dyne --- target/arm/hvf/hvf.c | 4 1 file changed, 4 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 0afd96018e..43cf250eef 100644 --- a/target/arm/hvf/hvf.c

Re: [PATCH 2/5] pci: Use PCI PM capability initializer

On Mon, 24 Feb 2025 19:37:03 +0100 Eric Auger wrote: > Hi Alex, > > On 2/20/25 11:48 PM, Alex Williamson wrote: > > Switch callers directly initializing the PCI PM capability with > > pci_add_capability() to use pci_pm_init(). > > > > Cc: Dmitry Fleytman > > Cc: Akihiko Odaki > > Cc: Jason Wan

Re: [PATCH 2/5] pci: Use PCI PM capability initializer

Hi Alex, On 2/20/25 11:48 PM, Alex Williamson wrote: > Switch callers directly initializing the PCI PM capability with > pci_add_capability() to use pci_pm_init(). > > Cc: Dmitry Fleytman > Cc: Akihiko Odaki > Cc: Jason Wang > Cc: Stefan Weil > Cc: Sriram Yagnaraman > Cc: Keith Busch > Cc:

Re: [PATCH 1/5] hw/pci: Basic support for PCI power management

Hi Alex, On 2/20/25 11:48 PM, Alex Williamson wrote: > The memory and IO BARs for devices are only accessible in the D0 > power state. In other power states the PCI spec defines that the > device should respond to TLPs and messages with an Unsupported > Request response. The closest we can com

Re: [PATCH 5/5] hw/vfio/pci: Re-order pre-reset

On 2/20/25 11:48 PM, Alex Williamson wrote: > We want the device in the D0 power state going into reset, but the > config write can enable the BARs in the address space, which are > then removed from the address space once we clear the memory enable > bit in the command register. Re-order to c

Re: [PATCH 00/61] target/arm: Implement FEAT_SME2

On 2/6/25 11:56, Richard Henderson wrote: Based-on:20250201164012.1660228-1-peter.mayd...@linaro.org ("[PATCH v2 00/69] target/arm: FEAT_AFP and FEAT_RPRES") This implements the Scalar Matrix Extensions, version 2, plus two trivial extensions for float16 and bfloat16. This hasn't been tested mu

Re: [PATCH] QIOChannelSocket: Flush zerocopy socket error queue on ENOBUF failure for sendmsg

On Fri, Feb 21, 2025 at 04:44:48AM -0500, Manish Mishra wrote: > We allocate extra metadata SKBs in case of zerocopy send. This metadata memory > is accounted for in the OPTMEM limit. If there is any error with sending > zerocopy data or if zerocopy was skipped, these metadata SKBs are queued in >

[PATCH v3 00/44] x86: Improve operation under QEMU

U-Boot can start and boot an OS in both qemu-x86 and qemu-x86_64 but it is not perfect. With both builds, executing the VESA ROM causes an intermittent hang, at least on some AMD CPUs. With qemu-x86_64 kvm cannot be used since the move to long mode (64-bit) is done in a way that works on real har

[PATCH v2 3/6] hw/riscv: Make FDT optional for MPFS

Real-time kernels such as RTEMS or Zephyr may use a static device tree built into the kernel image. Do not require to use the -dtb option if -kernel is used for the microchip-icicle-kit machine. Issue a warning if no device tree is provided by the user since the machine does not generate one. Si

[PATCH v2 2/6] hw/riscv: More flexible FDT placement for MPFS

If the kernel entry is in the high DRAM area, place the FDT into this area. Signed-off-by: Sebastian Huber Reviewed-by: Alistair Francis --- hw/riscv/microchip_pfsoc.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip

[PATCH v2 1/6] hw/misc: Add MPFS system reset support

Signed-off-by: Sebastian Huber --- hw/misc/mchp_pfsoc_sysreg.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c index 7876fe0c5b..08196525aa 100644 --- a/hw/misc/mchp_pfsoc_sysreg.c +++ b/hw/misc/mchp_pfsoc_sysreg.c @@ -27,7 +27,

[PATCH v2 5/6] hw/riscv: Configurable MPFS CLINT timebase freq

This property enables the setting of the CLINT timebase frequency through the command line, for example: -machine microchip-icicle-kit,clint-timebase-frequency=1000 Signed-off-by: Sebastian Huber Reviewed-by: Philippe Mathieu-Daudé --- hw/riscv/microchip_pfsoc.c | 49

[PATCH v2 0/6] Improve Microchip Polarfire SoC customization

Booting the microchip-icicle-kit machine using the latest PolarFire SoC Hart Software Services (HSS) no longer works since Qemu lacks support for several registers (clocks, DRAM controller). Also reading from the SDCard does not work currently. In order to allow tests runs for real-time kernels su

Re: Building QEMU as a Shared Library

Hi Saanjh, here is a minimal patch that builds one shared library per target (arch, mode) where arch is cpu arch, and mode is system or user, and launch system-aarch64 through a simple driver: https://github.com/pbo-linaro/qemu/commit/fbb39cc64f77d4bf1e5e50795c75b62735bf5c5f With this, it co

[PATCH v2 4/6] hw/riscv: Allow direct start of kernel for MPFS

Further customize the -bios and -kernel options behaviour for the microchip-icicle-kit machine. If "-bios none -kernel filename" is specified, then do not load a firmware and instead only load and start the kernel image. Signed-off-by: Sebastian Huber --- hw/riscv/microchip_pfsoc.c | 57 +++

[PATCH v2 6/6] hw/riscv: microchip_pfsoc: Rework documentation

Mention that running the HSS no longer works. Document the changed boot options. Reorder documentation blocks. Update URLs. Signed-off-by: Sebastian Huber --- docs/system/riscv/microchip-icicle-kit.rst | 124 +++-- 1 file changed, 43 insertions(+), 81 deletions(-) diff --git

[PATCH v2 6/9] target/loongarch: Fix some modifiers for log formatting

target_ulong -> TARGET_FMT_ld vaddr -> VADDR_PRIx uint32_t -> PRIx32 Signed-off-by: Jiaxun Yang --- target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +- target/loongarch/tcg/tlb_helper.c | 2 +- target/loongarch/tcg/translate.c | 5 ++--- 3 files changed,

[PATCH v2 4/9] target/loongarch: Perform sign extension for IOCSR reads

As per LoongArch Reference Manual - Volume 1: Basic Architecture, 4.2.2. IOCSR Access Instructions: The reading value is described as "writes it to the general register rd after symbolic expansion." which means it should be sign extended. Signed-off-by: Jiaxun Yang --- target/loongarch/tcg/iocs

[PATCH v2 5/9] target/loongarch: Use target_ulong for iocsrrd helper results

Those results are all targeting TCGv values, which means they should be in target_ulong type. Signed-off-by: Jiaxun Yang --- target/loongarch/helper.h | 8 target/loongarch/tcg/iocsr_helper.c | 8 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/l

[PATCH v2 8/9] target/loongarch: Fix load type for gen_ll

gen_ll should use tcg_gen_qemu_ld_tl to load t1, as t1 is in TCGv which means it should be a tl type value. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Jiaxun Yang --- target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/t

[PATCH v2 3/9] target/loongarch: Fix PGD CSR for LoongArch32

As per manual, the source of PGD CSR is relevant to highest bit of BADV. In LoongArch32, all CSRs are 32 bits only, thus we should check bit 31 of BADV to determine PGDH/PGDL for LoongArch32. Signed-off-by: Jiaxun Yang --- target/loongarch/tcg/csr_helper.c | 2 +- 1 file changed, 1 insertion(+),

[PATCH v2 7/9] target/loongarch: Use target_ulong for CSR helpers

All CSRs are meant to be target_ulong wide in our setting. Signed-off-by: Jiaxun Yang --- target/loongarch/helper.h| 14 +++--- target/loongarch/tcg/op_helper.c | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/loongarch/helper.h b/target/loongarch/

[PATCH v2 0/9] target/loongarch: LoongArch32 fixes 1

Hi all, This series is a collection of small fixes I made to TCG for LoongArch32. There are still many thing broken, especially on CSRs. More series following. However this is sufficient to boot 32bit kernel. Thanks for revivewing! Signed-off-by: Jiaxun Yang --- Changes in v2: - Addressing min

[PATCH v2 9/9] target/loongarch: Introduce max32 CPU type

Introduce max32 CPU type as it's necessary to demonstrate all features we have in LA32. Signed-off-by: Jiaxun Yang --- target/loongarch/cpu.c | 152 +++-- 1 file changed, 122 insertions(+), 30 deletions(-) diff --git a/target/loongarch/cpu.c b/target/

[PATCH v2 1/9] target/loongarch: Enable rotr.w/rotri.w for LoongArch32

As per "LoongArch Reference Manual Volume 1: Basic Architecture" v1.1.0, "2.2 Table 2. Application-level basic integer instructions in LA32", rotr.w and rotri.w is a part of LA32 basic integer instructions. Note that those instructions are indeed not in LA32R subset, however QEMU is not performing

[PATCH v2 2/9] target/loongarch: Fix address generation for gen_sc

gen_sc should use make_address_i to obtain source address to ensure that address is properly truncated. Another temp value is created in middle to avoid data corruption as make_address_i may return the same memory location as src1. Signed-off-by: Jiaxun Yang --- target/loongarch/tcg/insn_trans/

[PATCH v3 02/44] x86: qemu: Switch to bochs display

The vesa display is widely used on hardware, but it is a bit of a pain with QEMU. It requires executing option ROMs, which either doesn't work with kvm, or is difficult to do in a kvm/QEMU-friendly way. THe bochs display is probably better anyway, so switch to that. It works fine with kvm as it do

[PATCH v3 32/44] x86: qemu: Use the new e820 API

Move over to use this API before making the code even more complicated. Signed-off-by: Simon Glass --- Changes in v3: - Add new patch to use the new e820 API arch/x86/cpu/qemu/e820.c | 48 ++-- 1 file changed, 12 insertions(+), 36 deletions(-) diff --git a/

[PATCH v3 03/44] x86: qemu: Enable dhrystone

Provide the 'dhry' command, which helps to check that kvm is being used properly with QEMU. Signed-off-by: Simon Glass --- (no changes since v1) configs/qemu-x86_64_defconfig | 1 + configs/qemu-x86_defconfig| 1 + 2 files changed, 2 insertions(+) diff --git a/configs/qemu-x86_64_defconfi

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