On Wed, Feb 19, 2025 at 09:52:35AM +0800, oen...@gmail.com wrote:
> From: Huaitong Han
>
> The vring call fd is set even when the guest does not use MSIX (e.g., virtio
> PMD). This results in unnecessary CPU overhead for handling virtio interrupts.
> The previous patch only optimized the conditio
On 5/5/23 23:24, Richard Henderson wrote:
The port currently does not support "oversize" guests, which
means riscv32 can only target 32-bit guests. We will soon be
building TCG once for all guests. This implies that we can
only support riscv64.
Since all Linux distributions target riscv64 not
Hi Cedric,
>
> On 2/13/25 04:35, Jamin Lin wrote:
> > This method simplifies the process of fetching and extracting assets
> > from the Aspeed GitHub repository.
> >
> > Signed-off-by: Jamin Lin
> > ---
> > tests/functional/test_aarch64_aspeed.py | 9 +
> > 1 file changed, 5 insertion
Hi Cedric,
> Subject: Re: [PATCH v3 18/28] hw/arm/aspeed: Add SoC and Machine Support
> for AST2700 A1
>
> On 2/13/25 04:35, Jamin Lin wrote:
> > The memory map for AST2700 A1 remains compatible with AST2700 A0.
> > However, the IRQ mapping has been updated for AST2700 A1, with GIC
> > interrupt
Hi Cedric,
> Subject: Re: [PATCH v3 21/28] hw/misc/aspeed_hace: Fix boot issue in the
> Crypto Manager Self Test
>
> On 2/13/25 04:35, Jamin Lin wrote:
> > Currently, it does not support the CRYPT command. Instead, it only
> > sends an interrupt to notify the firmware that the crypt command has
>
Mauro Carvalho Chehab writes:
> Em Wed, 05 Feb 2025 09:16:53 +0100
> Markus Armbruster escreveu:
[...]
>> Sorry if this has been answered already... why not GPL-2.0-or-later?
>>
>> More of the same below.
>
> No particular reason. It is just that GPL-2.0 is my preferred license.
>
> I'll cha
The pm_cap on the PCIExpressDevice object can be distilled down
to the new instance on the PCIDevice object.
Cc: Michael S. Tsirkin
Cc: Marcel Apfelbaum
Signed-off-by: Alex Williamson
---
hw/pci-bridge/pcie_pci_bridge.c | 1 -
hw/virtio/virtio-pci.c | 8 +++-
include/hw/pci/pcie.h
On Thu, Feb 20, 2025 at 04:57:51PM +0100, Eric Auger wrote:
> Hi Michael,
>
>
> On 2/20/25 4:25 PM, Michael S. Tsirkin wrote:
> > On Fri, Jan 31, 2025 at 10:55:26AM +0100, Eric Auger wrote:
> >> I tested [PATCH] virtio: Remove virtio devices on device_shutdown()
> >> https://lore.kernel.org/all/2
Hi Richard,
On 17/2/25 00:07, Richard Henderson wrote:
Create a special subclass for sub, because two backends can
support "subtract from immediate". Drop all backend support
for an immediate as the second operand, as we transform sub
to add during optimize.
Signed-off-by: Richard Henderson
-
On Wed, Feb 12, 2025 at 05:44:49AM +, Suravee Suthikulpanit wrote:
> Current amd-iommu model internally creates an AMDVI-PCI device. Here is
> a snippet from info qtree:
>
> bus: main-system-bus
> type System
> dev: amd-iommu, id ""
> xtsup = false
> pci-id = ""
> i
Em Mon, 3 Feb 2025 15:34:23 +0100
Igor Mammedov escreveu:
> On Fri, 31 Jan 2025 18:42:44 +0100
> Mauro Carvalho Chehab wrote:
>
> > There are two pointers that are needed during error injection:
> >
> > 1. The start address of the CPER block to be stored;
> > 2. The address of the ack.
> >
>
Hi Eric,
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH rfcv2 00/20] intel_iommu: Enable stage-1 translation for
>passthrough device
>
>
>Hi Zhenzhong
>
>On 2/19/25 9:22 AM, Zhenzhong Duan wrote:
>> Hi,
>>
>> Per Jason Wang's suggestion, iommufd nesting series[1] is split into
On 20/02/2025 22:13, Michael S. Tsirkin wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> On Mon, Jan 20, 2025 at 05:41:32PM +, CLEMENT MATHIEU--DRIF wrote:
>> From: Clement Mathieu
Pierrick kindly helped me to resolve this issue which ended
being trivial (to him!). Not tested on Windows so far.
Since v1:
- Include Pierrick's meson fix patch (adding Fixes: tag)
- Addressed Thomas review comments (config.py, os.path.join)
Philippe Mathieu-Daudé (2):
tests/functional: Introd
Introduce a helper to get the default shared library
suffix used on the host.
Suggested-by: Pierrick Bouvier
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
---
tests/functional/qemu_test/__init__.py | 2 +-
tests/functional/qemu_test/cmd.py | 1 -
tests/functional/qem
Not all platforms use the '.so' suffix for shared libraries,
which is how plugins are built. Use the recently introduced
dso_suffix() helper to get the proper host suffix.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2804
Suggested-by: Pierrick Bouvier
Suggested-by: Daniel P. Berrangé
On 20/2/25 09:02, Philippe Mathieu-Daudé wrote:
Introduce a helper to get the default shared library
suffix used on the host.
Suggested-by: Pierrick Bouvier
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
---
tests/functional/qemu_test/__init__.py | 2 +-
tests/function
Cc: John for advice on my somewhat nebulous mypy worries at the end.
Daniel P. Berrangé writes:
> The 'qapi.backend.QAPIBackend' class defines an API contract for
> code generators. The current generator is put into a new class
> 'qapi.backend.QAPICBackend' and made to be the default impl.
>
> A
Daniel P. Berrangé writes:
[...]
> When I think about the code generator and how this will all
> evolve over time, I have a strong feeling that none of this
> should be in qemu.git.
Yes, keeping it in qemu.git has its drawbacks. Testing is awkward
there. The coupling could cause friction.
I'
On 10:28 Thu 20 Feb , Philippe Mathieu-Daudé wrote:
> We shouldn't receive characters when the full UART or its
> receiver is disabled. However we don't want to break the
> possibly incomplete "my first bare metal assembly program"s,
> so we choose to simply display a warning when this occurs.
Slightly ping.
Hope to merge to qemu 10.0 if possible :)
Regards
Bibo Mao
On 2025/2/11 上午11:08, Bibo Mao wrote:
LoongArch cpu hotplug is based on ACPI GED device, it depends on
patchset where TYPE_HOTPLUG_HANDLER interface is added in ipi and extioi
interrupt controller class for cpu hotplug ev
On 12/10/18 10:20, Daniel P. Berrangé wrote:
On Fri, Oct 12, 2018 at 02:22:06AM +0200, Philippe Mathieu-Daudé wrote:
Hi Paolo,
Here are the changes you suggested in
https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg02294.html
chardev: Simplify IOWatchPoll::fd_can_read as a GSource
On 20/2/25 11:07, Philippe Mathieu-Daudé wrote:
On 12/10/18 10:20, Daniel P. Berrangé wrote:
On Fri, Oct 12, 2018 at 02:22:06AM +0200, Philippe Mathieu-Daudé wrote:
Hi Paolo,
Here are the changes you suggested in
https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg02294.html
charde
On 20/02/2025 09.02, Philippe Mathieu-Daudé wrote:
Introduce a helper to get the default shared library
suffix used on the host.
Suggested-by: Pierrick Bouvier
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
---
tests/functional/qemu_test/__init__.py | 2 +-
tests/funct
On 20/2/25 10:50, Paolo Bonzini wrote:
On 2/20/25 10:20, Philippe Mathieu-Daudé wrote:
Hi,
QEMU provides the global '-g' CLI option:
$ qemu-system-foo --help
-g WxH[xDEPTH] Set the initial graphical resolution and depth
This option is used to pass resolution/depth information to guest
fi
Hi Alex,
On 2/19/25 10:19 PM, Alex Williamson wrote:
> On Wed, 19 Feb 2025 11:58:44 -0700
> Alex Williamson wrote:
>
>> On Wed, 19 Feb 2025 18:58:58 +0100
>> Eric Auger wrote:
>>
>>> Since kernel commit:
>>> 2b2c651baf1c ("vfio/pci: Invalidate mmaps and block the access
>>> in D3hot power stat
It is a common convention in QEMU to return a positive value in case of
success, and a negated errno value in case of error. Unfortunately,
using errno portably in Rust is a bit complicated; on Unix the errno
values are supported natively by io::Error, but on Windows they are not;
so, use the libc
On Thu, Feb 06, 2025 at 01:28:37PM -0600, Babu Moger wrote:
> Date: Thu, 6 Feb 2025 13:28:37 -0600
> From: Babu Moger
> Subject: [PATCH v5 4/6] target/i386: Add feature that indicates WRMSR to
> BASE reg is non-serializing
> X-Mailer: git-send-email 2.34.1
>
> Add the CPUID bit indicates that a
> +static const CPUCaches epyc_genoa_v2_cache_info = {
> +.l1d_cache = &(CPUCacheInfo) {
> +.type = DATA_CACHE,
> +.level = 1,
> +.size = 32 * KiB,
> +.line_size = 64,
> +.associativity = 8,
> +.partitions = 1,
> +.sets = 64,
> +.l
> +static const CPUCaches epyc_turin_cache_info = {
> +.l1d_cache = &(CPUCacheInfo) {
> +.type = DATA_CACHE,
> +.level = 1,
> +.size = 48 * KiB,
> +.line_size = 64,
> +.associativity = 12,
> +.partitions = 1,
> +.sets = 64,
> +.lin
Albert Esteve writes:
> @@ -192,6 +194,24 @@ typedef struct VhostUserShared {
> unsigned char uuid[16];
> } VhostUserShared;
>
> +/* For the flags field of VhostUserMMap */
> +#define VHOST_USER_FLAG_MAP_R (1u << 0)
> +#define VHOST_USER_FLAG_MAP_W (1u << 1)
> +
> +typedef struct {
> +
On Thu, 20 Feb 2025 at 10:52, Peter Maydell wrote:
>
> On Thu, 20 Feb 2025 at 10:43, Peter Maydell wrote:
> >
> > On Tue, 18 Feb 2025 at 13:54, Peter Maydell
> > wrote:
> > >
> > > On Mon, 17 Feb 2025 at 14:55, Peter Maydell
> > > wrote:
> > > >
> > > > On Sat, 8 Feb 2025 at 16:39, Philippe M
Le 27/01/2025 à 19:29, Andrea Bolognani a écrit :
Right now information regarding the family each CPU type belongs
to is recorded in two places: the large data table at the top of
the script, and the qemu_host_family() function.
We can make things better by mapping host CPU architecture to
QEMU
Le 27/01/2025 à 19:29, Andrea Bolognani a écrit :
Until now, the script has worked under the assumption that a
host CPU can run binaries targeting any CPU in the same family.
That's a fair enough assumption when it comes to running i386
binaries on x86_64, but it doesn't quite apply in the genera
> +static const CPUCaches epyc_milan_v3_cache_info = {
> +.l1d_cache = &(CPUCacheInfo) {
> +.type = DATA_CACHE,
> +.level = 1,
> +.size = 32 * KiB,
> +.line_size = 64,
> +.associativity = 8,
> +.partitions = 1,
> +.sets = 64,
> +.l
On 20/02/2025 09:20, Philippe Mathieu-Daudé wrote:
Hi,
QEMU provides the global '-g' CLI option:
$ qemu-system-foo --help
-g WxH[xDEPTH] Set the initial graphical resolution and depth
This option is used to pass resolution/depth information to guest
firmwares in the machines defined in t
In the IOCanReadHandler sh_serial_can_receive(), if the Serial
Control Register 'Receive Enable' bit is set (bit 4), then we
return a size of (1 << 4) which happens to be equal to 16, so
effectively SH_RX_FIFO_LENGTH.
The IOReadHandler, sh_serial_receive1() takes care to receive
multiple chars, bu
While we model a 16-elements RX FIFO since the PL011 model was
introduced in commit cdbdb648b7c ("ARM Versatile Platform Baseboard
emulation"), we only read 1 char at a time!
Have the IOCanReadHandler handler return how many elements are
available, and use that in the IOReadHandler handler.
Examp
While we model a 4-elements RX FIFO since the MCF UART model
was introduced in commit 20dcee94833 ("MCF5208 emulation"),
we only read 1 char at a time!
Have the IOCanReadHandler handler return how many elements are
available, and use that in the IOReadHandler handler.
Signed-off-by: Philippe Math
On 19/02/2025 22:11, Peter Xu wrote:
> then
> in the test it tries to detect rdma link and fetch the ip only
It should work without root permission if we just*detect* and*fetch ip*.
Do you also mean we can split new-rdma-link.sh to 2 separate scripts
- add-rdma-link.sh
> +static CPUCaches epyc_v5_cache_info = {
> +.l1d_cache = &(CPUCacheInfo) {
> +.type = DATA_CACHE,
> +.level = 1,
> +.size = 32 * KiB,
> +.line_size = 64,
> +.associativity = 8,
> +.partitions = 1,
> +.sets = 64,
> +.lines_per_tag
On Tue, 18 Feb 2025 at 13:54, Peter Maydell wrote:
>
> On Mon, 17 Feb 2025 at 14:55, Peter Maydell wrote:
> >
> > On Sat, 8 Feb 2025 at 16:39, Philippe Mathieu-Daudé
> > wrote:
> > >
> > > Hi,
> > >
> > > This series add support for (async) FIFO on the transmit path
> > > of the PL011 UART.
> >
Le 27/01/2025 à 19:29, Andrea Bolognani a écrit :
This should make no difference from the functional point of
view and it's just preparation for upcoming changes.
Signed-off-by: Andrea Bolognani
---
scripts/qemu-binfmt-conf.sh | 17 ++---
1 file changed, 10 insertions(+), 7 delet
Hi Alex,
On 2/20/25 11:31 AM, Eric Auger wrote:
>
> Hi Alex,
>
> On 2/19/25 10:19 PM, Alex Williamson wrote:
>> On Wed, 19 Feb 2025 11:58:44 -0700
>> Alex Williamson wrote:
>>
>>> On Wed, 19 Feb 2025 18:58:58 +0100
>>> Eric Auger wrote:
>>>
Since kernel commit:
2b2c651baf1c ("vfio/pc
On Thu, 20 Feb 2025 at 10:43, Peter Maydell wrote:
>
> On Tue, 18 Feb 2025 at 13:54, Peter Maydell wrote:
> >
> > On Mon, 17 Feb 2025 at 14:55, Peter Maydell
> > wrote:
> > >
> > > On Sat, 8 Feb 2025 at 16:39, Philippe Mathieu-Daudé
> > > wrote:
> > > >
> > > > Hi,
> > > >
> > > > This series
On Thu, Feb 06, 2025 at 01:28:35PM -0600, Babu Moger wrote:
> Date: Thu, 6 Feb 2025 13:28:35 -0600
> From: Babu Moger
> Subject: [PATCH v5 2/6] target/i386: Update EPYC-Rome CPU model for Cache
> property, RAS, SVM feature bits
> X-Mailer: git-send-email 2.34.1
>
> Found that some of the cache p
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> Introduce 'fifo_depth' and 'fifo_available' local variables
> to better express the 'r' variable use.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> hw/char/pl011.c | 5 +++--
> 1 file changed, 3 insertions(+
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> Log FIFO use (availability and depth).
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> hw/char/pl011.c | 10 ++
> hw/char/trace-events | 7 ---
> 2 files changed, 10 insertions(+), 7 deletion
On 17/2/25 13:50, Peter Maydell wrote:
The work I needed to do to make various softfloat emulation behaviours
runtime-selectable for Arm FEAT_AFP has left the fpu code with very
few remaning target ifdefs. So this series turns the last remaning
ones into runtime behaviour choices and switches the
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> While we model a 32-elements RX FIFO since the PL011 model was
> introduced in commit 988f2442971 ("hw/char/imx_serial: Implement
> receive FIFO and ageing timer") we only read 1 char at a time!
"the IMX serial model"?
Reviewed-by: Luc Mic
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> Defines FIFO_DEPTH and use it, fixing coding style.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
> ---
> hw/char/mcf_uart.c | 10 +++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ch
>-Original Message-
>From: Alex Williamson
>Subject: Re: [RFC 0/2] hw/vfio/pci: Prevent BARs from being dma mapped in
>d3hot state
>
>On Thu, 20 Feb 2025 04:24:13 +
>"Duan, Zhenzhong" wrote:
>
>> >-Original Message-
>> >From: Alex Williamson
>> >Subject: Re: [RFC 0/2] hw/v
On 22:08 Wed 19 Feb , Philippe Mathieu-Daudé wrote:
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> While we model a 4-elements RX FIFO since the PL011 model
> was introduced in commit 20dcee94833
From: Pierrick Bouvier
./tests/functional/test_aarch64_tcg_plugins.py needs to have plugin
libinsn built. However, it's not listed as a dependency, so meson can't
know it needs to be built.
Thus, we keep track of all plugins, and add them as an explicit
dependency.
Fixes: 4c134d07b9e ("tests: a
On 20/02/2025 09.02, Philippe Mathieu-Daudé wrote:
Not all platforms use the '.so' suffix for shared libraries,
which is how plugins are built. Use the recently introduced
dso_suffix() helper to get the proper host suffix.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2804
Suggested-by
Hello,
On Wed, 19 Feb 2025 at 22:53, Fabiano Rosas wrote:
> I don't see anything stopping postcopy_start() from being called in the
> source in relation to multifd recv threads being setup in the
> destination. So far it seems possible that the source is opening the
> preempt channel while multif
On 2/20/25 10:20, Philippe Mathieu-Daudé wrote:
Hi,
QEMU provides the global '-g' CLI option:
$ qemu-system-foo --help
-g WxH[xDEPTH] Set the initial graphical resolution and depth
This option is used to pass resolution/depth information to guest
firmwares in the machines defined in the f
On 2/19/25 17:12, Vitalii Mordan wrote:
diff --git a/util/thread-pool.c b/util/thread-pool.c
index 27eb777e85..6c5f4d085b 100644
--- a/util/thread-pool.c
+++ b/util/thread-pool.c
@@ -111,9 +111,8 @@ static void *worker_thread(void *opaque)
ret = req->func(req->arg);
req->re
Philippe Mathieu-Daudé writes:
> Pierrick kindly helped me to resolve this issue which ended
> being trivial (to him!). Not tested on Windows so far.
>
> Since v1:
> - Include Pierrick's meson fix patch (adding Fixes: tag)
> - Addressed Thomas review comments (config.py, os.path.join)
>
> Philipp
Hi,
QEMU provides the global '-g' CLI option:
$ qemu-system-foo --help
-g WxH[xDEPTH] Set the initial graphical resolution and depth
This option is used to pass resolution/depth information to guest
firmwares in the machines defined in the following files:
hw/ppc/mac_newworld.c
hw/ppc/
On 20/2/25 09:48, Philippe Mathieu-Daudé wrote:
On 17/2/25 13:50, Peter Maydell wrote:
The work I needed to do to make various softfloat emulation behaviours
runtime-selectable for Arm FEAT_AFP has left the fpu code with very
few remaning target ifdefs. So this series turns the last remaning
one
Log FIFO use (availability and depth).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Luc Michel
---
hw/char/pl011.c | 10 ++
hw/char/trace-events | 7 ---
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/p
We shouldn't receive characters when the full UART or its
receiver is disabled. However we don't want to break the
possibly incomplete "my first bare metal assembly program"s,
so we choose to simply display a warning when this occurs.
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu
Since v1:
- Fixed typos (Luc)
Some UART devices implement a RX FIFO but their code
(via IOCanReadHandler) only return a size of 1 element,
while we can receive more chars.
This series takes advantage of the full depth.
Inspired by pm215 chat comment on yesterday's community
meeting on the PL011
Introduce 'fifo_depth' and 'fifo_available' local variables
to better express the 'r' variable use.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
hw/char/pl011.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/char/pl011.c b/hw/char/pl011.c
index
Defines FIFO_DEPTH and use it, fixing coding style.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Luc Michel
---
hw/char/mcf_uart.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/char/mcf_uart.c b/hw/char/mcf_uart.c
index 980a12fcb7d..95f269ee9b7 100644
-
While we model a 32-elements RX FIFO since the IMX serial
model was introduced in commit 988f2442971 ("hw/char/imx_serial:
Implement receive FIFO and ageing timer") we only read 1 char
at a time!
Have the IOCanReadHandler handler return how many elements are
available, and use that in the IOReadHa
While we model a 8-elements RX FIFO since the BCM2835 AUX model
was introduced in commit 97398d900ca ("bcm2835_aux: add emulation
of BCM2835 AUX block") we only read 1 char at a time!
Have the IOCanReadHandler handler return how many elements are
available, and use that in the IOReadHandler handle
This is now redundant to PCIDevice.pm_cap.
Cc: Cédric Le Goater
Signed-off-by: Alex Williamson
---
hw/vfio/pci.c | 9 -
hw/vfio/pci.h | 1 -
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index 6903f831e45f..ba4ef65b16fa 100644
--- a/hw/vfio
Switch callers directly initializing the PCI PM capability with
pci_add_capability() to use pci_pm_init().
Cc: Dmitry Fleytman
Cc: Akihiko Odaki
Cc: Jason Wang
Cc: Stefan Weil
Cc: Sriram Yagnaraman
Cc: Keith Busch
Cc: Klaus Jensen
Cc: Jesper Devantier
Cc: Michael S. Tsirkin
Cc: Marcel Apf
We want the device in the D0 power state going into reset, but the
config write can enable the BARs in the address space, which are
then removed from the address space once we clear the memory enable
bit in the command register. Re-order to clear the command bit
first, so the power state change do
Eric recently identified an issue[1] where during graceful shutdown
of a VM in a vIOMMU configuration, the guest driver places the device
into the D3 power state, the vIOMMU is then disabled, triggering an
AddressSpace update. The device BARs are still mapped into the AS,
but the vfio host driver
On Wed, Feb 12, 2025 at 05:44:48AM +, Suravee Suthikulpanit wrote:
> Currently, amd-iommu device does not support migration. This series addresses
> an issue due hidden AMDVI-PCI device enumeration. Then introduces migratable
> VMStateDescription, which saves necessary parameters for the device
Further customize the -bios and -kernel options behaviour for the
microchip-icicle-kit machine. If "-bios none -kernel filename" is
specified, then do not load a firmware and instead only load and start
the kernel image.
Signed-off-by: Sebastian Huber
---
v2: Use riscv_find_firmware() to locate
- Am 20. Feb 2025 um 23:29 schrieb Philippe Mathieu-Daudé phi...@linaro.org:
> Hi Conor,
>
> On 20/2/25 19:30, Conor Dooley wrote:
>> +cc qemu-riscv, Alistar.
>>
>> On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote:
>>> Booting the microchip-icicle-kit machine using the latest
On 20/02/2025 23:55, Peter Xu wrote:
> On Thu, Feb 20, 2025 at 05:40:38PM +0800, Li Zhijian wrote:
>> On 19/02/2025 22:11, Peter Xu wrote:
>>> then
>>> in the test it tries to detect rdma link and fetch the ip only
>> It should work without root permission if we just*detect* and*fetc
Hi Cedric,
> Subject: Re: [PATCH v3 08/28] hw/intc/aspeed: Add support for multiple output
> pins in INTC
>
> On 2/13/25 04:35, Jamin Lin wrote:
> > Added support for multiple output pins in the INTC controller to
> > accommodate the AST2700 A1.
> >
> > Introduced "num_outpins" to represent the
Let me share my performance report after applying the patches for the
information:
1. live mlx VF migration
outgoing migration:
+--+---+---++
| VF(s) number | 1 | 2 | 4 |
+--+-
>
> Looks good. I've queued it up on my gitlab staging tree, but
> Michael if you want to pick this one directly that's fine as well.
>
> I should be pushing out my gitlab tree shortly (bit of networking
> fun to deal with).
>
Hi, Jonathan
About qemu side, I have another question: Could the qe
Refactor the page saving logic by integrating the control_save_page()
function directly into ram_save_target_page(). This change consolidates the
RDMA migration decision-making process into a single function, enhancing
clarity and maintainability.
Signed-off-by: Li Zhijian
---
migration/ram.c |
This qtest requires there is a RDMA(RoCE) link in the host.
In order to make the test work smoothly, introduce a
scripts/rdma-migration-helper.sh to
- setup a new Soft-RoCE(aka RXE) if it's root
- detect existing RoCE link
Test will be skipped if there is no available RoCE link.
# Start of rdma t
qemu_rdma_save_page() no longer returns RAM_SAVE_CONTROL_NOT_SUPP
since commit a4832d299dd ("migration/rdma: Check sooner if we are in postcopy
for save_page()")
Signed-off-by: Li Zhijian
---
migration/rdma.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/migration/rdma.c
Similar to migration_channels_and_transport_compatible(), introduce a
new helper migration_capabilities_and_transport_compatible() to check if
the capabilites is compatible with the transport.
Currently, only move the capabilities vs RDMA transport to this
function.
Signed-off-by: Li Zhijian
---
Address an error in RDMA-based migration by ensuring RDMA is prioritized
when saving pages in `ram_save_target_page()`.
Previously, the RDMA protocol's page-saving step was placed after other
protocols due to a refactoring in commit bc38dc2f5f3. This led to migration
failures characterized by unkn
It's believed that RDMA + postcopy-ram has been broken for a while.
Rather than spending time re-enabling it, let's simply disable it as a
trade-off.
Signed-off-by: Li Zhijian
---
migration/migration.c | 4
1 file changed, 4 insertions(+)
diff --git a/migration/migration.c b/migration/migr
Refactor the migration control logic by eliminating the
`RAM_SAVE_CONTROL_NOT_SUPP` return value within the migration codebase.
This involves moving the checks for RDMA migration status and postcopy
state from rdma_control_save_page() to control_save_page()
With this change, control_save_page() n
Since we have disabled RDMA + postcopy, it's safe to remove
the migration_in_postcopy() that follows the migration_rdma().
Signed-off-by: Li Zhijian
---
migration/ram.c | 2 +-
migration/rdma.c | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/migration/ram.c b/migratio
Reviewed-by: Clément Mathieu--Drif
On 19/02/2025 09:22, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> In early days vtd_ce_get_rid2pasid_entry() is used to get pasid
Em Mon, 3 Feb 2025 16:22:36 +0100
Igor Mammedov escreveu:
> On Mon, 3 Feb 2025 11:09:34 +
> Jonathan Cameron wrote:
>
> > On Fri, 31 Jan 2025 18:42:41 +0100
> > Mauro Carvalho Chehab wrote:
> >
> > > Now that the ghes preparation patches were merged, let's add support
> > > for error in
John Snow writes:
> On Wed, Feb 19, 2025 at 8:22 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > "The text handler you add looks just like the existing latex handler. Does
>> > LaTeX output lack "little headings", too?"
>> >
>> > Yes, almost certainly. Can you let me know which outpu
>-Original Message-
>From: Alex Williamson
>Subject: [PATCH 4/5] pcie, virtio: Remove redundant pm_cap
>
>The pm_cap on the PCIExpressDevice object can be distilled down
>to the new instance on the PCIDevice object.
>
>Cc: Michael S. Tsirkin
>Cc: Marcel Apfelbaum
>Signed-off-by: Alex
- It fix the RDMA migration broken issue
- disable RDMA + postcopy
- some cleanups
- Add a qtest for RDMA at last
Changs since V1[0]:
Add some saparate patches to refactor and cleanup based on V1
[0]
https://lore.kernel.org/qemu-devel/20250218074345.638203-1-lizhij...@fujitsu.com/
Li Zhijian (8
Hi Cedric,
>
> Hi Cedric,
>
> > Subject: Re: [PATCH v3 21/28] hw/misc/aspeed_hace: Fix boot issue in
> > the Crypto Manager Self Test
> >
> > On 2/13/25 04:35, Jamin Lin wrote:
> > > Currently, it does not support the CRYPT command. Instead, it only
> > > sends an interrupt to notify the firmwa
On Thu, Feb 20, 2025 at 03:48:53PM -0700, Alex Williamson wrote:
> Eric recently identified an issue[1] where during graceful shutdown
> of a VM in a vIOMMU configuration, the guest driver places the device
> into the D3 power state, the vIOMMU is then disabled, triggering an
> AddressSpace update.
On Tue, Jan 28, 2025 at 07:57:03PM +0100, David Hildenbrand wrote:
> This is based-on [1], which adds MSI-X support to virtio-balloon-pci,
> but can be applied independently.
>
> Turns out it is fairly easy to get virtio-mem-pci running on s390x. We
> only have to add MSI-X support to virtio-mem-p
Hi Zhao,
On 2/20/2025 5:26 AM, Zhao Liu wrote:
+static const CPUCaches epyc_milan_v3_cache_info = {
+.l1d_cache = &(CPUCacheInfo) {
+.type = DATA_CACHE,
+.level = 1,
+.size = 32 * KiB,
+.line_size = 64,
+.associativity = 8,
+.partitions = 1,
+
Hi Zhao,
On 2/20/2025 6:00 AM, Zhao Liu wrote:
On Thu, Feb 06, 2025 at 01:28:37PM -0600, Babu Moger wrote:
Date: Thu, 6 Feb 2025 13:28:37 -0600
From: Babu Moger
Subject: [PATCH v5 4/6] target/i386: Add feature that indicates WRMSR to
BASE reg is non-serializing
X-Mailer: git-send-email 2.34.
Hi Zhao,
On 2/20/2025 6:05 AM, Zhao Liu wrote:
+static const CPUCaches epyc_genoa_v2_cache_info = {
+.l1d_cache = &(CPUCacheInfo) {
+.type = DATA_CACHE,
+.level = 1,
+.size = 32 * KiB,
+.line_size = 64,
+.associativity = 8,
+.partitions = 1,
+
Hi Zhao,
On 2/20/2025 5:18 AM, Zhao Liu wrote:
On Thu, Feb 06, 2025 at 01:28:35PM -0600, Babu Moger wrote:
Date: Thu, 6 Feb 2025 13:28:35 -0600
From: Babu Moger
Subject: [PATCH v5 2/6] target/i386: Update EPYC-Rome CPU model for Cache
property, RAS, SVM feature bits
X-Mailer: git-send-email
Hi Zhao,
On 2/20/2025 6:11 AM, Zhao Liu wrote:
+static const CPUCaches epyc_turin_cache_info = {
+.l1d_cache = &(CPUCacheInfo) {
+.type = DATA_CACHE,
+.level = 1,
+.size = 48 * KiB,
+.line_size = 64,
+.associativity = 12,
+.partitions = 1,
+
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