On Tue, 4 Feb 2025 at 08:37, Peter Maydell wrote:
> On Thu, 30 Jan 2025 at 22:31, Edgar E. Iglesias
> wrote:
> > On Mon, Jan 27, 2025 at 8:40 AM Peter Maydell
> wrote:
> >> On Thu, 19 Dec 2024 at 06:17, Andrew.Yuan
> wrote:
> >> > -rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset
On Tue, 4 Feb 2025 at 22:37, Peter Maydell wrote:
> On Thu, 30 Jan 2025 at 22:31, Edgar E. Iglesias
> wrote:
> > On Mon, Jan 27, 2025 at 8:40 AM Peter Maydell
> > wrote:
> >> On Thu, 19 Dec 2024 at 06:17, Andrew.Yuan
> >> wrote:
> >> > -rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr
On Wed, Feb 05, 2025 at 05:57:08PM +0530, Prasad Pandit wrote:
> From: Prasad Pandit
>
> Move MULTIFD_ macros to the header file so that
> they are accessible from other source files.
>
> Reviewed-by: Fabiano Rosas
> Signed-off-by: Prasad Pandit
Reviewed-by: Peter Xu
--
Peter Xu
On Wed, Feb 05, 2025 at 05:57:09PM +0530, Prasad Pandit wrote:
> From: Prasad Pandit
>
> Refactor ram_save_target_page legacy and multifd
> functions into one. Other than simplifying it,
> it frees 'migration_ops' object from usage, so it
> is expunged.
>
> Reviewed-by: Fabiano Rosas
> Signed-o
On Fri, Jan 31, 2025 at 8:18 AM Markus Armbruster wrote:
> Cc: John Snow for Python typing expertise.
>
> Daniel P. Berrangé writes:
>
> > This replaces use of the constants from the QapiSpecialFeatures
> > enum, with constants from the auto-generate QapiFeatures enum
> > in qapi-features.h
> >
This reflects the latest frozen version of the RISC-V Debug
specification (1.0.0-rc4) which includes the Sdtrig extension.
Signed-off-by: Rob Bradford
---
disas/riscv.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 305dd40ac4..85cd2a9c
Some extra spaces made into into the RISC-V opcode data table.
Signed-off-by: Rob Bradford
---
disas/riscv.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 4075ed6bfe..305dd40ac4 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
The function boston_fdt_filter() can return NULL on errors (in which
case it will print an error message). When we call this from the
non-FIT-image codepath, we aren't checking the return value, so we
will plough on with a NULL pointer, and segfault in fdt_totalsize().
Check for errors here.
Sign
On Tue, 20 Aug 2024 at 12:30, Florian Lugou wrote:
>
> > > $ aarch64-none-elf-gcc -ffreestanding -nostdlib -T
> > > qemu/tests/tcg/aarch64/system/kernel.ld -o test test.S
> > >
> > > $ qemu-system-aarch64 \
> > > -machine virt,secure=on,gic-version=3 \
> > > -cpu cortex-a57 \
> >
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness on the single machine using the
device.
Signed-off-by: Philippe Mathieu-D
The archive used in test_microblaze_s3adsp1800.py (testing a
big-endian target) contains a big-endian kernel. Rename using
the _BE suffix.
Similarly, the archive in test_microblazeel_s3adsp1800 (testing
a little-endian target) contains a little-endian kernel. Rename
using _LE suffix.
These change
Ensure microblaze machines can run cross-endianness by
running all tests on all machines.
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/test_microblaze_s3adsp1800.py | 6 ++
tests/functional/test_microblazeel_s3adsp1800.py | 6 ++
2 files changed,
Have the MicroblazeMachine class being common to both
MicroblazeBigEndianMachine and MicroblazeLittleEndianMachine
classes. Move the xmaton and ballerina tests to the parent class.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
.../functional/test_microblaze_s3adsp1800.py |
Consider the CPU ENDI bit, swap instructions when the CPU
endianness doesn't match the binary one.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/microblaze/cpu.h | 7 +++
target/microblaze/translate.c | 5 +++--
2 files changed, 10 insertions(+), 2 de
All callers of do_load() / do_store() set MO_TE flag.
Set it once in the callees.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/microblaze/translate.c | 36 +++
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/targ
Make microblaze tests a bit more generic.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
tests/functional/test_microblaze_s3adsp1800.py | 7 +--
tests/functional/test_microblazeel_s3adsp1800.py | 7 +--
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness on the single machine using the
device.
Reviewed-by: Richard Henderson
S
Introduce an abstract machine parent class which defines
the 'little_endian' property. Duplicate the current machine,
which endian is tied to the binary endianness, to one big
endian and a little endian machine; updating the machine
description. Keep the current default machine for each binary.
'p
mo_endian() returns the target endianness, currently static.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/microblaze/translate.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microbla
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair
of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN.
Add the "little-endian" property to select the device
endianness, defaulting to little endian.
Set the proper endianness for each machine using the device.
Reviewed-by: Richard Henderson
Signed
When a property value is static (not provided by QMP or CLI),
error shouldn't happen, otherwise it is a programming error.
Therefore simplify and use &error_abort as this can't fail.
Reported-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
---
hw/arm/xl
Commit f0ec14c78c4 ("tests/avocado: Fix console data loss") fixed
QEMUMachine's problem with console, we don't need to use the sleep()
kludges.
Suggested-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/test_microblazeel_s3adsp1800.py | 8 +++-
1 file changed, 3 in
When the IOMMU address space width is smaller than the physical
address width, a MMIO region of a device can fail to map because the
region is outside the supported IOVA ranges of the VM. In this case,
PCI peer-to-peer transactions on BARs are not supported. This can
occur with the 39-bit IOMMU add
Depending on the configuration of the host and VM, a passthrough
device may generate recurring DMA mapping errors at runtime. In such
cases, reporting the issue once is sufficient.
We have already the warn/error_report_once() routines taking a format
and arguments. Using the same design pattern, a
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Hello,
Under certain circumstances, a MMIO region of a device fails to map
because the region is outside the supported IOVA ranges of the VM. In
this case, PCI peer-to-peer transactions on BARs are not suppo
This helper will be useful in the listener handlers to extract the
VFIO device from a memory region using memory_region_owner(). At the
moment, we only care for PCI passthrough devices. If the need arises,
we will add more.
Signed-off-by: Cédric Le Goater
---
include/hw/vfio/vfio-common.h | 1 +
On 06/02/2025 12.33, Philippe Mathieu-Daudé wrote:
Ensure microblaze machines can run cross-endianness by
running all tests on all machines.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/test_microblaze_s3adsp1800.py | 6 ++
tests/functional/test_microblazeel_s3adsp1800.py
> >> > > The select&umask is the common way for x86 to identify the PMU event,
> >> > > so support this way as the "x86-default" format in kvm-pmu-filter
> >> > > object.
> >> >
> >> > So, format 'raw' lets you specify the PMU event code as a number, wheras
> >> > 'x86-default' lets you specify it
On Thu, Feb 06, 2025 at 02:53:58PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Daniel,
>
> On 6/2/25 14:20, Daniel P. Berrangé wrote:
> > On Thu, Feb 06, 2025 at 02:10:47PM +0100, Philippe Mathieu-Daudé wrote:
> > > Introduce an abstract machine parent class which defines
> > > the 'little_endian' p
To ease the debug of reset sequence, let's add a trace point
in vfio_reset_handler()
Signed-off-by: Eric Auger
---
hw/vfio/common.c | 1 +
hw/vfio/trace-events | 1 +
2 files changed, 2 insertions(+)
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index f7499a9b74..173fb3a997 100644
--- a/
Add missing Sdtrig CSRs per the latest RISC-V Debug specification. (+ minor
whitespace fix)
Rob Bradford (2):
disas/riscv: Fix minor whitespace issues
disas/riscv: Add missing Sdtrig CSRs
disas/riscv.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
--
2.48.1
Commit fc4e394b28 removed the last caller of blk_op_is_blocked(). Remove
the now unused function.
Signed-off-by: Kevin Wolf
---
include/system/block-backend-global-state.h | 1 -
block/block-backend.c | 12
2 files changed, 13 deletions(-)
diff --git a/includ
On Thu, Feb 06, 2025 at 03:07:06PM +, Shameerali Kolothum Thodi wrote:
> > If we set the physical/guest SMMU relationship directly, then at the
> > time the VFIO device is plugged, we can diagnose the incorrectly
> > placed VFIO device, and better reason about behaviour.
>
> Agree.
Can you ju
On 06/02/2025 14.10, Philippe Mathieu-Daudé wrote:
Commit f0ec14c78c4 ("tests/avocado: Fix console data loss") fixed
QEMUMachine's problem with console, we don't need to use the sleep()
kludges.
Suggested-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/test_microbl
On Thu, Feb 06, 2025 at 01:02:38PM -0400, Jason Gunthorpe wrote:
> On Thu, Feb 06, 2025 at 03:07:06PM +, Shameerali Kolothum Thodi wrote:
> > > If we set the physical/guest SMMU relationship directly, then at the
> > > time the VFIO device is plugged, we can diagnose the incorrectly
> > > place
On 06/02/2025 12.33, Philippe Mathieu-Daudé wrote:
Make microblaze tests a bit more generic.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/functional/test_microblaze_s3adsp1800.py | 7 +--
tests/functional/test_microblazeel_s3adsp1800.py | 7 +--
2 files changed, 10 insertions(+
Peter Xu writes:
> On Wed, Feb 05, 2025 at 05:42:37PM -0300, Fabiano Rosas wrote:
>> Fabiano Rosas writes:
>>
>> > Daniel P. Berrangé writes:
>> >
>> >> On Tue, Feb 04, 2025 at 10:31:31AM -0500, Peter Xu wrote:
>> >>> On Tue, Feb 04, 2025 at 03:39:00PM +0100, Maciej S. Szmigiero wrote:
>> >>>
"Maciej S. Szmigiero" writes:
> On 5.02.2025 21:42, Fabiano Rosas wrote:
>> Fabiano Rosas writes:
>>
>>> Daniel P. Berrangé writes:
>>>
On Tue, Feb 04, 2025 at 10:31:31AM -0500, Peter Xu wrote:
> On Tue, Feb 04, 2025 at 03:39:00PM +0100, Maciej S. Szmigiero wrote:
>> On 3.02.2025
On 2/6/25 9:53 AM, Daniel P. Berrangé wrote:
> On Fri, Jan 31, 2025 at 05:08:28PM +0100, Eric Auger wrote:
>> Hi,
>>
>>
>> On 1/31/25 4:23 PM, Shameerali Kolothum Thodi wrote:
-Original Message-
From: Jason Gunthorpe
Sent: Friday, January 31, 2025 2:54 PM
To: Shamee
gs/pull-9p-20250206
for you to fetch changes up to bfa7bf02782dbd996201c90f850ca11730041af1:
MAINTAINERS: Mark me as reviewer only for 9pfs (2025-02-06 17:10:46 +0100)
* Greg Kurz steps back as maintainer of 9pfs.
* Make multidevs=rem
1a6ed33cc5 introduced option multidevs=remap|forbid|warn and made
"warn" the default option.
As it turned out though, e.g. by several reports in conjunction with
following 9p client issue:
https://github.com/torvalds/linux/commit/850925a8133c73c4a2453c360b2c3beb3bab67c9
Many people are just igno
Improve tracing of 9p 'Topen' request type by showing open() flags as
human-readable text.
E.g. trace output:
v9fs_open tag 0 id 12 fid 2 mode 100352
would become:
v9fs_open tag=0 id=12 fid=2 mode=100352(RDONLY|NONBLOCK|DIRECTORY|
TMPFILE|NDELAY)
Therefor add a new utility function qemu_
'Twalk' is the most important request type in the 9p protocol to look out
for when debugging 9p communication. That's because it is the only part
of the 9p protocol which actually deals with human-readable path names,
whereas all other 9p request types work on numeric file IDs (FIDs) only.
Improve
To pave the way for adding new test use_dir_after_unlink with subsequent
patch, i.e. making it clear that the existing test is just about unlinked
files, not unlinked directories.
Signed-off-by: Christian Schoenebeck
Message-Id:
<9d2ca46a58b812ad17ca7bb8a84f12252d3e3832.1736427878.git.qemu_...@c
From: Greg Kurz
I still review 9pfs changes from time to time but I'm definitely
not able to do actual maintainer work. Drop my tree on the way
as I'll obviously not use it anymore, and it has been left
untouched since May 2020.
Signed-off-by: Greg Kurz
Reviewed-by: Christian Schoenebeck
Messa
Sending a Treaddir request on an unlinked directory should also succeed
if the directory was alread opened before unlink. We just check that no
error occurs and that we get some kind of Treaddir result, but completely
ignore the actual Treaddir result content. In fact, there should be no
system as
After removing a directory from the filesystem, it should still be
possible to operate on the directory if the directory has been opened
before.
As a first step this new test will verify whether Tgetattr request
works on the unlinked directory.
Signed-off-by: Christian Schoenebeck
Message-Id:
<
> >> +static int sanitize_range(CXLType3Dev *ct3d, uint64_t dpa_addr, size_t
> >> length,
> >> + uint8_t fill_value)
> >> +{
> >> +
> >> +MemoryRegion *vmr = NULL, *pmr = NULL;
> >> +uint64_t vmr_size = 0, pmr_size = 0;
> >> +AddressSpace *as = NULL;
> >> +
Currently the iommu may be reset before the devices
it protects. For example this happens with virtio-net.
Let's use 3-phase reset mechanism and reset the IOMMU on
exit phase intead.
Signed-off-by: Eric Auger
---
hw/virtio/virtio-iommu.c | 9 +
hw/virtio/trace-events | 2 +-
2 files c
Currently the iommu may be reset before the devices
it protects. For example this happens with virtio-scsi-pci.
when system_reset is issued from qmp monitor, spurious
"virtio: zero sized buffers are not allowed" warnings can
be observed.
Signed-off-by: Eric Auger
---
hw/arm/smmuv3.c | 9
Currently the IOMMU may be reset before the devices
it protects. For example this happens with virtio-net.
Let's use 3-phase reset mechanism and reset the IOMMU on
exit phase instead.
Signed-off-by: Eric Auger
---
hw/i386/intel_iommu.c | 8 +---
hw/i386/trace-events | 1 +
2 files changed,
This is a follow-up of Peter's attempt to fix the fact that
vIOMMUs are likely to be reset before the device they protect:
[PATCH 0/4] intel_iommu: Reset vIOMMU after all the rest of devices
https://lore.kernel.org/all/20240117091559.144730-1-pet...@redhat.com/
This is especially observed with vi
From: Peter Xu
No bug report for this, but logically tearing down of existing address
space should happen before reset of IOMMU state / registers, because the
current address spaces may still rely on those information.
Signed-off-by: Peter Xu
Signed-off-by: Eric Auger
---
hw/i386/intel_iommu.
On 6/2/25 15:31, Daniel P. Berrangé wrote:
On Thu, Feb 06, 2025 at 02:53:58PM +0100, Philippe Mathieu-Daudé wrote:
Hi Daniel,
On 6/2/25 14:20, Daniel P. Berrangé wrote:
On Thu, Feb 06, 2025 at 02:10:47PM +0100, Philippe Mathieu-Daudé wrote:
Introduce an abstract machine parent class which def
On 6/2/25 14:49, BALATON Zoltan wrote:
On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote:
On 6/2/25 13:49, BALATON Zoltan wrote:
On Thu, 6 Feb 2025, Philippe Mathieu-Daudé wrote:
On 15/1/25 20:04, BALATON Zoltan wrote:
The interrupt enable registers are not reset to 0 but some bits are
enabled
On Fri, 24 Jan 2025 at 17:51, Philippe Mathieu-Daudé wrote:
>
> fifo_timeout_timer is created in the DeviceRealize handler,
> not in the instance_init one. For parity, delete it in
> DeviceUnrealize, rather than instance_finalize.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Mayd
On 2/6/25 18:44, Cédric Le Goater wrote:
For pseries machines, commit 567b5b309abe ("vfio/pci: Relax DMA map
errors for MMIO regions") introduced 2 error reports to notify the
user of MMIO mapping errors. Consolidate both code paths under one.
Cc: Harsh Prateek Bora
Cc: Shivaprasad G Bhat
S
> -Original Message-
> From: Daniel P. Berrangé
> Sent: Thursday, February 6, 2025 2:47 PM
> To: Shameerali Kolothum Thodi
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org;
> eric.au...@redhat.com; peter.mayd...@linaro.org; j...@nvidia.com;
> nicol...@nvidia.com; ddut...@redhat.com; Lin
On Fri, 24 Jan 2025 at 17:51, Philippe Mathieu-Daudé wrote:
>
> QOM types are now registered using as TypeInfo via DEFINE_TYPES()
> or type_init(). Update TYPE_SH_SERIAL, removing the empty QOM
> instance_init/finalize handlers.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/char/sh_serial
On Tue, 2025-02-04 at 14:52 +, Peter Maydell wrote:
> On Tue, 4 Feb 2025 at 14:17, David Woodhouse wrote:
> >
> > On Tue, 2025-02-04 at 13:49 +, Peter Maydell wrote:
> > > On Thu, 16 Jan 2025 at 14:05, David Woodhouse
> > > wrote:
> > > > + qemu_register_reset(vmclock_handle_reset, vm
We originally implemented '-machine dumpdtb' in a fairly ad-hoc way:
every machine using FDT is supposed to call qemu_fdt_dumpdtb() once
it has finished creating and modifying the DTB; if the user passed in
the machine option then qemu_fdt_dumpdtb() will write the FDT to a
file and then exit QEMU.
I have added your project idea to the wiki. Please make further
changes directly on the wiki.
https://wiki.qemu.org/Google_Summer_of_Code_2025#Adding_Kani_proofs_for_Virtqueues_in_Rust-vmm
Thanks,
Stefan
Currently we handle the 'dumpdtb' machine sub-option ad-hoc in every
board model that has an FDT. It's up to the board code to make sure
it calls qemu_fdt_dumpdtb() in the right place.
This means we're inconsistent and often just ignore the user's
command line argument:
* if the board doesn't ha
Currently if the user requests via -machine dumpdtb=file.dtb that we
dump the DTB, but the machine doesn't have a DTB, we silently ignore
the option. This is confusing to users, and is a legacy of the old
board-specific implementation of the option, where if the execution
codepath didn't go via a
The openrisc machines don't set MachineState::fdt to point to their
DTB blob. This means that although the command line '-machine
dumpdtb=file.dtb' option works, the equivalent QMP and HMP monitor
commands do not, but instead produce the error "This machine doesn't
have a FDT".
Set MachineState::
In hmp_dumpdtb(), we print a message when the command succeeds. This
message is missing the trailing \n, so the HMP command prompt is
printed immediately after it. We also weren't capitalizing 'DTB', or
quoting the filename in the message. Fix these nits.
Signed-off-by: Peter Maydell
---
moni
Hi,
On 2/6/25 12:42 PM, Eugenio Perez Martin wrote:
On Thu, Feb 6, 2025 at 6:26 AM Sahil Siddiq wrote:
Hi,
On 2/4/25 11:40 PM, Eugenio Perez Martin wrote:
On Tue, Feb 4, 2025 at 1:49 PM Sahil Siddiq wrote:
On 1/31/25 12:27 PM, Eugenio Perez Martin wrote:
On Fri, Jan 31, 2025 at 6:04 AM S
The boston machine doesn't set MachineState::fdt to the DTB blob that
it has loaded or created, which means that the QMP/HMP dumpdtb
monitor commands don't work.
Setting MachineState::fdt is easy in the non-FIT codepath: we can
simply do so immediately before loading the DTB into guest memory.
The
"Maciej S. Szmigiero" writes:
> On 6.02.2025 15:13, Fabiano Rosas wrote:
>> "Maciej S. Szmigiero" writes:
>>
>>> On 5.02.2025 21:42, Fabiano Rosas wrote:
Fabiano Rosas writes:
> Daniel P. Berrangé writes:
>
>> On Tue, Feb 04, 2025 at 10:31:31AM -0500, Peter Xu wrote:
>>>
On Mon, 3 Feb 2025 at 14:41, Alex Bennée wrote:
>
> Don't both creating a GString to temporarily hold our qtest command.
> Instead do a simpler g_strndup and use autofree to clean up
> afterwards.
>
> Signed-off-by: Alex Bennée
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 3 Feb 2025 at 14:42, Alex Bennée wrote:
>
> It is invalid to call clock_step with an implied time to step forward
> as if no timers are running we won't be able to advance.
>
> Signed-off-by: Alex Bennée
>
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On 6/2/25 18:47, Richard Henderson wrote:
On 2/6/25 09:32, Philippe Mathieu-Daudé wrote:
We only support 32-bit TriCore architecture.
Signed-off-by: Philippe Mathieu-Daudé
---
target/tricore/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/tricore/t
Alistair's email is typed differently, so the get_maintainer.pl
script add it twice :) Unify to reduce traffic.
$ git grep -h 'Alistair Francis' -- MAINTAINERS | sort -u
M: Alistair Francis
M: Alistair Francis
M: Alistair Francis
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS
Some places already use the hwaddr type. Use it all over
the API allows it to be target agnostic. Use cpu_env() in
riscv_plic_hart_config_string() to shorten the access.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/riscv/boot.h | 21 ++---
include/hw/riscv/boot_op
opentitan_machine_init() calls get_system_memory(),
which is declared in "exec/address-spaces.h". Include
it in order to avoid when refactoring unrelated headers:
hw/riscv/opentitan.c:83:29: error: call to undeclared function
'get_system_memory'
83 | MemoryRegion *sys_mem = get_system_
"cpu.h" is target-specific. Definitions which can be used
by hw/ code when building QOM blocks can be in "cpu-qom.h",
which is target-agnostic.
Move the MISA bits (removing the pointless target_ulong cast)
and the IRQ index definitions.
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu
opentitan.c, riscv-iommu-pci.c, riscv-iommu-sys.c don't depend
on target-specific knowledge. Move them to common_ss[] to build
them once.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/riscv/meson.build | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/meson.build b
On 6/2/25 19:18, Philippe Mathieu-Daudé wrote:
Alistair's email is typed differently, so the get_maintainer.pl
script add it twice :) Unify to reduce traffic.
$ git grep -h 'Alistair Francis' -- MAINTAINERS | sort -u
M: Alistair Francis
M: Alistair Francis
M: Alistair Francis
Sig
On Thu, Feb 06, 2025 at 06:18:14PM +, Shameerali Kolothum Thodi wrote:
> > So even if you invent an iommu ID we cannot accept it as a handle to
> > create viommu in iommufd.
>
> Creating the vIOMMU only happens when the user does a cold/hot plug of
> a VFIO device. At that time Qemu checks w
+Michal
On 6/2/25 19:06, Daniel P. Berrangé wrote:
On Thu, Feb 06, 2025 at 06:49:38PM +0100, Philippe Mathieu-Daudé wrote:
On 6/2/25 18:12, Daniel P. Berrangé wrote:
On Thu, Feb 06, 2025 at 04:04:20PM +0100, Philippe Mathieu-Daudé wrote:
On 6/2/25 15:31, Daniel P. Berrangé wrote:
On Thu, Feb
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 127 +
1 file changed, 60 insertions(+), 67 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b0bc5e4503f..b2b9b4f6e39 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
In preparation for generalizing the custom CSR functionality,
make the test return bool instead of int. Make the insertion_test
optional, too.
Signed-off-by: Paolo Bonzini
---
target/riscv/th_csr.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/target/riscv/th_c
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 65 --
2 files changed, 25 insertions(+), 41 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index bfe1455254c..398cb4f583c 100644
--- a/targ
Hi Alastair,
the subject is a slightly underhanded description, in that what I really
wanted to achieve was removing RISC-V's use of .instance_post_init; that's
because RISC-V operate with an opposite conception of .instance_post_init
compared to everyone else: RISC-V wants to register properties
Profile CPUs reuse the instance_init function for bare CPUs; make them
proper subclasses instead. Enabling a profile is now done based on the
RISCVCPUDef struct: even though there is room for only one in RISCVCPUDef,
subclasses check that the parent class's profile is enabled through the
parent pr
Start putting all the CPU definitions in a struct. Later this will replace
instance_init functions with declarative code, for now just remove the
ugly cast of class_data.
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.h | 4
target/riscv/cpu.c | 26 +-
2 files c
Prepare for adding more fields to RISCVCPUDef and reading them in
riscv_cpu_init: instead of storing the misa_mxl_max field in
RISCVCPUClass, ensure that there's always a valid RISCVCPUDef struct
and go through it.
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.h | 2 +-
hw/riscv/boo
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 55 ++
1 file changed, 17 insertions(+), 38 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 253ed5132c4..5c6ba511ef2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 67 --
1 file changed, 23 insertions(+), 44 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7ebf007c129..b0a28c065e1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
They are never accessed together with the rest of the CPUConfig data,
so just store it in the ArchCPU struct.
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.h| 16 +
target/riscv/cpu_cfg.h| 16 -
target/riscv/cpu_cfg_fields.h.inc | 8 -
hw/risc
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 40 +---
1 file changed, 17 insertions(+), 23 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b47ca531503..a8aaa65f56e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -67
Unlike other uses of .instance_post_init, accel_cpu_instance_init()
*registers* properties, and therefore must be run before
device_post_init() which sets them to their values from -global.
In order to move all registration of properties to .instance_init,
call accel_cpu_instance_init() at the end
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 75 --
2 files changed, 22 insertions(+), 54 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index d56b067bf24..bfe1455254c 100644
--- a/targ
Allow using RISCVCPUDef to replicate all the logic of custom .instance_init
functions. To simulate inheritance, merge the child's RISCVCPUDef with
the parent and then finally move it to the CPUState at the end of
TYPE_RISCV_CPU's own instance_init function.
STRUCT_FIELD is introduced here because
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 61 +-
1 file changed, 28 insertions(+), 33 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6c898cef625..b0bc5e4503f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
Since all TYPE_RISCV_CPU subclasses support a class_data of type
RISCVCPUDef, process it even before calling the .class_init function
for the subclasses.
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 7 ---
target/riscv/tcg/tcg-cpu.c | 9 +
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5c6ba511ef2..8fa05912698 100644
--- a/target/riscv/cpu.c
+++ b/target/ris
Start from the top of the hierarchy: dynamic and vendor CPUs are just
markers, whereas bare CPUs can have their instance_init function
replaced by RISCVCPUDef.
The only difference is that the maximum supported SATP mode has to
be specified separately for 32-bit and 64-bit modes.
Signed-off-by: Pa
To support merging a subclass's RISCVCPUDef into the superclass, a list
of all the CPU features is needed. Put them into a header file that
can be included multiple times, expanding the macros BOOL_FIELD and
TYPE_FIELD to different operations.
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu_c
Signed-off-by: Paolo Bonzini
---
target/riscv/cpu.c | 75 ++
1 file changed, 35 insertions(+), 40 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b2b9b4f6e39..7ebf007c129 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
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