From: Yu-Ming Chang
We only check RVC to allow 16-bit aligned return addreses. This will
cause issues when only ext_zca is enabled without RVC: 16-bit
instructions are allowed, but 16-bit aligned return address are not.
We should also check ext_zca to permit 16-bit aligned return addresses.
Sign
On 2025/02/03 7:08, Dmitry Osipenko wrote:
On 1/27/25 07:57, Akihiko Odaki wrote:
On 2025/01/27 3:06, Dmitry Osipenko wrote:
On 1/21/25 07:26, Akihiko Odaki wrote:
...
I feel the dependency information for virglrenderer and Mesa are more
suited for the Mesa documentation as they are not specif
Hi Philippe
> From: Philippe Mathieu-Daudé
> Sent: Thursday, January 30, 2025 11:03 PM
> To: qemu-...@nongnu.org; qemu-devel@nongnu.org
> Cc: Cédric Le Goater ; Peter Maydell
> ; Steven Lee ; Troy
> Lee ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley
> Subject: Re: [PATCH 2/2] hw/arm/aspeed_ast27x
On 2025/02/03 8:21, Dmitry Osipenko wrote:
From: Alex Bennée
This attempts to tidy up the VirtIO GPU documentation to make the list
of requirements clearer. There are still a lot of moving parts and the
distros have some catching up to do before this is all handled
automatically.
Signed-off-by
On 2025/02/03 8:21, Dmitry Osipenko wrote:
Extend virtio-gpu documentation with a link to the Mesa VirGL
documentation.
Suggested-by: Akihiko Odaki
Signed-off-by: Dmitry Osipenko
---
docs/system/devices/virtio-gpu.rst | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/doc
On 2025/02/03 8:21, Dmitry Osipenko wrote:
Change virtio-gpu Venus link, pointing it at the Mesa Venus
documentation instead of the protocol. The Mesa doc provides more
information and also has a link to the protocol.
Suggested-by: Akihiko Odaki
Signed-off-by: Dmitry Osipenko
Reviewed-by: Ak
For instance, QEMUs newer than b6ecc63c569bb88c0fcadf79fb92bf4b88aefea8
would silently treat this akin to an unmapped page (as required by the
RISC-V spec, admittedly). However, not all hardware platforms do (e.g.
CVA6) which leads to an apparent QEMU bug.
Instead, log a guest error so that in fut
On 1/2/25 16:28, Bernhard Beschow wrote:
Am 30. Januar 2025 23:05:53 UTC schrieb "Philippe Mathieu-Daudé"
:
Cc'ing AMD folks
Hi Bernhard,
TL;DR; can't you use the PCF8574 which is a more complete model of I/O
expander? (See hw/gpio/pcf8574.c)
If it is software-compatible then I could use
On 2/1/25 08:39, Peter Maydell wrote:
The negation steps in FCADD must honour FPCR.AH's "don't change the
sign of a NaN" semantics. Implement this in the same way we did for
the base ASIMD FCADD, by encoding FPCR.AH into the SIMD data field
passed to the helper and using that to decide whether t
Le 01/02/2025 à 20:36, Michael Tokarev a écrit :
17.01.2025 17:05, Laurent Vivier wrote:
CC: qemu-stable and qemu-trivial.
On 17/01/2025 12:17, Laurent Vivier wrote:
announce_self that sends a RARP packet after migration
or with announce_self QMP/HMP command doesn't work with
vhost because of
On 2.02.2025 03:06, Dr. David Alan Gilbert wrote:
* Maciej S. Szmigiero (m...@maciej.szmigiero.name) wrote:
From: "Maciej S. Szmigiero"
postcopy_ram_listen_thread() is a free running thread, so it needs to
take BQL around function calls to migration methods requiring BQL.
qemu_loadvm_state_ma
On 1/31/25 17:14, Cédric Le Goater wrote:
> Hello Tomita,
>
> On 1/24/25 20:12, Tomita Moeko wrote:
>> The actual IO BAR4 write quirk in vfio_probe_igd_bar4_quirk() was
>> removed in previous change, leaving the function not matching its name,
>> so move it into the newly introduced vfio_config_qu
get_signal.h
@@ -4,5 +4,6 @@
#include "../generic/signal.h"
#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
+#undef TARGET_SA_RESTORER
#endif /* RISCV_TARGET_SIGNAL_H */
---
base-commit: 6fccaa2fba391815308a746d68f7fa197bc93586
change-id: 20250202-riscv-sa-restorer-edd3dfa7790f
Best regards,
--
Thomas Weißschuh
This patchset adds DRM native context support to VirtIO-GPU on Qemu.
Contarary to Virgl and Venus contexts that mediates high level GFX APIs,
DRM native context [1] mediates lower level kernel driver UAPI, which
reflects in a less CPU overhead and less/simpler code needed to support it.
DRM contex
From: Pierre-Eric Pelloux-Prayer
If EGL is used, we can rely on dmabuf to import textures without
doing copies.
To get this working on X11, we use the existing SDL hint:
SDL_HINT_VIDEO_X11_FORCE_EGL (because dmabuf can't be used with GLX).
Reviewed-by: Akihiko Odaki
Acked-by: Michael S. Tsirki
Change virtio-gpu Venus link, pointing it at the Mesa Venus
documentation instead of the protocol. The Mesa doc provides more
information and also has a link to the protocol.
Suggested-by: Akihiko Odaki
Signed-off-by: Dmitry Osipenko
---
docs/system/devices/virtio-gpu.rst | 2 +-
1 file changed
SDL API changes GL context to a newly created GL context, which differs
from other GL providers that don't switch context. Change SDL backend to
restore the original GL context. This allows Qemu's virtio-gpu to support
new virglrenderer async-fencing feature for Virgl contexts, otherwise
virglrende
Extend virtio-gpu documentation with a link to the Mesa VirGL
documentation.
Suggested-by: Akihiko Odaki
Signed-off-by: Dmitry Osipenko
---
docs/system/devices/virtio-gpu.rst | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/system/devices/virtio-gpu.rst
b/docs/system/
Support asynchronous fencing feature of virglrenderer. It allows Qemu to
handle fence as soon as it's signalled instead of periodically polling
the fence status. This feature is required for enabling DRM context
support in Qemu because legacy fencing mode isn't supported for DRM
contexts in virglre
Display refreshment is invoked by a timer and it erroneously disables
the active scanout if it happens to be invoked after scanout has been
enabled. This offending scanout-disable race condition with a timer
can be easily hit when Qemu runs with a disabled vsync by using SDL or
GTK displays (with v
Add support for DRM native contexts to VirtIO-GPU. DRM context is enabled
using a new virtio-gpu-gl device option "drm_native_context=on".
Unlike Virgl and Venus contexts that operate on application API level,
DRM native contexts work on a kernel UAPI level. This lower level results
in a lightweig
Display refreshment is invoked by a timer and it erroneously disables
the active scanout if it happens to be invoked after scanout has been
enabled. This offending scanout-disable race condition with a timer
can be easily hit when Qemu runs with a disabled vsync by using SDL or
GTK displays (with v
From: Alex Bennée
This attempts to tidy up the VirtIO GPU documentation to make the list
of requirements clearer. There are still a lot of moving parts and the
distros have some catching up to do before this is all handled
automatically.
Signed-off-by: Alex Bennée
Cc: Sergio Lopez Pascual
Sign
On Thu, Dec 5, 2024 at 9:36 PM Rajnesh Kanwal wrote:
>
> CTR entries are accessed using ctrsource, ctrtarget and ctrdata
> registers using smcsrind/sscsrind extension. This commits extends
> the csrind extension to support CTR registers.
>
> ctrsource is accessible through xireg CSR, ctrtarget is
On Thu, Dec 5, 2024 at 9:36 PM Rajnesh Kanwal wrote:
>
> Add a subsection to machine.c to migrate CTR CSR state
>
> Signed-off-by: Rajnesh Kanwal
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/machine.c | 25 +
> 1 file changed, 25 insertions(+)
>
> diff
On Thu, Dec 5, 2024 at 9:35 PM Rajnesh Kanwal wrote:
>
> This commit adds logic to records CTR entries of different types
> and adds required hooks in TCG and interrupt/Exception logic to
> record events.
>
> This commit also adds support to invoke freeze CTR logic for breakpoint
> exceptions and
On Thu, Dec 5, 2024 at 9:35 PM Rajnesh Kanwal wrote:
>
> CTR extension adds a new instruction sctrclr to quickly
> clear the recorded entries buffer.
>
> Signed-off-by: Rajnesh Kanwal
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 1 +
> target/
v1: 20250128004254.33442-1-richard.hender...@linaro.org
For v2, immediately disable 64-on-32 TCG.
I *suspect* that we should disable 64-on-32 for *all* accelerators.
The idea that an i686 binary on an x86_64 host may be used to spawn
an x86_64 guest via kvm is silly and a bit more than niche.
Sim
Provide out-of-line versions of some of the qemu/plugin.h API.
These will be referenced with --enable-plugin, but CONFIG_TCG
is disabled for a specific target.
Signed-off-by: Richard Henderson
---
plugins/stubs.c | 49 +
plugins/meson.build | 5 ++
Hack around mips32 host allowing kvm acceleration
of mips64 guest, but tcg is disabled.
Signed-off-by: Richard Henderson
---
target/mips/tcg/meson.build| 4 ++--
target/mips/tcg/system/meson.build | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/mips/tcg/
No need to expand this function inline.
Unexport qemu_plugin_opts to match.
Signed-off-by: Richard Henderson
---
include/qemu/plugin.h | 9 +
plugins/loader.c | 7 ++-
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h
in
This is now prohibited in configuration.
Signed-off-by: Richard Henderson
---
include/qemu/atomic.h | 18 +++--
include/tcg/oversized-guest.h | 23 --
accel/tcg/cputlb.c | 7 ---
accel/tcg/tcg-all.c | 9 -
target/
The fact that this is only enabled for x86 probably means it
was done incorrectly. Certainly the set of files selected to
go into the module is woefully incomplete. Drop it for now.
Signed-off-by: Richard Henderson
---
accel/tcg/meson.build | 11 ---
meson.build | 18 +---
Add tcg_allowed, qmp_x_query_jit, qmp_x_query_opcount.
These are referenced when CONFIG_TCG is enabled globally,
but not for a specific target.
Signed-off-by: Richard Henderson
---
accel/stubs/tcg-stub.c | 24
1 file changed, 24 insertions(+)
diff --git a/accel/stubs/tc
This is now handled by the configs/targets/*.mak fragment.
Signed-off-by: Richard Henderson
---
target/alpha/cpu-param.h | 2 --
target/arm/cpu-param.h| 2 --
target/avr/cpu-param.h| 1 -
target/hexagon/cpu-param.h| 1 -
target/hppa/cpu-param.h | 2 --
target/i386/
We deprecated i686 system mode support for qemu 8.0. However, to
make real cleanups to TCG we need to deprecate all 32-bit hosts.
Signed-off-by: Richard Henderson
---
docs/about/deprecated.rst | 7 +++
meson.build | 6 ++
2 files changed, 9 insertions(+), 4 deletions(-)
d
These are not called so frequently as to be
performance sensitive.
Signed-off-by: Richard Henderson
---
include/tcg/perf.h | 23 ---
tcg/perf-stubs.c | 26 ++
tcg/meson.build| 2 ++
3 files changed, 28 insertions(+), 23 deletions(-)
create mode
For system mode, we can rarely support the amount of RAM that
the guest requires. Emulation is restricted to round-robin
mode, which solves many of the atomicity issues, but not those
associated with virtio. In any case, round-robin does nothing
to help the speed of emulation.
For user mode, most
Configuration of 64-bit host on 32-bit guest will shortly
be denied. Use a 32-bit guest instead.
Signed-off-by: Richard Henderson
---
.gitlab-ci.d/crossbuilds.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml
inde
Rather than unconditional linkage via system_ss, conditinally
include the static library via specific_ss. This will elide
the code when CONFIG_TCG is disabled for a specific target.
Signed-off-by: Richard Henderson
---
tcg/meson.build | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
Use CONFIG_TCG as a project-wide flag to indicate that TCG is enabled
for *some* target. Use CONFIG_TCG_TARGET to indicate that TCG is
enabled for a specific target.
Within a specific compilation unit, we can remap CONFIG_TCG based on
CONFIG_TCG_TARGET. This allows us to avoid changes to the bul
Define TARGET_LONG_BITS in each target's configure fragment.
Do this without removing the define in target/*/cpu-param.h
so that errors are caught like so:
In file included from .../src/include/exec/cpu-defs.h:26,
from ../src/target/hppa/cpu.h:24,
from ../src/linu
Hi all, my first contribution. I checked code style, patch submission
rules and did a manual test (details on request)
Synopsis:
It's a corner case, where a segfault occurs when logging Sparc CPU state
in a partially initialized state.
No related bug report.
Open to harsh criticism ;-)
Rega
On 1/27/25 07:57, Akihiko Odaki wrote:
> On 2025/01/27 3:06, Dmitry Osipenko wrote:
>> On 1/21/25 07:26, Akihiko Odaki wrote:
>> ...
> I feel the dependency information for virglrenderer and Mesa are more
> suited for the Mesa documentation as they are not specific to QEMU and
> potenti
On 1/31/25 20:19, Dmitry Osipenko wrote:
> On 1/29/25 04:18, Gurchetan Singh wrote:
>> On Sun, Jan 26, 2025 at 12:14 PM Dmitry Osipenko <
>> dmitry.osipe...@collabora.com> wrote:
>>
>>> From: Alex Bennée
>>>
>>> This attempts to tidy up the VirtIO GPU documentation to make the list
>>> of requirem
Hey Ani!
On 28.01.25 22:31, Ani Sinha wrote:
VM firmware update is a mechanism where the virtual machines can use their
preferred and trusted firmware image in their execution environment without
having to depend on a untrusted party to provide the firmware bundle. This is
particularly useful fo
On 1/31/25 13:44, Artyom Tarasenko wrote:
fake access to
PCR Performance Control Register
and
PIC Performance Instrumentation Counter.
Ignore writes in privileged mode, and return 0 on reads.
This allows booting Tribblix, MilaX and v9os under Niagara target.
Signed-off-by: Artyom Tarasenko
--
On 2/2/25 13:46, Richard Henderson wrote:
On 1/31/25 13:44, Artyom Tarasenko wrote:
fake access to
PCR Performance Control Register
and
PIC Performance Instrumentation Counter.
Ignore writes in privileged mode, and return 0 on reads.
This allows booting Tribblix, MilaX and v9os under Niagara t
On 2/2/25 2:15 AM, julia wrote:
For instance, QEMUs newer than b6ecc63c569bb88c0fcadf79fb92bf4b88aefea8
would silently treat this akin to an unmapped page (as required by the
RISC-V spec, admittedly). However, not all hardware platforms do (e.g.
CVA6) which leads to an apparent QEMU bug.
Inst
On Thu, Jan 16, 2025 at 1:32 PM ~yuming wrote:
>
> From: Yu-Ming Chang
>
> Only check misa.C will cause issues when ext_zca is enabled without
> misa.C being set. For example, only enable ext_zce.
Thanks for the patch!
I'm not clear what the problem is and what this commit fixes. Do you
mind up
On Tue, 2025-01-28 at 09:03 +0100, Klaus Jensen wrote:
> On Jan 15 02:16, Wilfred Mallawa wrote:
> > On Fri, 2025-01-10 at 10:04 +0100, Klaus Jensen wrote:
> > > On Jan 7 15:29, Wilfred Mallawa via wrote:
> > > > This header contains the transport encoding for an SPDM message
> > > > that
> > > >
Print out error messages when virgl fence creation fails to aid debugging
of the fence-related bugs.
Reviewed-by: Akihiko Odaki
Acked-by: Michael S. Tsirkin
Tested-by: Alex Bennée
Signed-off-by: Dmitry Osipenko
---
hw/display/virtio-gpu-virgl.c | 13 -
1 file changed, 12 insertion
So far there isn't way to test host kernel vhost-scsi event queue path,
because VIRTIO_SCSI_F_HOTPLUG isn't supported by QEMU.
virtio-scsi.c and vhost-user-scsi.c already support VIRTIO_SCSI_F_HOTPLUG
as property "hotplug".
Add support to vhost-scsi.c to help evaluate and test event queue.
To te
On Tue, Jan 28, 2025 at 4:05 PM Alistair Francis wrote:
>
> Bin Meng has been a long time contributor and maintainer for QEMU RISC-V
> and has been very beneficial to the RISC-V ecosystem.
>
> Unfortunately his email has started to bounce so this patch is removing
> them from MAINTAINERS. If in th
On Thu, Dec 5, 2024 at 9:36 PM Rajnesh Kanwal wrote:
>
> This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and
> sctrdepth CSRs handling.
>
> Signed-off-by: Rajnesh Kanwal
Acked-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 5 ++
> target/riscv/cpu_cfg.h | 2 +
+ Troy
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On 2/2/25 19:14, Henk van der Laak (LaakSoft) via wrote:
Hi all, my first contribution. I checked code style, patch submission rules and did a
manual test (details on request)
Synopsis:
It's a corner case, where a segfault occurs when logging Sparc CPU state in a partially
initialized state.
On 2/2/25 20:03, Henk van der Laak (LaakSoft) wrote:
On 03/02/2025 04:45, Richard Henderson wrote:
On 2/2/25 19:14, Henk van der Laak (LaakSoft) via wrote:
Hi all, my first contribution. I checked code style, patch submission rules and did a
manual test (details on request)
Synopsis:
It's a c
At Sun, 02/02/2025 at 18:09 +0100, Philippe Mathieu-Daudé writes:
> No clue about compatibility. If you unfortunately need to add it,
> then please address my comments in the next version.
TCA6416 is _way_ more complex device than PCF8574. Basically PCF8574 is
shift register directly connected to I
> This happens because 'pte' is a 'target_ulong' type that, for riscv32, will be
> interpreted as uint32_t while the FMT being used is PRIx64.
>
> You can fix it by using TARGET_FMT_lx instead of PRIx64:
>
I've sent a follow-up patch fixing these build errors, it builds on 32 & 64 bit
on my syste
Hi Philippe,
> From: Philippe Mathieu-Daudé
> Sent: Thursday, January 30, 2025 11:14 PM
> To: Jamin Lin ; Cédric Le Goater ;
> Peter Maydell ; Andrew Jeffery
> ; Joel Stanley ; Alistair
> Francis ; Cleber Rosa ; Wainer
> dos Santos Moschetta ; Beraldo Leal
> ; open list:ASPEED BMCs ; open
> list:
Hi Philippe,
> From: Jamin Lin
> Sent: Monday, February 3, 2025 3:29 PM
> To: Philippe Mathieu-Daudé ; Cédric Le Goater
> ; Peter Maydell ; Andrew Jeffery
> ; Joel Stanley ; Alistair
> Francis ; Cleber Rosa ; Wainer
> dos Santos Moschetta ; Beraldo Leal
> ; open list:ASPEED BMCs ; open
> list:All
* Maciej S. Szmigiero (m...@maciej.szmigiero.name) wrote:
> On 2.02.2025 03:06, Dr. David Alan Gilbert wrote:
> > * Maciej S. Szmigiero (m...@maciej.szmigiero.name) wrote:
> > > From: "Maciej S. Szmigiero"
> > >
> > > postcopy_ram_listen_thread() is a free running thread, so it needs to
> > > tak
On 1/27/25 19:17, Alex Bennée wrote:
...
> I'm still seeing corruption with -display gtk,gl=on on my x86 system
> BTW. I would like to understand if that is a problem with QEMU, GTK or
> something else in the stack before we merge.
I reproduced the display mirroring/corruption issue and bisected i
On 2/1/2025 2:27 AM, Paolo Bonzini wrote:
On Fri, Jan 24, 2025 at 2:40 PM Xiaoyao Li wrote:
For TDX guest, the phys_bits is not configurable and can only be
host/native value.
Validate phys_bits inside tdx_check_features().
Hi Xiaoyao,
to avoid
qemu-kvm: TDX requires guest CPU physical bi
On 2/1/25 08:39, Peter Maydell wrote:
The Armv8.7 FEAT_AFP feature defines three new control bits in
the FPCR:
* FPCR.AH: "alternate floating point mode"; this changes floating
point behaviour in a variety of ways, including:
- the sign of a default NaN is 1, not 0
- if FPCR.FZ is
On 2/1/25 08:39, Peter Maydell wrote:
For the x86 and the Arm FEAT_AFP semantics, we need to be able to
tell the target code that the FPU operation has used an input
denormal. Implement this; when it happens we set the new
float_flag_denormal_input_used.
Note that we only set this when an input
On 2/1/25 08:39, Peter Maydell wrote:
Currently we handle flushing of output denormals in uncanon_normal
always before we deal with rounding. This works for architectures
that detect tininess before rounding, but is usually not the right
place when the architecture detects tininess after roundin
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