Add me as the maintainer for the ivshmem-flat device.
Signed-off-by: Gustavo Romero
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2101b51217..461f98525b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2785,6 +2785,13 @@ F: hw/hyperv/hv-
On Thu, 2024-12-19 at 17:39 +, Daniel P. Berrangé wrote:
> On Thu, Dec 12, 2024 at 12:05:28PM -0500, James Bottomley wrote:
> > The Microsoft Simulator (mssim) is the reference emulation platform
> > for the TCG TPM 2.0 specification.
> >
> > https://github.com/Microsoft/ms-tpm-20-ref.git
> >
On Mon, Jan 6, 2025 at 3:46 PM wrote:
>
> From: Frank Chang
>
> This patchset added support for Smrnmi Extension in RISC-V.
>
> There are four new CSRs and one new instruction added to allow NMI to be
> resumable in RISC-V, which are:
>
> ==
On 1/6/25 13:49, Philippe Mathieu-Daudé wrote:
diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h
index a6c7cdba5d..6734fd63e7 100644
--- a/tcg/ppc/tcg-target-has.h
+++ b/tcg/ppc/tcg-target-has.h
@@ -16,13 +16,14 @@
#define have_altivec (cpuinfo & CPUINFO_ALTIVEC)
#define have
On 1/6/25 13:58, Philippe Mathieu-Daudé wrote:
On 2/1/25 19:06, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h | 16 ++---
tcg/aarch64/tcg-target-has.h | 12 ++--
tcg/arm/tcg-target-has.h | 8 +--
tcg/i386/tcg-target-has.h
Add logic cpu index output parameter for function cpu_by_arch_id,
CPUState::cpu_index is logic cpu slot index for possible_cpus.
However it is logic cpu index with LoongsonIPICommonState::IPICore,
here hide access for CPUState::cpu_index directly, it comes from
function cpu_by_arch_id().
Signed-of
Add realize interface for loongar ipi device.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 19 +++
include/hw/intc/loongarch_ipi.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index 2ae1a42c46..4e2f9acd
There is arch_id and CPUState pointer in IPICore object, with function
cpu_by_arch_id() it can be implemented by parsing IPICore array.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 36 +++-
1 file changed, 11 insertions(+), 25 deletions(-)
diff --git a/h
Since cpu number can be acquired from possible_cpu_arch_ids(),
num-cpu property is not necessary. Here remove num-cpu property
for object iTYPE_LOONGARCH_IPI object.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 5 -
hw/loongarch/virt.c | 1 -
2 files changed, 6 deletions(-)
dif
With mips64 loongson ipi, num_cpu property is used, with loongarch
ipi, num_cpu can be acquired from possible_cpu_arch_ids.
Here remove num_cpu setting from loongson_ipi_common, and this piece
of code is put into loongson ipi and loongarch ipi.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.
With mips64 loongson ipi, num_cpu property is used, with loongarch
ipi, num_cpu can be acquired from possible_cpu_arch_ids.
Here remove property num_cpu from loongson_ipi_common, and this piece
of code is put into loongson ipi and loongarch ipi.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi
Property num_cpu is not necessary, it can be acquired from function
possible_cpu_arch_ids(), also adding arch_id and CPUState pointer in
IPICore object, so that IPICore object can be parsed from physical
cpu id.
---
v2 ... v3:
1. Remove TYPE_HOTPLUG_HANDLER interface support
2. Remove nu
Supported CPU number can be acquired from function
possible_cpu_arch_ids(), cpu-num property is not necessary.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.c | 13 -
include/hw/intc/loongson_ipi_common.h | 2 ++
2 files changed, 10 insertions(+), 5 deletions(-)
d
On 6/1/25 21:33, Daniel Henrique Barboza wrote:
On 1/6/25 5:02 PM, Philippe Mathieu-Daudé wrote:
Only iterate over HVF vCPUs when running HVF specific code.
Signed-off-by: Philippe Mathieu-Daudé
---
include/system/hvf_int.h | 4
accel/hvf/hvf-accel-ops.c | 9 +
target/arm/h
On 2/1/25 19:06, Richard Henderson wrote:
Test each vector type, not just lumping them all together.
Add tests for I32 (always true) and I64 (64-bit hosts).
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 66 ---
1 file changed, 43 inserti
On 2/1/25 19:06, Richard Henderson wrote:
Begin to rely on TCGOp.type to discriminate operations,
rather than two different opcodes. Convert mov first.
Introduce TCG_OPF_INT in order to keep opcode dumps the same.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 4 ++-
On 2/1/25 19:06, Richard Henderson wrote:
For TCI, we're losing type information from the interpreter.
Limit the opcodes to the host register size; on 64-bit host
it's just as easy to reconstruct 64-bit operands for normal add/sub.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h
Perhaps add in the commit msg something like "it's only being used in
bsd-user and linux-user code"
On 1/6/25 5:02 PM, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Daniel Henrique Barboza
include/hw/core/cpu.h | 3 +++
1 file changed, 3 insertions
On Mon, Jan 06, 2025 at 04:24:53PM -0300, Fabiano Rosas wrote:
> Here's the fix for the pre-existing issue in the script:
For this patch:
>
> -- 8< --
> From 5bcad03aad85556a7b72f79d3574e246a99432c3 Mon Sep 17 00:00:00 2001
> From: Fabiano Rosas
> Date: Mon, 6 Jan 2025 15:05:31 -0300
> Subject:
Reviewed-by: Glenn Miles
On Fri, 2024-12-13 at 13:07 -0600, Richard Henderson wrote:
> Signed-off-by: Richard Henderson
> ---
> hw/gpio/imx_gpio.c | 2 +-
> hw/gpio/npcm7xx_gpio.c | 2 +-
> hw/gpio/omap_gpio.c | 2 +-
> hw/gpio/pca9552.c| 2 +-
> hw/gpio/pca9554.c|
On 2/1/25 19:06, Richard Henderson wrote:
Pass a type parameter to the macros; this is unused with these opcodes,
but will be used with others, so keep it for uniformity.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 24 +++---
tcg/aarch64/tcg-target-has.h |
Hi Richard,
On 2/1/25 19:06, Richard Henderson wrote:
Pass a type parameter to the macros; this is unused with these opcodes,
but will be used with others, so keep it for uniformity.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 24 +++---
tcg/aarch64/tcg-target-h
On 2/1/25 19:06, Richard Henderson wrote:
Only the integer opcodes handled here; the vector rotates
are left for a future patch, as they are split by immediate,
scalar, and vector shift count.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 8
tcg/aarch64/tc
On 2/1/25 19:06, Richard Henderson wrote:
Merge not only the i32 and i64 alternatives, but all
of the different input bit sizes as well. For each
tcg target they are all the same.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 10 +-
tcg/aarch64/tcg-target-h
On 2/1/25 19:06, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 16 ++---
tcg/aarch64/tcg-target-has.h | 12 ++--
tcg/arm/tcg-target-has.h | 8 +--
tcg/i386/tcg-target-has.h| 12 ++--
tcg/loongarch64/tcg-target-has.
Hello,
On 12/10/24 04:04, Nicholas Piggin wrote:
This series makes a bunch of fixes and improvements to the HOMER and
OCC unit models for powernv. It gets OPAL OCC code happier again,
Nice. I had similar changes exposing pstates and sensors for QEMU.
I am glad this is now possible.
but requi
On 2/1/25 19:06, Richard Henderson wrote:
Return C_NotImplemented instead of asserting for opcodes
not implemented by the backend.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 12 ++--
tcg/aarch64/tcg-target.c.inc | 2 +-
tcg/arm/tcg-target.c.inc
On 2/1/25 19:06, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 9 -
tcg/optimize.c | 20 +---
tcg/tcg-op.c | 10 +-
tcg/tcg.c| 19 +++
On Tue, Jan 7, 2025 at 3:38 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This new version is a re-sent of v1, rebased on top of
> alistair/riscv-to-apply.next, with acks/r-bs added.
>
> No other changes made.
>
> Changes from v1:
> - rebased on top of alistair/riscv-to-apply.next
> - v1 link:
>
On Tue, Jan 7, 2025 at 3:54 AM Andrea Bolognani wrote:
>
> On Mon, Jan 06, 2025 at 11:57:58AM +, Daniel P. Berrangé wrote:
> > On Mon, Jan 06, 2025 at 11:47:00AM +, Peter Maydell wrote:
> > > On Mon, 6 Jan 2025 at 01:29, Alistair Francis
> > > wrote:
> > > > We didn't get an answer to th
On Mon, Jan 6, 2025 at 8:25 PM wrote:
>
> From: Alexey Baturo
>
> Hi,
>
> Rebased against Alistair's riscv-to-apply.next
>
> Thanks
>
> [v14]:
> Rebased and addressed Alistair's comments on code style.
>
>
> [v13]:
> Rebased and addressed Daniel's comments about the return type of the helper.
>
>
I tested this series of patches with virtio-net regression
tests,everything works fine.
Tested-by: Lei Yang
On Mon, Jan 6, 2025 at 11:57 PM Jonah Palmer wrote:
>
> Commit a0d7215e33 ("vhost-vdpa: do not cleanup the vdpa/vhost-net
> structures if peer nic is present") effectively delayed the bac
I tested this series of patches with virtio-net regression tests,
everything works fine.
Tested-by: Lei Yang
On Sat, Jan 4, 2025 at 4:05 PM Akihiko Odaki wrote:
>
> g_spawn_sync() gives an informative message if it fails to execute
> the script instead of reporting exiting status 1.
>
> g_spawn
On Mon, Jan 6, 2025 at 3:47 PM wrote:
>
> From: Tommy Wu
>
> Because the RNMI interrupt trap handler address is implementation defined.
> We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property
> of the harts. It’s very easy for users to set the address based on their
> exp
On Mon, Jan 6, 2025 at 3:46 PM wrote:
>
> From: Tommy Wu
>
> This adds the properties for ISA extension Smrnmi.
>
> Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set
> mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all
> interrupts will be disabled. Since our curr
On Mon, 6 Jan 2025 at 01:29, Alistair Francis wrote:
>
> On Fri, Jan 3, 2025 at 2:04 AM Andrea Bolognani wrote:
> >
> > On Tue, Dec 03, 2024 at 10:47:02AM +0100, Andrea Bolognani wrote:
> > > Currently the script won't generate a configuration file that
> > > sets up qemu-user-riscv32 on riscv64,
On Mon, 6 Jan 2025 at 11:58, Daniel P. Berrangé wrote:
>
> On Mon, Jan 06, 2025 at 11:47:00AM +, Peter Maydell wrote:
> > On Mon, 6 Jan 2025 at 01:29, Alistair Francis wrote:
> > >
> > > On Fri, Jan 3, 2025 at 2:04 AM Andrea Bolognani
> > > wrote:
> > > >
> > > > On Tue, Dec 03, 2024 at 10:
Il gio 2 gen 2025, 18:04 Philippe Mathieu-Daudé ha
scritto:
> > +unsafe {
> > +bindings::device_class_set_legacy_reset(dc,
> Some(rust_reset_fn::));
>
> Pre-existing, but since it appears on this patch, Rust device models
> should not implement this legacy interface. I
On Mon, Jan 06, 2025 at 11:47:00AM +, Peter Maydell wrote:
> On Mon, 6 Jan 2025 at 01:29, Alistair Francis wrote:
> >
> > On Fri, Jan 3, 2025 at 2:04 AM Andrea Bolognani wrote:
> > >
> > > On Tue, Dec 03, 2024 at 10:47:02AM +0100, Andrea Bolognani wrote:
> > > > Currently the script won't gen
On 1/6/25 3:23 PM, Philippe Mathieu-Daudé wrote:
When running on a heterogeneous setup, the CPU_FOREACH()
macro in arm_get_cpu_by_id() iterates on all vCPUs,
regardless they are ARM or not. Check the CPU class type
and skip the non-ARM instances.
Signed-off-by: Philippe Mathieu-Daudé
---
R
Only iterate over HVF vCPUs when running HVF specific code.
Signed-off-by: Philippe Mathieu-Daudé
---
include/system/hvf_int.h | 4
accel/hvf/hvf-accel-ops.c | 9 +
target/arm/hvf/hvf.c | 4 ++--
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/include/system/hv
Only iterate over KVM vCPUs when running KVM specific code.
Signed-off-by: Philippe Mathieu-Daudé
---
include/system/kvm_int.h | 3 +++
accel/kvm/kvm-all.c | 14 +++---
hw/i386/kvm/clock.c | 3 ++-
hw/intc/spapr_xive_kvm.c | 5 +++--
hw/intc/x
We can only run a single hardware accelerator at a time,
so add a generic hw_accel_get_cpus_queue() helper in
accel-system.c, a file common to all HW accelerators.
Register AccelOpsClass::get_cpus_queue() for each HW
accelerator. Add a generic CPU_FOREACH_HWACCEL() macro.
Signed-off-by: Philippe
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/core/cpu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index c3ca0babcb3..48d90f50a71 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -594,8 +594,11 @@ extern CPUTailQ c
Hi,
Currently we register all vCPUs to the global 'cpus_queue' queue,
however we can not discriminate per accelerator or per target
architecture (which might happen in a soon future).
This series tries to add an accelerator discriminator, so
accelerator specific code can iterate on its own vCPUs.
Dear QEMU community,
Below is a draft release schedule for QEMU 10.0. Please let me know if
you see issues with public holidays or other dates that would prevent
us from rolling this release in mid to late March.
2024-12-11 Beginning of development phase
2025-03-11 Soft feature freeze. Only bug fi
On Mon, Jan 06, 2025 at 11:57:58AM +, Daniel P. Berrangé wrote:
> On Mon, Jan 06, 2025 at 11:47:00AM +, Peter Maydell wrote:
> > On Mon, 6 Jan 2025 at 01:29, Alistair Francis wrote:
> > > We didn't get an answer to the issue of a CPU supporting RV32 and yet
> > > the kernel still calls QEM
When running on a heterogeneous setup, the CPU_FOREACH()
macro in arm_get_cpu_by_id() iterates on all vCPUs,
regardless they are ARM or not. Check the CPU class type
and skip the non-ARM instances.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/arm-powerctl.c | 6 --
1 file changed, 4
On Fri, 27 Dec 2024 at 10:55, Тигран Согомонян
wrote:
>
> 27/12/24 01:49, Alex Bennée пишет:
> > Tigran Sogomonian writes:
> >
> >> s->buswidth = nand_flash_ids[s->chip_id].width >> 3;
> >> <= 16 >> 3 <= 2.
> >> x <= s->ioaddr[offset] << (s->buswidth << 3)
> >> <= max_uint8_t << 16
> >> With x <<
From: Daniel P. Berrangé
Provide a way to report the process load average, via a new
'guest-get-load' command.
This is only implemented for POSIX platforms providing 'getloadavg'.
Example illustrated with qmp-shell:
(QEMU) guest-get-load
{
"return": {
"load15m": 1.546875,
"
From: Dehan Meng
Make sure the error log of fsfreeze hooks
when freeze/thaw/snapshot could be logged
to system logs if the default logfile of
qga can't be written or other situations
Signed-off-by: Dehan Meng
Reviewed-by: Yan Vugenfirer
Reviewed-by: Konstantin Kostiuk
Message-ID: <20241225083
The following changes since commit 9ee90cfc25747ab25c7da31a50f167fc5122e20e:
Merge tag 'qtest-20250102-pull-request' of https://gitlab.com/farosas/qemu
into staging (2025-01-03 09:14:11 -0500)
are available in the Git repository at:
https://github.com/kostyanf14/qemu.git tags/qga-pull-2025-
On 1/6/25 5:02 PM, Philippe Mathieu-Daudé wrote:
Only iterate over HVF vCPUs when running HVF specific code.
Signed-off-by: Philippe Mathieu-Daudé
---
include/system/hvf_int.h | 4
accel/hvf/hvf-accel-ops.c | 9 +
target/arm/hvf/hvf.c | 4 ++--
3 files changed, 11 ins
On 5/1/25 01:57, Richard Henderson wrote:
On 1/3/25 15:17, Philippe Mathieu-Daudé wrote:
No need to link capstone to targets which don't use it.
Signed-off-by: Philippe Mathieu-Daudé
---
disas/meson.build | 1 -
target/arm/meson.build | 1 +
target/i386/meson.build | 1 +
target
On 2/1/25 19:05, Richard Henderson wrote:
These defines are not required outside of tcg/tcg.c,
which includes tcg-target.c.inc before use.
Reduces the exported symbol set of tcg-target.h.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 13 -
tcg/arm/tcg-ta
On 2/1/25 19:05, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
tcg/tcg.c | 22 ++
2 files changed, 23 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 2/1/25 19:05, Richard Henderson wrote:
Avoid direct usage of TCG_TARGET_deposit_*_valid.
Signed-off-by: Richard Henderson
---
target/i386/tcg/emit.c.inc | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 2/1/25 19:05, Richard Henderson wrote:
This macro is unused.
Signed-off-by: Richard Henderson
---
target/i386/tcg/emit.c.inc | 2 --
1 file changed, 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 2/1/25 19:05, Richard Henderson wrote:
In addition, add empty files for mips, sparc64 and tci.
Make the include unconditional within tcg-opc.h.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h | 4 +---
tcg/aarch64/{tcg-target.opc.h => tcg-ta
On 2/1/25 19:05, Richard Henderson wrote:
Don't reference TCG_TARGET_MAYBE_vec in a public header.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 7 ---
tcg/tcg.c | 4
2 files changed, 4 insertions(+), 7 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 2/1/25 19:05, Richard Henderson wrote:
Now that tcg-target-opc.h.inc is unconditional,
we can move these out of the generic header.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 6 --
tcg/tci/tcg-target-opc.h.inc | 5 -
2 files changed, 4 insertions(+), 7 de
On 2/1/25 19:06, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
accel/tcg/internal-target.h | 1 +
tcg/aarch64/tcg-target-mo.h | 12
tcg/aarch64/tcg-target.h| 2 --
tcg/arm/tcg-target-mo.h | 13 +
tcg/arm/tcg-target.h
On Mon, 6 Jan 2025 at 18:23, Philippe Mathieu-Daudé wrote:
>
> When running on a heterogeneous setup, the CPU_FOREACH()
> macro in arm_get_cpu_by_id() iterates on all vCPUs,
> regardless they are ARM or not. Check the CPU class type
> and skip the non-ARM instances.
>
> Signed-off-by: Philippe Mat
On Fri, Jan 03, 2025 at 07:34:08PM -0300, Fabiano Rosas wrote:
> Fabiano Rosas writes:
>
> > Stefan Hajnoczi writes:
> >
> >> On Fri, 3 Jan 2025 at 13:32, Fabiano Rosas wrote:
> >>>
> >>> Thomas Huth writes:
> >>>
> >>> > On 20/12/2024 17.28, Peter Xu wrote:
> >>> >> On Thu, Dec 19, 2024 at 03
On Sat, Jan 04, 2025 at 12:28:14PM +0100, Phil Dennis-Jordan wrote:
> On Fri, 3 Jan 2025 at 16:16, Daniel P. Berrangé wrote:
>
> > On Fri, Jan 03, 2025 at 04:05:58PM +0100, Philippe Mathieu-Daudé wrote:
> > > As Daniel suggested [*]:
> > >
> > > > We should consider to rank HVF above TCG, on the
Peter Xu writes:
> On Fri, Jan 03, 2025 at 07:34:08PM -0300, Fabiano Rosas wrote:
>> Fabiano Rosas writes:
>>
>> > Stefan Hajnoczi writes:
>> >
>> >> On Fri, 3 Jan 2025 at 13:32, Fabiano Rosas wrote:
>> >>>
>> >>> Thomas Huth writes:
>> >>>
>> >>> > On 20/12/2024 17.28, Peter Xu wrote:
>> >>
Only iterate over TCG vCPUs when running TCG specific code.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/cputlb.c | 7 ---
accel/tcg/monitor.c | 3 ++-
accel/tcg/tb-maint.c | 7 ---
accel/tcg/tcg-accel-ops-rr.c | 10 +-
accel/tcg/tcg-accel-ops
We want the ability to iterate over vCPUs of a specific
accelerator. Introduce cpus_get_accel_cpus_queue() to
be used by accelerator common code, and expose the
get_cpus_queue() in AccelOpsClass, so each accelerator
can register its own queue of vCPUs.
Signed-off-by: Philippe Mathieu-Daudé
---
Use a specific vCPUs queue for our unique software accelerator.
Register the AccelOpsClass::get_cpus_queue() handler.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-accel-ops.h | 10 ++
accel/tcg/tcg-accel-ops.c | 8
2 files changed, 18 insertions(+)
diff --git a/acce
On 2/1/25 19:06, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 7 +++--
tcg/optimize.c | 12 -
tcg/tcg-op.c | 20 +++
tcg/tcg.c| 6 ++---
tcg/tci.c
On 1/3/2025 4:52 PM, Philippe Mathieu-Daudé wrote:
On 28/12/24 18:37, Philippe Mathieu-Daudé wrote:
On 19/12/24 12:01, Xiaoyao Li wrote:
There are duplicated code to setup the value of MSR_CORE_THREAD_COUNT.
Extract a common function for it.
Signed-off-by: Xiaoyao Li
---
Changes in v2:
- move
On 1/7/2025 12:31 PM, Xiaoyao Li wrote:
On 1/3/2025 4:52 PM, Philippe Mathieu-Daudé wrote:
On 28/12/24 18:37, Philippe Mathieu-Daudé wrote:
On 19/12/24 12:01, Xiaoyao Li wrote:
There are duplicated code to setup the value of MSR_CORE_THREAD_COUNT.
Extract a common function for it.
Signed-off-
On Mon, Jan 06, 2025 at 07:26:20AM -0800, Joelle van Dyne wrote:
> If the policy is macOS 12 or later then you still need patch 2-3 because
> currently it is broken on macOS 12.
Actually our min baseline for macOS is currently macOS 14.
Per the doc Peter mentions, we officially target the most re
On 1/3/25 09:10, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (5):
semihosting/syscalls: Include missing 'exec/cpu-defs.h' header
semihosting/uaccess: Include missing 'exec/cpu-all.h' header
semihosting/arm-compat: Include missing 'cpu.h' header
semihosting/console: Avoid incl
On Sat, Jan 04, 2025 at 05:04:07PM +0900, Akihiko Odaki wrote:
> g_spawn_check_exit_status() is renamed to g_spawn_check_wait_status()
> in 2.70.
>
> Signed-off-by: Akihiko Odaki
> ---
> include/glib-compat.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/glib-compat.h b/inc
On Sat, Jan 04, 2025 at 05:04:08PM +0900, Akihiko Odaki wrote:
> g_spawn_sync() gives an informative message if it fails to execute
> the script instead of reporting exiting status 1.
>
> g_spawn_check_wait_status() also gives an message easier to understand
> than the raw value returned by waitpi
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
target/riscv/translate.c | 22 --
target/riscv/vector_helper.c | 16
2 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/targe
From: Alexey Baturo
Zjpm extension is finally ratified. And it's much simplier compared to the
experimental one.
The newer version doesn't allow to specify custom mask or base for pointer
masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo
Acked-
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 4
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 33 +++--
t
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h| 5 +++
target/riscv/cpu_helper.c | 78 +++
2 files changed, 83 insertions(+)
diff --git a/target/riscv/cpu.
Hi Alistair,
I rebased these patches against riscv-to-apply.next and resubmitted them.
Thanks
пн, 6 янв. 2025 г. в 06:36, Alistair Francis :
> On Tue, Dec 17, 2024 at 6:57 PM wrote:
> >
> > From: Alexey Baturo
> >
> > Hi,
> >
> > Rebased and addressed Alistair's comments on code style.
> >
>
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_helper.c| 19 +
target/riscv/internals.h | 54
target/riscv/op
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 99588e219e..d9eb2c04c3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -193,
From: Alexey Baturo
Signed-off-by: Alexey Baturo
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: LIU Zhiwei
---
target/riscv/cpu.h| 3 +++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +
3 files changed, 11 insertions(+)
diff --git a
From: Alexey Baturo
Hi,
Rebased against Alistair's riscv-to-apply.next
Thanks
[v14]:
Rebased and addressed Alistair's comments on code style.
[v13]:
Rebased and addressed Daniel's comments about the return type of the helper.
Thanks
[v12]:
Rebased and addressed Richard's comments about pro
Hi Thomas,
test_x86_64_hotplug_cpu.py times out frequently in CI runs. Here is an example:
https://gitlab.com/qemu-project/qemu/-/jobs/8777540230#L1151
The detailed test logs are here:
https://gitlab.com/qemu-project/qemu/-/jobs/8777540230/artifacts/browse/build/tests/functional/x86_64/test_x86_64
On Mon, 6 Jan 2025 at 16:45, Stefan Hajnoczi wrote:
>
> Hi Thomas,
> test_x86_64_hotplug_cpu.py times out frequently in CI runs. Here is an
> example:
> https://gitlab.com/qemu-project/qemu/-/jobs/8777540230#L1151
>
> The detailed test logs are here:
> https://gitlab.com/qemu-project/qemu/-/jobs/
On Tue, Dec 31, 2024 at 01:23:31AM +0100, Paolo Bonzini wrote:
> Date: Tue, 31 Dec 2024 01:23:31 +0100
> From: Paolo Bonzini
> Subject: [RFC PATCH 4/9] rust: vmstate: implement Zeroable for VMStateField
> X-Mailer: git-send-email 2.47.1
>
> This shortens a bit the constants. Do not bother using
Il lun 6 gen 2025, 14:32 Peter Maydell ha
scritto:
> I think here I agree with Philippe that we might as well
> provide only the new API to Rust devices.
>
Ok, I wasn't thinking of doing that because there isn't right now an easy
way to add interfaces to Rust-defined classes. However, all device
If the policy is macOS 12 or later then you still need patch 2-3 because
currently it is broken on macOS 12.
On Monday, January 6, 2025, Peter Maydell wrote:
> On Mon, 23 Dec 2024 at 04:10, Joelle van Dyne wrote:
> > Some features require APIs introduced in a recent version of macOS.
> Currentl
On 2025/1/6 21:38, fuqiang wang wrote:
I'm sorry for getting back to you after a few days.
在 2025/1/3 00:40, Yong Huang 写道:
>
>
> On Tue, Dec 31, 2024 at 9:56 AM fuqiang wang wrote:
>
> The current dirtylimit_throttle_pct trace event is triggered when the
> throttle time is adjusted li
From: Eugenio Pérez
Commit a0d7215e33 ("vhost-vdpa: do not cleanup the vdpa/vhost-net
structures if peer nic is present") effectively delayed the backend
cleanup, allowing the frontend or the guest to access it resources as
long as the frontend is still visible to the guest.
However it does not
Commit a0d7215e33 ("vhost-vdpa: do not cleanup the vdpa/vhost-net
structures if peer nic is present") effectively delayed the backend
cleanup, allowing the frontend or the guest to access it resources as
long as the frontend NIC is still visible to the guest.
However it does not clean up the resou
From: Eugenio Pérez
This change is used in later commits so we can avoid the removal of the
netclient if it is delayed.
No functional change intended.
Reviewed-by: Si-Wei Liu
Acked-by: Jason Wang
Signed-off-by: Eugenio Pérez
---
net/net.c | 13 -
1 file changed, 8 insertions(+),
On Thu, 2024-12-19 at 18:24 +0100, David Woodhouse wrote:
> On Tue, 2024-12-03 at 17:33 +, David Woodhouse wrote:
> > From: David Woodhouse
> >
> > The vmclock device addresses the problem of live migration with
> > precision clocks. The tolerances of a hardware counter (e.g. TSC) are
> > typ
On Thu, 2024-12-19 at 17:24 +0100, David Woodhouse wrote:
> From: David Woodhouse
>
> The system GSIs are not designed for sharing. One device might assert a
> shared interrupt with qemu_set_irq() and another might deassert it, and
> the level from the first device is lost.
>
> This could be sol
On 12/23/24 11:33 AM, Eugenio Perez Martin wrote:
On Fri, Dec 20, 2024 at 10:02 PM Michael Tokarev wrote:
12.09.2024 19:54, Eugenio Pérez wrote:
Commit a0d7215e33 ("vhost-vdpa: do not cleanup the vdpa/vhost-net
structures if peer nic is present") effectively delayed the backend
cleanup, al
On 1/3/25 07:05, Philippe Mathieu-Daudé wrote:
As Daniel suggested [*]:
We should consider to rank HVF above TCG, on the basis
that HW acceleration is faster and should provide a
host<->guest security boundary that we don't claim for TCG
[*] https://lore.kernel.org/qemu-devel/z07yasl2pd3cp...
Do a cosmetic change in riscv_raise_exception() to change 'exception'
type from uint32_t to RISCVException, making it a bit clear that the
arg is directly correlated to the RISCVException enum.
As a side effect, change 'excp' type from int to RISCVException in
generate_exception() to guarantee tha
Hi,
This new version is a re-sent of v1, rebased on top of
alistair/riscv-to-apply.next, with acks/r-bs added.
No other changes made.
Changes from v1:
- rebased on top of alistair/riscv-to-apply.next
- v1 link:
https://lore.kernel.org/qemu-riscv/20241219174657.1988767-1-dbarb...@ventanamicro.co
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