Hi Richard,
On 2/1/25 19:06, Richard Henderson wrote:
Pass a type parameter to the macros; this is unused with these opcodes,
but will be used with others, so keep it for uniformity.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
include/tcg/tcg-opc.h | 24 +++---
tcg/aarch64/tcg-target-has.h | 9 +-
tcg/arm/tcg-target-has.h | 7 +-
tcg/i386/tcg-target-has.h | 6 +-
tcg/loongarch64/tcg-target-has.h | 11 +--
tcg/mips/tcg-target-has.h | 9 +-
tcg/ppc/tcg-target-has.h | 9 +-
tcg/riscv/tcg-target-has.h | 11 +--
tcg/s390x/tcg-target-has.h | 6 +-
tcg/sparc64/tcg-target-has.h | 9 +-
tcg/tcg-has.h | 19 ++---
tcg/tci/tcg-target-has.h | 8 +-
tcg/tcg-op.c | 136 ++++++++++++++++++-------------
tcg/tcg.c | 12 +--
14 files changed, 139 insertions(+), 137 deletions(-)
diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h
index a6c7cdba5d..6734fd63e7 100644
--- a/tcg/ppc/tcg-target-has.h
+++ b/tcg/ppc/tcg-target-has.h
@@ -16,13 +16,14 @@
#define have_altivec (cpuinfo & CPUINFO_ALTIVEC)
#define have_vsx (cpuinfo & CPUINFO_VSX)
+/* optional integer instructions */
+#define TCG_TARGET_HAS_div(T) 1
+#define TCG_TARGET_HAS_rem(T) 1
Can you explain this change?
/* optional instructions automatically implemented */
#define TCG_TARGET_HAS_ext8u_i32 0 /* andi */
#define TCG_TARGET_HAS_ext16u_i32 0
-/* optional instructions */
-#define TCG_TARGET_HAS_div_i32 1
-#define TCG_TARGET_HAS_rem_i32 have_isa_3_00
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
@@ -52,8 +53,6 @@
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_extr_i64_i32 0
-#define TCG_TARGET_HAS_div_i64 1
-#define TCG_TARGET_HAS_rem_i64 have_isa_3_00
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_ext8s_i64 1
#define TCG_TARGET_HAS_ext16s_i64 1
