On Wed, Dec 25, 2024 at 10:38 AM Dehan Meng wrote:
>
> Make sure the error log of fsfreeze hooks
> when freeze/thaw/snapshot could be logged
> to system logs if the default logfile of
> qga can't be written or other situations
>
> Signed-off-by: Dehan Meng
> ---
> scripts/qemu-guest-agent/fsfree
Frank,
I believe patch 7 should be squashed in with this one. This patch will break
'check-functional' because the 'max' CPU isn't able to support Smrnmi and we're
only fixing it 2 patches later. In theory this is fine but it can be problematic
when doing bisecting looking for bugs.
If you mer
On 12/17/24 3:24 AM, frank.ch...@sifive.com wrote:
From: Frank Chang
Zicfilp extension introduces the MNPELP (bit 9) in mnstatus.
The MNPELP field holds the previous ELP.
When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set
to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNP
On 12/17/24 3:24 AM, frank.ch...@sifive.com wrote:
From: Tommy Wu
Because the RNMI interrupt trap handler address is implementation defined.
We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property
of the harts. It’s very easy for users to set the address based on their
On 12/17/24 3:24 AM, frank.ch...@sifive.com wrote:
From: Tommy Wu
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted conte
To prevent integer overflow it is worth casting 1 to 1ULL.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Tigran Sogomonian
---
hw/misc/mps2-fpgaio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio
The value of an arithmetic expression
'rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION' is a subject
to overflow because its operands are not cast to
a larger data type before performing arithmetic. Thus, need
to cast rpm to uint64_t.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signe
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/10.0 for any
user-visible changes.
signature.asc
Description: PGP signature
On 12/18/24 4:15 AM, Chao Liu wrote:
We want a commit message here because the change is not trivial.
You gave an explanation in the v1 cover letter:
---
Recently, when I was writing a RISCV test, I found that when VL is set to 0, the
instruction should be nop, but when I tested it, I found tha
On 12/26/24 01:58, Tigran Sogomonian wrote:
To prevent integer overflow it is worth casting 1 to 1ULL.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Tigran Sogomonian
---
hw/misc/mps2-fpgaio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
On 12/18/24 4:15 AM, Chao Liu wrote:
Some vector instructions are special, such as the vlm.v instruction,
where setting its vl actually sets evl = (vl + 7) >> 3. To improve
maintainability, we will uniformly use VSTART_CHECK_EARLY_EXIT() to
check for the condition vstart >= vl. This function w
s->buswidth = nand_flash_ids[s->chip_id].width >> 3;
<= 16 >> 3 <= 2.
x <= s->ioaddr[offset] << (s->buswidth << 3)
<= max_uint8_t << 16
With x << 24 overflow is possible.
Other cases are similar.
Thus, need to cast return value to uint64_t.
Found by Linux Verification Center (linuxtesting.org) wit
On Thu, Dec 26, 2024 at 6:00 AM Tigran Sogomonian
wrote:
> The value of an arithmetic expression
> 'rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION' is a subject
> to overflow because its operands are not cast to
> a larger data type before performing arithmetic. Thus, need
> to cast rpm to uint64_t.
>
>
Signed-off-by: Hao Wu
---
configs/devices/aarch64-softmmu/default.mak | 1 +
hw/arm/Kconfig | 11 +
hw/arm/meson.build | 1 +
hw/arm/npcm8xx.c| 810
include/hw/arm/npcm8xx.h
Signed-off-by: Hao Wu
---
hw/arm/meson.build | 2 +-
hw/arm/npcm8xx_boards.c | 256 +++
include/hw/arm/npcm8xx.h | 20 +++
3 files changed, 277 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/npcm8xx_boards.c
diff --git a/hw/arm/meson.build b
These 2 values are different between NPCM7XX and NPCM8XX
CLKs. So we add them to the class and assign different values
to them.
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 17 +++--
include/hw/misc/npcm_clk.h | 9 -
2 files changed, 19 insertions(+), 7 deletions(-
NPCM8XX adds a few new registers and have a different set of reset
values to the CLK modules. This patch supports them.
This patch doesn't support the new clock values generated by these
registers. Currently no modules use these new clock values so they
are not necessary at this point.
Implementat
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
PHY. This implementation contains all the default registers and
the soft reset feature that are required to load the Linux kernel
driver. Further features have not been implemented yet.
Signed-off-by: Hao Wu
---
hw/net/meson.buil
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 131 -
include/hw/misc/npcm_gcr.h | 6 +-
2 files changed, 134 insertions(+), 3 deletions(-)
diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c
index 295073ba14..52d0fa07ea 100644
--- a/hw/misc/npcm_gc
The NPCM8xx GCR device can be accessed with 64-bit memory operations.
This patch supports that.
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 94 +---
hw/misc/trace-events | 4 +-
2 files changed, 74 insertions(+), 24 deletions(-)
diff --git a/hw/misc
NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR
module. Since we don't simulate a detailed memory controller, we
need to store this information directly similar to the NPCM7XX's
INCTR3 register.
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 24 +++
The following changes since commit a7f77545d401266a6415e6e03c7738c95314f0e6:
Merge tag 'pull-tcg-20241224' of https://gitlab.com/rth7680/qemu into staging
(2024-12-25 08:33:33 -0500)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-vfio-2024122
A lot of NPCM7XX and NPCM8XX GCR modules share the same code,
this commit moves the NPCM7XX GCR to NPCM GCR for these
properties.
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 92 +-
hw/misc/trace-events | 6 +--
include/hw/arm/npcm7xx.h | 2
This allows different FIUs to have different flash sizes, useful
in NPCM8XX which has multiple different sized FIU modules.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 6 ++
hw/ssi/npcm7xx_fiu.c | 11 +++
include/hw/ssi/npcm7xx_fiu.h | 1 +
3 files changed, 14
NPCM7XX and NPCM8XX have a different set of CLK registers. This
commit changes the name of the clk files to be used by both
NPCM7XX and NPCM8XX CLK modules.
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 2 +-
hw/misc/{npcm7xx_clk.c => npcm_clk.c} | 2 +-
inclu
This newer vbootrom supports NPCM8xx. Similar to the NPCM7XX one
it supports loading the UBoot from the SPI device and not more.
We updated the npcm7xx bootrom to be compiled from this version.
Signed-off-by: Hao Wu
---
pc-bios/npcm7xx_bootrom.bin | Bin 768 -> 768 bytes
roms/vbootrom
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
Signed-off-by: Hao Wu
---
docs/system/arm/nuvoton.rst | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/docs/system/arm/nuvo
NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module
needs to fit both. This commit changes the name of the GCR module.
Future commits will add the support for NPCM8XX GCRs.
Signed-off-by: Hao Wu
---
hw/misc/meson.build | 2 +-
hw/misc/{npcm7xx_gcr.c => n
Changes since v1:
1. Updated vbootrom and pc-bios
2. Split out CLK/GCR patches into refactoring and adding new features
3. Fixed a few misc items from the patches.
---
NPCM8XX BMCs are the successors of the NPCM7XX BMCs. They feature
quad-core ARM Cortex A35 that supports both 32 bits and 64 bit
These 2 values are different between NPCM7XX and NPCM8XX
GCRs. So we add them to the class and assign different values
to them.
Signed-off-by: Hao Wu
---
hw/misc/npcm_gcr.c | 24 +++-
include/hw/misc/npcm_gcr.h | 13 +++--
2 files changed, 26 insertions(+), 11
A lot of NPCM7XX and NPCM8XX CLK modules share the same code,
this commit moves the NPCM7XX CLK to NPCM CLK for these
properties.
Signed-off-by: Hao Wu
---
hw/misc/npcm_clk.c | 106 +
hw/misc/trace-events | 6 +--
include/hw/arm/npcm7xx.h |
The bootrom is a minimal bootrom used to load an NPCM8XX image.
The source code is located in the same repo as the NPCM7XX one:
github.com/google/vbootrom/tree/master/npcm8xx.
Signed-off-by: Hao Wu
---
MAINTAINERS | 1 +
pc-bios/README | 8
pc-bios/meson
This newer vbootrom supports NPCM8xx. Similar to the NPCM7XX one
it supports loading the UBoot from the SPI device and not more.
We updated the npcm7xx bootrom to be compiled from this version.
Signed-off-by: Hao Wu
---
pc-bios/npcm7xx_bootrom.bin | Bin 768 -> 768 bytes
roms/vbootrom
On 26/12/24 10:58, Tigran Sogomonian wrote:
To prevent integer overflow it is worth casting 1 to 1ULL.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Tigran Sogomonian
---
hw/misc/mps2-fpgaio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
Hi!
What's the reason to require python-pycotap when configuring qemu?
It does not look like an essential part of build procedure, but used
to run tests only, no?
While this python module is shipped with qemu, but for downstream
distributions these are usually stripped off the source tarball.
T
On 26/12/24 05:22, bibo mao wrote:
On 2024/12/25 下午7:32, Philippe Mathieu-Daudé wrote:
Hi Bibo,
On 25/12/24 03:40, Bibo Mao wrote:
From: ghy <2247883...@qq.com>
Is this authorship correct? Should it be:
From: Guo Hongyu
yes, this is better.
Refer to the link below for a description o
Fix types for various TCGv.
Performing TCGv type conversion as necessary when interaction with GPR
happens.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_vec.c.inc | 70 +
1 file changed, 36 insertions(+), 34 deletions(-)
diff --git a/target/loong
Hi all,
It's boxing day so time to dump big stuff!
This series is a collection of small fixes I made to TCG for
getting LoongArch32 build to work.
There are still many thing broken, especially on CSRs. More
series following. A brief todo would be:
- Refactoring CSR handling to perform sign exten
Use tl variant whenever possible.
Silent compiler warnings by performing casting for come consts.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_bit.c.inc | 34 ++---
1 file changed, 19 insertions(+), 15 deletions(-)
diff --git a/target/loongarch/tcg/i
Add LoongArch32 Kconfig entry and enable the virt machine for
LoongArch32.
Signed-off-by: Jiaxun Yang
---
hw/loongarch/Kconfig | 2 +-
target/loongarch/Kconfig | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index
fe1c6feac1
As per "LoongArch Reference Manual Volume 1: Basic Architecture" v1.1.0,
"2.2 Table 2. Application-level basic integer instructions in LA32",
rotr.w and rotri.w is a part of LA32 basic integer instructions.
Note that those instructions are indeed not in LA32R subset, however QEMU
is not performing
mulh.w and mulh.wu are handled with tcg_gen_muls2_i32 and tcg_gen_mulu2_i32
to adopt different TARGET_LONG size.
min value of divisor is generated from TARGET_LONG_BITS to adopt different
long size as well.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_arith.c.inc | 25 ++
is_la64 should be wired to false on LA32 build.
VA32 CSR check shouldn't be performed in LA32 mode.
Signed-off-by: Jiaxun Yang
---
target/loongarch/cpu.h | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index
Those results are all targeting TCGv values, which means they should
be in target_ulong type.
Signed-off-by: Jiaxun Yang
---
target/loongarch/helper.h | 8
target/loongarch/tcg/iocsr_helper.c | 8
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/l
gen_sc should use make_address_i to obtain source address
to ensure that address is properly truncated.
Another temp value is created in middle to avoid data corruption
as make_address_i may return the same memory location as src1.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/
LoongArch32 have 32 bit vaddr and 36 bit paddr as per architecture
specification.
Signed-off-by: Jiaxun Yang
---
target/loongarch/cpu-param.h | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index
db5ad1
On 12/26/24 13:19, Jiaxun Yang wrote:
As per "LoongArch Reference Manual Volume 1: Basic Architecture" v1.1.0,
"2.2 Table 2. Application-level basic integer instructions in LA32",
rotr.w and rotri.w is a part of LA32 basic integer instructions.
Note that those instructions are indeed not in LA32
On 12/26/24 13:19, Jiaxun Yang wrote:
gen_sc should use make_address_i to obtain source address
to ensure that address is properly truncated.
Another temp value is created in middle to avoid data corruption
as make_address_i may return the same memory location as src1.
Signed-off-by: Jiaxun Yan
All float computations are kept to be 64 bit, fix types for various TCGv.
Performing TCGv type conversion as necessary when interaction with GPR
happens.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_farith.c.inc | 53 +++---
target/loongarch/tcg/insn_trans/trans_
target_ulong -> TARGET_FMT_ld
vaddr -> VADDR_PRIx
uint32_t -> PRIx32
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
target/loongarch/tcg/tlb_helper.c | 2 +-
target/loongarch/tcg/translate.c | 5 ++---
3 files changed,
Avoid compiler warning on 32bit. This code path won't be taken anyway.
Signed-off-by: Jiaxun Yang
---
target/loongarch/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index
580362ac3e9ffbe6c8523cf5790
Store internal registers including GPRs, CSRs, and LBT scratchs
as target_ulong, as per architecture specification.
The only exception here is tlb_misc, as it's only used by QEMU
internally and need keep to be 64bit to store all required fields.
There is no migration ABI change, as target_ulong i
Introduce max32 CPU type as it's necessary to demonstrate all
features we have in LA32.
Signed-off-by: Jiaxun Yang
---
target/loongarch/cpu.c | 92 ++
1 file changed, 92 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
in
As per LoongArch Reference Manual - Volume 1: Basic Architecture,
4.2.2. IOCSR Access Instructions:
The reading value is described as "writes it to the general register rd
after symbolic expansion." which means it should be sign extended.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/iocs
la464 CPU is not available on LoongArch32. Use max32 which makes
more sense here.
Signed-off-by: Jiaxun Yang
---
hw/loongarch/virt.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index
3a905cf71d46e3c5a29672f7bb73faedf1d29444..343d2e745e155d59
They are not available on 32 bit builds.
Signed-off-by: Jiaxun Yang
---
target/loongarch/cpu.c | 68 --
1 file changed, 38 insertions(+), 30 deletions(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index
82412f8867a50a6cd25cff511
Signed-off-by: Jiaxun Yang
---
MAINTAINERS | 4 ++--
configs/devices/loongarch32-softmmu/default.mak | 7 +++
configs/targets/loongarch32-softmmu.mak | 7 +++
3 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAIN
gen_ll should use tcg_gen_qemu_ld_tl to load t1, as t1 is
in TCGv which means it should be a tl type value.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/t
As per manual, the source of PGD CSR is relevant to highest bit of
BADV. In LoongArch32, all CSRs are 32 bits only, thus we should check
bit 31 of BADV to determine PGDH/PGDL for LoongArch32.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/csr_helper.c | 2 +-
1 file changed, 1 insertion(+),
All TARGET_LOONGARCH64 qapis are also available for LoongArch32 as we
are reusing the same CPU backend implemenation.
Use TARGET_LOONGARCH to identify LoongArch.
Signed-off-by: Jiaxun Yang
---
qapi/machine-target.json | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/q
Use TCGv_i64 for intermediate values and perform truncation as necessary.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_extra.c.inc | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/tcg/insn_trans/trans_extra.c.inc
b/target/loong
All CSRs are meant to be target_ulong wide in our setting.
Signed-off-by: Jiaxun Yang
---
target/loongarch/helper.h| 14 +++---
target/loongarch/tcg/op_helper.c | 4 ++--
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/loongarch/helper.h b/target/loongarch/
On 12/26/24 13:19, Jiaxun Yang wrote:
Avoid compiler warning on 32bit. This code path won't be taken anyway.
Signed-off-by: Jiaxun Yang
---
target/loongarch/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_h
On 12/26/24 13:19, Jiaxun Yang wrote:
target_ulong -> TARGET_FMT_ld
vaddr -> VADDR_PRIx
uint32_t -> PRIx32
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
target/loongarch/tcg/tlb_helper.c | 2 +-
target/loongarch/tcg/translate.c
On 12/26/24 13:19, Jiaxun Yang wrote:
Those results are all targeting TCGv values, which means they should
be in target_ulong type.
Signed-off-by: Jiaxun Yang
---
target/loongarch/helper.h | 8
target/loongarch/tcg/iocsr_helper.c | 8
2 files changed, 8 insertion
On 12/26/24 13:19, Jiaxun Yang wrote:
All CSRs are meant to be target_ulong wide in our setting.
Signed-off-by: Jiaxun Yang
---
target/loongarch/helper.h| 14 +++---
target/loongarch/tcg/op_helper.c | 4 ++--
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/ta
On 12/26/24 13:19, Jiaxun Yang wrote:
Use tl variant whenever possible.
Silent compiler warnings by performing casting for come consts.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_bit.c.inc | 34 ++---
1 file changed, 19 insertions(+), 15 deletio
On 12/26/24 13:19, Jiaxun Yang wrote:
Use TCGv_i64 for intermediate values and perform truncation as necessary.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_extra.c.inc | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/tcg/in
Hi Philippe,
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Wednesday, December 25, 2024 7:28 PM
> To: Steven Lee ; Cédric Le Goater
> ; Peter Maydell ; Troy Lee
> ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc:
Hi Philippe,
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Wednesday, December 25, 2024 7:30 PM
> To: Steven Lee ; Cédric Le Goater
> ; Peter Maydell ; Troy Lee
> ; Jamin Lin ; Andrew
> Jeffery ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc:
On 12/26/24 13:19, Jiaxun Yang wrote:
mulh.w and mulh.wu are handled with tcg_gen_muls2_i32 and tcg_gen_mulu2_i32
to adopt different TARGET_LONG size.
min value of divisor is generated from TARGET_LONG_BITS to adopt different
long size as well.
Signed-off-by: Jiaxun Yang
---
target/loongarch
On 12/26/24 13:19, Jiaxun Yang wrote:
gen_ll should use tcg_gen_qemu_ld_tl to load t1, as t1 is
in TCGv which means it should be a tl type value.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
1 file changed, 1 i
On 12/26/24 13:19, Jiaxun Yang wrote:
@@ -4850,12 +4852,12 @@ static bool gen_g2x(DisasContext *ctx, arg_vr_i *a,
MemOp mop,
return gen_g2v_vl(ctx, a, 32, mop, func);
}
-TRANS(vinsgr2vr_b, LSX, gen_g2v, MO_8, tcg_gen_st8_i64)
-TRANS(vinsgr2vr_h, LSX, gen_g2v, MO_16, tcg_gen_st16_i64)
On 26/12/24 22:19, Jiaxun Yang wrote:
la464 CPU is not available on LoongArch32. Use max32 which makes
more sense here.
Signed-off-by: Jiaxun Yang
---
hw/loongarch/virt.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index
3a905cf71d46e3c5
On 26/12/24 22:19, Jiaxun Yang wrote:
Introduce max32 CPU type as it's necessary to demonstrate all
features we have in LA32.
Signed-off-by: Jiaxun Yang
---
target/loongarch/cpu.c | 92 ++
1 file changed, 92 insertions(+)
#ifdef TARGET_LO
On 12/26/24 14:08, Jiaxun Yang wrote:
在2024年12月26日十二月 下午9:55，Richard Henderson写道：
[...]
While this allows the code to compile, (1) the functions are unused and
(2) they do not
compute the required results. For me, the latter is concerning.
I'd suggest moving GEN_FALSE_TRANS out of trans_priv
On 26/12/24 23:58, Jiaxun Yang wrote:
在2024年12月26日十二月 下午10:48，Philippe Mathieu-Daudé写道：
On 26/12/24 22:19, Jiaxun Yang wrote:
Store internal registers including GPRs, CSRs, and LBT scratchs
as target_ulong, as per architecture specification.
The only exception here is tlb_misc, as it's only
在2024年12月26日十二月 下午10:55，Philippe Mathieu-Daudé写道：
> On 26/12/24 22:19, Jiaxun Yang wrote:
>> Introduce max32 CPU type as it's necessary to demonstrate all
>> features we have in LA32.
>>
>> Signed-off-by: Jiaxun Yang
>> ---
>> target/loongarch/cpu.c | 92
>> +
> @@ -8165,9 +8157,6 @@ static void x86_cpu_init_default_topo(X86CPU *cpu)
> {
> CPUX86State *env = &cpu->env;
>
> -env->nr_modules = 1;
> -env->nr_dies = 1;
> -
Instead, initialize topo_info?
> /* thread, core and socket levels are set by default. */
> set_bit(CPU_TOPOL
On Thu, Dec 19, 2024 at 06:01:22AM -0500, Xiaoyao Li wrote:
> Date: Thu, 19 Dec 2024 06:01:22 -0500
> From: Xiaoyao Li
> Subject: [PATCH v2 07/10] i386/cpu: Hoist check of CPUID_EXT3_TOPOEXT
> against threads_per_core
> X-Mailer: git-send-email 2.34.1
>
> Now it changes to use env->topo_info.thr
Tigran Sogomonian writes:
> s->buswidth = nand_flash_ids[s->chip_id].width >> 3;
> <= 16 >> 3 <= 2.
> x <= s->ioaddr[offset] << (s->buswidth << 3)
> <= max_uint8_t << 16
> With x << 24 overflow is possible.
> Other cases are similar.
> Thus, need to cast return value to uint64_t.
>
> Found by Lin
On 12/26/24 14:58, Philippe Mathieu-Daudé wrote:
On 26/12/24 22:19, Jiaxun Yang wrote:
Signed-off-by: Jiaxun Yang
---
MAINTAINERS | 4 ++--
configs/devices/loongarch32-softmmu/default.mak | 7 +++
configs/targets/loongarch32-softmmu.mak | 7 ++
On 12/26/24 18:39, Michael Tokarev wrote:
Hi!
What's the reason to require python-pycotap when configuring qemu?
It does not look like an essential part of build procedure, but used
to run tests only, no?
While this python module is shipped with qemu, but for downstream
distributions these are
On 27/12/24 00:03, Jiaxun Yang wrote:
在2024年12月26日十二月 下午10:56，Philippe Mathieu-Daudé写道：
On 26/12/24 22:19, Jiaxun Yang wrote:
la464 CPU is not available on LoongArch32. Use max32 which makes
more sense here.
Signed-off-by: Jiaxun Yang
---
hw/loongarch/virt.c | 4
1 file changed, 4 i
On Fri, Dec 27, 2024 at 3:02 AM Patrick Leis wrote:
>
>
> On Thu, Dec 26, 2024 at 6:00 AM Tigran Sogomonian <
> tsogomon...@astralinux.ru> wrote:
>
>> The value of an arithmetic expression
>> 'rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION' is a subject
>> to overflow because its operands are not cast to
在2024年12月26日十二月 下午9:31，Richard Henderson写道：
[...]
>>
>> -target_ulong helper_crc32c(target_ulong val, target_ulong m, uint64_t sz)
>> +target_ulong helper_crc32c(target_ulong val, target_ulong m, target_ulong
>> sz)
>> {
>> uint8_t buf[8];
>> target_ulong mask = ((sz * 8) == 64
On 12/26/24 13:19, Jiaxun Yang wrote:
All float computations are kept to be 64 bit, fix types for various TCGv.
Performing TCGv type conversion as necessary when interaction with GPR
happens.
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_farith.c.inc | 53 +++---
在2024年12月26日十二月 下午9:55，Richard Henderson写道：
[...]
> While this allows the code to compile, (1) the functions are unused and
> (2) they do not
> compute the required results. For me, the latter is concerning.
>
> I'd suggest moving GEN_FALSE_TRANS out of trans_privileged.c.inc, then
>
> #ifdef
在2024年12月26日十二月 下午10:48，Philippe Mathieu-Daudé写道：
> On 26/12/24 22:19, Jiaxun Yang wrote:
>> Store internal registers including GPRs, CSRs, and LBT scratchs
>> as target_ulong, as per architecture specification.
>>
>> The only exception here is tlb_misc, as it's only used by QEMU
>> internally
On 26/12/24 22:19, Jiaxun Yang wrote:
Signed-off-by: Jiaxun Yang
---
MAINTAINERS | 4 ++--
configs/devices/loongarch32-softmmu/default.mak | 7 +++
configs/targets/loongarch32-softmmu.mak | 7 +++
3 files changed, 16 insertions(+), 2 delet
On Thu, Dec 19, 2024 at 06:01:18AM -0500, Xiaoyao Li wrote:
> Date: Thu, 19 Dec 2024 06:01:18 -0500
> From: Xiaoyao Li
> Subject: [PATCH v2 03/10] i386/cpu: Drop cores_per_pkg in cpu_x86_cpuid()
> X-Mailer: git-send-email 2.34.1
>
> Local variable cores_per_pkg is only used to calculate threads_p
On Thu, Dec 19, 2024 at 06:01:17AM -0500, Xiaoyao Li wrote:
> Date: Thu, 19 Dec 2024 06:01:17 -0500
> From: Xiaoyao Li
> Subject: [PATCH v2 02/10] i386/cpu: Drop the variable smp_cores and
> smp_threads in x86_cpu_pre_plug()
> X-Mailer: git-send-email 2.34.1
>
> No need to define smp_cores and s
> +static inline unsigned x86_module_per_pkg(X86CPUTopoInfo *topo_info)
> +{
> +return topo_info->modules_per_die * topo_info->dies_per_pkg;
> +}
> +
> +static inline unsigned x86_cores_per_pkg(X86CPUTopoInfo *topo_info)
> +{
> +return topo_info->cores_per_module * x86_module_per_pkg(topo_i
On 26/12/24 22:19, Jiaxun Yang wrote:
Store internal registers including GPRs, CSRs, and LBT scratchs
as target_ulong, as per architecture specification.
The only exception here is tlb_misc, as it's only used by QEMU
internally and need keep to be 64bit to store all required fields.
There is no
On 26/12/24 22:19, Jiaxun Yang wrote:
Those results are all targeting TCGv values, which means they should
be in target_ulong type.
Signed-off-by: Jiaxun Yang
---
target/loongarch/helper.h | 8
target/loongarch/tcg/iocsr_helper.c | 8
2 files changed, 8 insertion
On 26/12/24 22:19, Jiaxun Yang wrote:
target_ulong -> TARGET_FMT_ld
vaddr -> VADDR_PRIx
uint32_t -> PRIx32
Signed-off-by: Jiaxun Yang
---
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
target/loongarch/tcg/tlb_helper.c | 2 +-
target/loongarch/tcg/translate.c
在2024年12月26日十二月 下午10:56，Philippe Mathieu-Daudé写道：
> On 26/12/24 22:19, Jiaxun Yang wrote:
>> la464 CPU is not available on LoongArch32. Use max32 which makes
>> more sense here.
>>
>> Signed-off-by: Jiaxun Yang
>> ---
>> hw/loongarch/virt.c | 4
>> 1 file changed, 4 insertions(+)
>>
>> d
On 12/25/24 17:24, Zhao Liu wrote:
On Fri, Dec 20, 2024 at 03:29:44PM +0100, Paolo Bonzini wrote:
Date: Fri, 20 Dec 2024 15:29:44 +0100
From: Paolo Bonzini
Subject: [PATCH 02/12] rust: add a utility module for compile-time type
checks
X-Mailer: git-send-email 2.47.1
It is relatively common i
On Thu, Dec 19, 2024 at 06:01:16AM -0500, Xiaoyao Li wrote:
> Date: Thu, 19 Dec 2024 06:01:16 -0500
> From: Xiaoyao Li
> Subject: [PATCH v2 01/10] i386/cpu: Extract a common fucntion to setup
> value of MSR_CORE_THREAD_COUNT
> X-Mailer: git-send-email 2.34.1
>
> There are duplicated code to setu
Like LBT feature, add type OnOffAuto for LSX feature setting. Also
add LSX feature detection with new VM ioctl command, fallback to old
method if it is not supported.
Signed-off-by: Bibo Mao
Reviewed-by: Bibo Mao
---
target/loongarch/cpu.c | 38 +++
target/loongarch/
1 - 100 of 124 matches
Mail list logo
