[PULL 46/72] target/arm: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for the arm target. This includes setting it for the old linux-user nwfpe emulation. For nwfpe, our default doesn't match the real kernel, but we avoid making a behaviour change in this commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Mes

[PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd

For IEEE fused multiply-add, the (0 * inf) + NaN case should raise Invalid for the multiplication of 0 by infinity. Currently we handle this in the per-architecture ifdef ladder in pickNaNMulAdd(). However, since this isn't really architecture specific we can hoist it up to the generic code. For

[PULL 42/72] target/microblaze: Set default NaN pattern explicitly

Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-37-peter.mayd...@linaro.org --- target/microblaze/cpu.c| 2 ++ fpu/softfloat-specialize.c.inc | 3 +-- 2

[PULL 41/72] tests/fp: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for the tests/fp code. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-36-peter.mayd...@linaro.org --- tests/fp/fp-bench.c | 1 + tests/fp/fp-test-log2.c | 1 + tests/fp/fp-test.c | 1 + 3 files change

[PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly

Set the Float3NaNPropRule explicitly for SPARC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-22-peter.mayd...@linaro.org --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 --

[PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg

In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion from float64 to floatx80 using a scratch float_status, because we don't want the conversion to affect the CPU's floating point exception status. Currently we use a zero-initialized float_status. This will get steadily more awkwar

[PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement

From: Bernhard Beschow The real device advertises this mode and the device model already advertises 100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to make the model more realistic. Reviewed-by: Peter Maydell Signed-off-by: Bernhard Beschow Tested-by: Guenter Roeck M

[PULL 52/72] target/sh4: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for sh4. Note that sh4 is one of the only three targets (the others being HPPA and sometimes MIPS) that has snan_bit_is_one set. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-47-peter.mayd...@linaro.org --- t

[PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status

In the helper functions flcmps and flcmpd we use a scratch float_status so that we don't change the CPU state if the comparison raises any floating point exception flags. Instead of zero-initializing this scratch float_status, initialize it as a copy of env->fp_status. This avoids the need to expli

[PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan()

Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL) to get the NaN bit pattern to reset the FPU registers. This works because it happens that our implementation of floatx80_default_nan() doesn't actually look at the float_status pointer except for TARGET_MIPS. However, this isn't guara

[PULL 29/72] target/i386: Set Float3NaNPropRule explicitly

Set the Float3NaNPropRule explicitly for i386. We had no i386-specific behaviour in the old ifdef ladder, so we were using the default "prefer a then b then c" fallback; this is actually the correct per-the-spec handling for i386. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Mess

[PULL 61/72] softfloat: Inline pickNaNMulAdd

From: Richard Henderson Inline pickNaNMulAdd into its only caller. This makes one assert redundant with the immediately preceding IF. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-3-richard.hender...@linaro.org [PMM: keep comment from o

[PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly

Set the FloatInfZeroNaNRule explicitly for the SPARC target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-10-peter.mayd...@linaro.org --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specia

[PULL 44/72] target/hppa: Set default NaN pattern explicitly

Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-39-peter.mayd...@linaro.org --- target/hppa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 3 --- 2

[PULL 57/72] target/hexagon: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for hexagon. Remove the ifdef from parts64_default_nan(); the only remaining unconverted targets all use the default case. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-52-peter.mayd...@linaro.org --- target/

[PULL 68/72] softfloat: Share code between parts_pick_nan cases

From: Richard Henderson Remember if there was an SNaN, and use that to simplify float_2nan_prop_s_{ab,ba} to only the snan component. Then, fall through to the corresponding float_2nan_prop_{ab,ba} case to handle any remaining nans, which must be quiet. Signed-off-by: Richard Henderson Reviewed

[PULL 43/72] target/i386: Set default NaN pattern explicitly

Set the default NaN pattern explicitly, and remove the ifdef from parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-38-peter.mayd...@linaro.org --- target/i386/tcg/fpu_helper.c | 4 fpu/softfloat-specialize.c.inc | 3 ---

[PULL 01/72] hw/net/lan9118: Extract lan9118_phy

From: Bernhard Beschow A very similar implementation of the same device exists in imx_fec. Prepare for a common implementation by extracting a device model into its own files. Some migration state has been moved into the new device model which breaks migration compatibility for the following mac

[PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd

The new implementation of pickNaNMulAdd() will find it convenient to know whether at least one of the three arguments to the muladd was a signaling NaN. We already calculate that in the caller, so pass it in as a new bool have_snan. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Mes

[PULL 55/72] target/sparc: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for SPARC, and remove the ifdef from parts64_default_nan. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-50-peter.mayd...@linaro.org --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc |

[PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed

From: Richard Henderson Move the fractional comparison to the end of the float_2nan_prop_x87 case. This is not required for any other 2nan propagation rule. Reorganize the x87 case itself to break out of the switch when the fractional comparison is not required. Signed-off-by: Richard Henderso

[PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly

Set the FloatInfZeroNaNRule explicitly for the xtensa target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-11-peter.mayd...@linaro.org --- target/xtensa/cpu.c| 2 ++ fpu/softfloat-speci

[PULL 49/72] target/mips: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for MIPS. Note that this is our only target which currently changes the default NaN at runtime (which it was previously doing indirectly when it changed the snan_bit_is_one setting). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20

[PULL 71/72] MAINTAINERS: update email address for Leif Lindholm

From: Leif Lindholm I'm migrating to Qualcomm's new open source email infrastructure, so update my email address, and update the mailmap to match. Signed-off-by: Leif Lindholm Reviewed-by: Leif Lindholm Reviewed-by: Brian Cain Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-D

[PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly

Set the FloatInfZeroNaNRule explicitly for s390, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-7-peter.mayd...@linaro.org --- target/s390x/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc |

[PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c

From: Richard Henderson This function is part of the public interface and is not "specialized" to any target in any way. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20241203203949.483774-7-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat

[PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly

Set the FloatInfZeroNaNRule explicitly for the HPPA target, so we can remove the ifdef from pickNaNMulAdd(). As this is the last target to be converted to explicitly setting the rule, we can remove the fallback code in pickNaNMulAdd() entirely. Signed-off-by: Peter Maydell Reviewed-by: Richard H

[PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly

Set the FloatInfZeroNaNRule explicitly for the loongarch target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-13-peter.mayd...@linaro.org --- target/loongarch/tcg/fpu_helper.c | 5 + fpu/softfloat-specialize.c.inc| 7 +-- 2 files chan

[PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd

IEEE 758 does not define a fixed rule for which NaN to pick as the result if both operands of a 3-operand fused multiply-add operation are NaNs. As a result different architectures have ended up with different rules for propagating NaNs. QEMU currently hardcodes the NaN propagation logic into the

[PULL 53/72] target/rx: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for rx. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-48-peter.mayd...@linaro.org --- target/rx/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 65a74ce720f.

[PULL 39/72] target/arm: Copy entire float_status in is_ebf

From: Richard Henderson Now that float_status has a bunch of fp parameters, it is easier to copy an existing structure than create one from scratch. Begin by copying the structure that corresponds to the FPSR and make only the adjustments required for BFloat16 semantics. Signed-off-by: Richard

[PULL 54/72] target/s390x: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for s390x. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-49-peter.mayd...@linaro.org --- target/s390x/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index

[PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan

We create our 128-bit default NaN by calling parts64_default_nan() and then adjusting the result. We can do the same trick for creating the floatx80 default NaN, which lets us drop a target ifdef. floatx80 is used only by: i386 m68k arm nwfpe old floating-point emulation emulation support

[PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN

From: Richard Henderson Unpacking and repacking the parts may be slightly more work than we did before, but we get to reuse more code. For a code path handling exceptional values, this is an improvement. Signed-off-by: Richard Henderson Message-id: 20241203203949.483774-8-richard.hender...@lin

[PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly

Set the FloatInfZeroNaNRule explicitly for the MIPS target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-9-peter.mayd...@linaro.org --- target/mips/fpu_helper.h | 9 + target/mips/ms

[PULL 60/72] fpu: Remove default handling for dnan_pattern

Now that all our targets have bene converted to explicitly specify their pattern for the default NaN value we can remove the remaining fallback code in parts64_default_nan(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-55-peter.mayd...@linaro.org

[PULL 72/72] MAINTAINERS: Add correct email address for Vikram Garhwal

From: Vikram Garhwal Previously, maintainer role was paused due to inactive email id. Commit id: c009d715721861984c4987bcc78b7ee183e86d75. Signed-off-by: Vikram Garhwal Reviewed-by: Francisco Iglesias Message-id: 20241204184205.12952-1-vikram.garh...@bytedance.com Signed-off-by: Peter Maydell

Re: [PATCH 15/20] tests/functional/aarch64: add tests for FEAT_RME

On 12/11/24 00:04, Thomas Huth wrote: On 10/12/2024 21.43, Alex Bennée wrote: From: Pierrick Bouvier This boot an OP-TEE environment, and launch a nested guest VM inside it using the Realms feature. We do it for virt and sbsa-ref platforms. Signed-off-by: Pierrick Bouvier - v2: - move

[PULL 22/72] target/arm: Set Float3NaNPropRule explicitly

Set the Float3NaNPropRule explicitly for Arm, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-18-peter.mayd...@linaro.org --- target/arm/cpu.c | 5 + fpu/softfloat-specialize.c.inc | 8 +--

[PULL 56/72] target/xtensa: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for xtensa. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-51-peter.mayd...@linaro.org --- target/xtensa/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c in

[PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly

Set the FloatInfZeroNaNRule explicitly for the x86 target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-12-peter.mayd...@linaro.org --- target/i386/tcg/fpu_helper.c | 7 +++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 8 insertio

[PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd

From: Richard Henderson Assign the pointer return value to 'a' directly, rather than going through an intermediary index. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-5-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- fpu

[PULL 48/72] target/m68k: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for m68k. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-43-peter.mayd...@linaro.org --- target/m68k/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 3 insertions(+), 1 deleti

[PULL 04/49] rust: build: move rustc_args.py invocation to qemu-api crate

Only qemu-api needs access to the symbols in config-host.h. Remove the temptation to use them elsewhere by limiting the --cfg arguments to the qemu-api crate. Per-crate invocation of the script will also be needed to add --check-cfg options for each crate's features (when more complex, build-time

[PULL 05/49] rust: build: restrict --cfg generation to only required symbols

Parse the Cargo.toml file, looking for the unexpected_cfgs configuration. When generating --cfg options from the config-host.h file, only use those that are included in the configuration. Signed-off-by: Paolo Bonzini --- rust/qemu-api/meson.build | 2 +- scripts/rust/rustc_args.py | 61 ++

[PULL 06/49] rust: build: generate lint flags from Cargo.toml

Cargo.toml makes it possible to describe the desired lint level settings in a nice format. We can extend this to Meson-built crates, by teaching rustc_args.py to fetch lint and --check-cfg arguments from Cargo.toml. --check-cfg arguments come from the unexpected_cfgs lint as well as crate features

[PULL 58/72] target/riscv: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for riscv. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-53-peter.mayd...@linaro.org --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly

Set the Float3NaNPropRule explicitly for loongarch, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-19-peter.mayd...@linaro.org --- target/loongarch/tcg/fpu_helper.c | 1 + fpu/softfloat-specialize.c.inc

[PULL 02/49] rust: apply --cfg MESON to all crates

We might have more uses for --cfg MESON, even though right now it's only qemu-api that has generated files. Since we're going to add more flags to the add_project_arguments calls for Rust, it makes sense to also add --cfg MESON everywhere. Signed-off-by: Paolo Bonzini --- meson.build

[PULL 07/49] rust: cargo: store desired warning levels in workspace Cargo.toml

An extra benefit of workspaces is that they allow to place lint level settings in a single Cargo.toml; the settings are then inherited by packages in the workspace. Correspondingly, teach rustc_args.py to get the unexpected_cfgs configuration from the workspace Cargo.toml. Note that it is still p

[PULL 64/72] softfloat: Pad array size in pick_nan_muladd

From: Richard Henderson While all indices into val[] should be in [0-2], the mask applied is two bits. To help static analysis see there is no possibility of read beyond the end of the array, pad the array to 4 entries, with the final being (implicitly) NULL. Signed-off-by: Richard Henderson R

[PULL 11/49] rust: build: add "make clippy", "make rustfmt", "make rustdoc"

Abstract common invocations of "cargo", that do not require copying the generated bindgen file or setting up MESON_BUILD_ROOT. In the future these could also do completely without cargo and invoke the underlying programs directly. Reviewed-by: Junjie Mao Signed-off-by: Paolo Bonzini --- rust/m

[PULL 16/49] clock: treat outputs and inputs the same in NamedClockList

Signed-off-by: Paolo Bonzini --- hw/core/qdev-clock.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c index ca65685c04e..2f9d6cb7579 100644 --- a/hw/core/qdev-clock.c +++ b/hw/core/qdev-clock.c @@ -48,14 +48,6 @@ static Nam

[PULL 15/49] clock: clear callback on unparent

Signed-off-by: Paolo Bonzini --- include/hw/clock.h | 8 hw/core/clock.c | 22 +- hw/core/qdev-clock.c | 5 + 3 files changed, 18 insertions(+), 17 deletions(-) diff --git a/include/hw/clock.h b/include/hw/clock.h index eb58599131c..a279bd4ba5e 100644 --

[PULL 14/49] rust/qemu-api: Fix fragment-specifiers in define_property macro

From: Junjie Mao For the matcher of macro, "expr" is used for expressions, while "ident" is used for variable/function names, and "ty" matches types. In define_property macro, $field is a member name of type $state, so it should be defined as "ident", though offset_of! doesn't complain about thi

[PULL 01/49] ci: enable rust in the Debian and Ubuntu system build job

We have fixed all incompatibilities with older versions of rustc and bindgen. Enable Rust on Debian to check that the minimum supported version of Rust is indeed 1.63.0, and 0.60.x for bindgen. Reviewed-by: Pierrick Bouvier Signed-off-by: Paolo Bonzini --- .gitlab-ci.d/buildtest.yml | 4 ++--

[PULL 17/49] clock: inline most of qdev_init_clocklist

Move object creation out of qdev_init_clocklist. The input/output cases are very simple, and the aliases are completely different. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini --- hw/core/qdev-clock.c | 71 +--- 1 file changed, 27 ins

[PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule

Explicitly set a rule in the softfloat tests for propagating NaNs in the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm rule of float_3nan_prop_s_cab. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124

[PULL 00/49] rust, QOM, kvm changes for 2024-12-11

The following changes since commit ae35f033b874c627d81d51070187fbf55f0bf1a7: Update version for v9.2.0 release (2024-12-10 16:20:54 +) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you to fetch changes up to 166e8a1fd15bfa527b25fc15ca3

[PULL 62/72] softfloat: Use goto for default nan case in pick_nan_muladd

From: Richard Henderson Remove "3" as a special case for which and simply branch to return the desired value. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-4-richard.hender...@linaro.org Signed-off-by: Peter Maydell --- fpu/softfloat-p

[PULL 28/49] i386: Replace type_register() with type_register_static()

From: Zhao Liu Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu Signed-off-by: Paolo Bonzini Link: https://lore.kernel.org/r/20241029085934.2799066-11-zhao1@intel.com --- include/hw/i386/pc.h | 4 ++-- target/i386/cpu.

[PULL 26/49] hw/usb: Replace type_register() with type_register_static()

From: Zhao Liu Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu Signed-off-by: Paolo Bonzini Link: https://lore.kernel.org/r/20241029085934.2799066-9-zhao1@intel.com --- hw/usb/hcd-ehci-pci.c | 2 +- hw/usb/hcd-uhci.c

[PULL 22/49] ppc: Replace type_register() with type_register_static()

From: Zhao Liu Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu Signed-off-by: Paolo Bonzini Link: https://lore.kernel.org/r/20241029085934.2799066-5-zhao1@intel.com --- hw/ppc/spapr.c | 2 +- target/ppc/kvm.c | 2 +-

[PULL 20/49] hw/block: Replace type_register() with type_register_static()

From: Zhao Liu Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu Signed-off-by: Paolo Bonzini Link: https://lore.kernel.org/r/20241029085934.2799066-3-zhao1@intel.com --- hw/block/m25p80.c | 2 +- 1 file changed, 1 inse

[PULL 24/49] hw/scsi: Replace type_register() with type_register_static()

From: Zhao Liu Replace type_register() with type_register_static() because\ type_register() will be deprecated. Signed-off-by: Zhao Liu Signed-off-by: Paolo Bonzini Link: https://lore.kernel.org/r/20241029085934.2799066-7-zhao1@intel.com --- hw/scsi/megasas.c | 2 +- hw/scsi/mptsas.c | 2

[PULL 09/49] rust: fix a couple style issues from clippy

These are reported as clippy::semicolon_inside_block and clippy::as_ptr_cast_mut. clippy::semicolon_inside_block can be configured not to lint single-line blocks; just go with the default. Reviewed-by: Junjie Mao Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 8 +-

[PULL 29/49] target/mips: Replace type_register() with type_register_static()

From: Zhao Liu Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu Signed-off-by: Paolo Bonzini Link: https://lore.kernel.org/r/20241029085934.2799066-12-zhao1@intel.com --- target/mips/cpu.c | 2 +- 1 file changed, 1 ins

[PULL 12/49] rust: ci: add job that runs Rust tools

Code checks, as well as documentation generation, are not yet tied to "make check" because they need new version of the Rust toolchain (even nightly in the case of "rustfmt"). Run them in CI using the existing nightly-Rust container. Signed-off-by: Paolo Bonzini --- .gitlab-ci.d/static_checks.y

[PULL 67/72] softfloat: Inline pickNaN

From: Richard Henderson Inline pickNaN into its only caller. This makes one assert redundant with the immediately preceding IF. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-id: 20241203203949.483774-9-richard.hender...@linaro.org Signed-off-by: Peter Maydell -

[PULL 36/49] rust: cell: add BQL-enforcing Cell variant

QEMU objects usually have their pointer shared with the "outside world" very early in their lifetime, for example when they create their MemoryRegions. Because at this point it is not valid anymore to create a &mut reference to the device, individual parts of the device struct must be made mutable

[PULL 13/49] rust: fix doc test syntax

Allow "cargo test --doc" to pass. Reviewed-by: Junjie Mao Signed-off-by: Paolo Bonzini --- rust/qemu-api/src/zeroable.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/rust/qemu-api/src/zeroable.rs b/rust/qemu-api/src/zeroable.rs index 13cdb2ccba5..6125aeed8b4 100644

[PULL 40/49] rust: add a bit operation module

The bindgen supports `static inline` function binding since v0.64.0 as an experimental feature (`--wrap-static-fns`), and stabilizes it after v0.70.0. But the oldest version of bindgen supported by QEMU is v0.60.1, so there's no way to generate the binding for deposit64() which is `static inline`

[PULL 31/49] target/xtensa: Replace type_register() with type_register_static()

From: Zhao Liu Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu Signed-off-by: Paolo Bonzini Link: https://lore.kernel.org/r/20241029085934.2799066-14-zhao1@intel.com --- target/xtensa/helper.c | 2 +- 1 file changed,

[PULL 27/49] hw/virtio: Replace type_register() with type_register_static()

From: Zhao Liu Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu Signed-off-by: Paolo Bonzini Link: https://lore.kernel.org/r/20241029085934.2799066-10-zhao1@intel.com --- hw/virtio/virtio-pci.c | 8 1 file cha

[PULL 25/49] hw/sensor: Replace type_register() with type_register_static()

From: Zhao Liu Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu Signed-off-by: Paolo Bonzini Link: https://lore.kernel.org/r/20241029085934.2799066-8-zhao1@intel.com --- hw/sensor/tmp421.c | 2 +- 1 file changed, 1 ins

[PULL 44/49] rust: qom: move ClassInitImpl to the instance side

Put all traits on the instance struct, which makes it possible to reuse class structs if no new virtual methods or class fields are added. This is almost always the case for devices (because they are leaf classes), which is the primary use case for Rust. This is also simpler: soon we will find the

[PULL 33/49] script/codeconverter/qom_type_info: Deprecate MakeTypeRegisterStatic and MakeTypeRegisterNotStatic

From: Zhao Liu Deprecate MakeTypeRegisterStatic and MakeTypeRegisterNotStatic because type_register() will be deprecated, then only type_register_static() is used. Signed-off-by: Zhao Liu Signed-off-by: Paolo Bonzini Link: https://lore.kernel.org/r/20241029085934.2799066-16-zhao1@intel.com

[PULL 41/49] rust: qom: add default definitions for ObjectImpl

Remove a bunch of duplicate const definitions. Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 6 -- rust/qemu-api/src/definitions.rs | 8 rust/qemu-api/tests/tests.rs | 4 3 files changed, 4 insertions(+), 14 deletions(-) diff --git a/rust/hw/char/pl01

[PULL 47/49] rust: qom: move bridge for TypeInfo functions out of pl011

Allow the ObjectImpl trait to expose Rust functions that avoid raw pointers (though INSTANCE_INIT for example is still unsafe). ObjectImpl::TYPE_INFO adds thunks around the functions in ObjectImpl. While at it, document `TypeInfo`. Reviewed-by: Zhao Liu Signed-off-by: Paolo Bonzini --- rust/hw

[PULL 43/49] rust: qom: convert type_info! macro to an associated const

type_info! is only used in the definition of ObjectImpl::TYPE_INFO, and in fact in all of them. Pull type_info!'s definition into the ObjectImpl trait, thus simplifying the external interface of qemu_api::definitions. Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 6 ++--

[PULL 49/49] rust: qom: change the parent type to an associated type

Avoid duplicated code to retrieve the QOM type strings from the Rust type. Reviewed-by: Zhao Liu Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 6 -- rust/qemu-api/src/definitions.rs | 12 rust/qemu-api/tests/tests.rs | 3 +-- 3 files changed, 9 inser

[PULL 59/72] target/tricore: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for tricore. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-54-peter.mayd...@linaro.org --- target/tricore/helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/tricore/helper.c b/target/tricor

[PULL 23/49] hw/rtc: Replace type_register() with type_register_static()

From: Zhao Liu Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu Signed-off-by: Paolo Bonzini Link: https://lore.kernel.org/r/20241029085934.2799066-6-zhao1@intel.com --- hw/rtc/m48t59-isa.c | 2 +- hw/rtc/m48t59.c

[PULL 34/49] qom/object: Remove type_register()

From: Zhao Liu At present, type_register() and type_register_static() are identical, although their documentation expects the *_static variant to accept the Typeinfo with the strings that have the static lifetime. However, the code implementation doesn't have any check or guarantee for static li

[PULL 45/72] target/alpha: Set default NaN pattern explicitly

Set the default NaN pattern explicitly for the alpha target. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-40-peter.mayd...@linaro.org --- target/alpha/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/alpha/cpu.c b/target/alpha/c

[PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd

If the target sets default_nan_mode then we're always going to return the default NaN, and pickNaNMulAdd() no longer has any side effects. For consistency with pickNaN(), check for default_nan_mode before calling pickNaNMulAdd(). When we convert pickNaNMulAdd() to allow runtime selection of the Na

[PATCH v3 08/69] target/arm: Convert CLZ, CLS to decodetree

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 72 ++ target/arm/tcg/a64.decode | 3 ++ 2 files changed, 33 insertions(+), 42 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tc

[PATCH v3 03/69] target/arm: Convert LSLV, LSRV, ASRV, RORV to decodetree

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 46 -- target/arm/tcg/a64.decode | 4 +++ 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/t

[PULL 30/49] target/sparc: Replace type_register() with type_register_static()

From: Zhao Liu Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu Signed-off-by: Paolo Bonzini Link: https://lore.kernel.org/r/20241029085934.2799066-13-zhao1@intel.com --- target/sparc/cpu.c | 2 +- 1 file changed, 1 in

[PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly

Set the Float3NaNPropRule explicitly for s390x, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20241202131347.498124-21-peter.mayd...@linaro.org --- target/s390x/cpu.c | 1 + fpu/softfloat-specialize.c.inc | 2 -- 2

[PULL 19/49] arm: Replace type_register() with type_register_static()

From: Zhao Liu Replace type_register() with type_register_static() because type_register() will be deprecated. Signed-off-by: Zhao Liu Signed-off-by: Paolo Bonzini Link: https://lore.kernel.org/r/20241029085934.2799066-2-zhao1@intel.com --- hw/arm/armsse.c| 2 +- hw/arm/smmuv3.c|

[PATCH v3 01/69] target/arm: Add section labels for "Data Processing (register)"

At the same time, use ### to separate 3rd-level sections. We already use ### for 4.1.92 Data Processing (immediate), but not the two following two third-level sections: 4.1.93 Branches, and 4.1.94 Loads and stores. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/

[PATCH v3 54/69] target/arm: Convert FABS, FNEG (vector) to decodetree

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 54 +++--- target/arm/tcg/a64.decode | 7 + 2 files changed, 31 insertions(+), 30 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/tran

[PATCH v3 20/69] target/arm: Introduce fp_access_check_scalar_hsd

Provide a simple way to check for float64, float32, and float16 support, as well as the fpu enabled. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 62 ++ 1 file changed, 32 insertions(+), 30 deletions(-) diff --

[PATCH v3 57/69] target/arm: Convert FCVT* (vector, integer) scalar to decodetree

Arm silliness with naming, the scalar insns described as part of the vector instructions, as separate from the "regular" scalar insns which output to general registers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 133 ++---

[PULL 08/49] rust: build: move strict lints handling to rustc_args.py

Make Cargo use unknown_lints = "allow" as well. This is more future proof as we might add new lints to rust/Cargo.toml that are not supported by older versions of rustc or clippy. Signed-off-by: Paolo Bonzini --- meson.build| 12 rust/Cargo.toml| 6

[PATCH v3 66/69] target/arm: Convert FRECPE, FRECPX, FRSQRTE to decodetree

Remove disas_simd_scalar_two_reg_misc and disas_simd_two_reg_misc_fp16 as these were the last insns decoded by those functions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 329 - target/arm/tcg/a64.decode

[PATCH v3 32/69] target/arm: Convert handle_fpfpcvt to decodetree

This includes SCVTF, UCVTF, FCVT{N,P,M,Z,A}{S,U}. Remove disas_fp_fixed_conv as those were the last insns decoded by that function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 391 ++--- target/arm/tcg/a64.decode

[PATCH v3 60/69] target/arm: Convert [US]CVTF (vector, fixed-point) scalar to decodetree

Remove disas_simd_scalar_shift_imm as these were the last insns decoded by that function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 47 -- target/arm/tcg/a64.decode | 8 ++ 2 files changed, 8 insert

Re: [PATCH v2 1/1] target/riscv: add VILL field for vtype register macro definition

On 2024/12/11 23:55, Richard Henderson wrote: On 12/11/24 09:48, Chao Liu wrote: Signed-off-by: Chao Liu ---   target/riscv/cpu.h | 3 ++-   1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 284b112821..0d74ee4581 100644 --- a/target/risc

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