Now that all our targets have bene converted to explicitly specify
their pattern for the default NaN value we can remove the remaining
fallback code in parts64_default_nan().
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20241202131347.498124-55-peter.mayd...@linaro.org
---
fpu/softfloat-specialize.c.inc | 14 --------------
1 file changed, 14 deletions(-)
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index 5954a6213b9..e075c47889a 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -135,20 +135,6 @@ static void parts64_default_nan(FloatParts64 *p,
float_status *status)
uint64_t frac;
uint8_t dnan_pattern = status->default_nan_pattern;
- if (dnan_pattern == 0) {
- /*
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
- * do not have floating-point.
- */
- if (snan_bit_is_one(status)) {
- /* sign bit clear, set all frac bits other than msb */
- dnan_pattern = 0b00111111;
- } else {
- /* sign bit clear, set frac msb */
- dnan_pattern = 0b01000000;
- }
- }
assert(dnan_pattern != 0);
sign = dnan_pattern >> 7;
--
2.34.1
