Arm silliness with naming, the scalar insns described
as part of the vector instructions, as separate from
the "regular" scalar insns which output to general registers.
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/arm/tcg/translate-a64.c | 133 ++++++++++++++-------------------
target/arm/tcg/a64.decode | 30 ++++++++
2 files changed, 86 insertions(+), 77 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 0f924b07dc..71f1d6f778 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8674,6 +8674,16 @@ static void do_fcvt_scalar(DisasContext *s, MemOp out,
MemOp esz,
tcg_shift, tcg_fpstatus);
tcg_gen_extu_i32_i64(tcg_out, tcg_single);
break;
+ case MO_16 | MO_SIGN:
+ gen_helper_vfp_toshh(tcg_single, tcg_single,
+ tcg_shift, tcg_fpstatus);
+ tcg_gen_extu_i32_i64(tcg_out, tcg_single);
+ break;
+ case MO_16:
+ gen_helper_vfp_touhh(tcg_single, tcg_single,
+ tcg_shift, tcg_fpstatus);
+ tcg_gen_extu_i32_i64(tcg_out, tcg_single);
+ break;
default:
g_assert_not_reached();
}
@@ -8717,6 +8727,42 @@ TRANS(FCVTZU_g, do_fcvt_g, a, FPROUNDING_ZERO, false)
TRANS(FCVTAS_g, do_fcvt_g, a, FPROUNDING_TIEAWAY, true)
TRANS(FCVTAU_g, do_fcvt_g, a, FPROUNDING_TIEAWAY, false)
+/*
+ * FCVT* (vector), scalar version.
+ * Which sounds weird, but really just means output to fp register
+ * instead of output to general register. Input and output element
+ * size are always equal.
+ */
+static bool do_fcvt_f(DisasContext *s, arg_fcvt *a,
+ ARMFPRounding rmode, bool is_signed)
+{
+ TCGv_i64 tcg_int;
+ int check = fp_access_check_scalar_hsd(s, a->esz);
+
+ if (check <= 0) {
+ return check == 0;
+ }
+
+ tcg_int = tcg_temp_new_i64();
+ do_fcvt_scalar(s, a->esz | (is_signed ? MO_SIGN : 0),
+ a->esz, tcg_int, a->shift, a->rn, rmode);
+
+ clear_vec(s, a->rd);
+ write_vec_element(s, tcg_int, a->rd, 0, a->esz);
+ return true;
+}
+
+TRANS(FCVTNS_f, do_fcvt_f, a, FPROUNDING_TIEEVEN, true)
+TRANS(FCVTNU_f, do_fcvt_f, a, FPROUNDING_TIEEVEN, false)
+TRANS(FCVTPS_f, do_fcvt_f, a, FPROUNDING_POSINF, true)
+TRANS(FCVTPU_f, do_fcvt_f, a, FPROUNDING_POSINF, false)
+TRANS(FCVTMS_f, do_fcvt_f, a, FPROUNDING_NEGINF, true)
+TRANS(FCVTMU_f, do_fcvt_f, a, FPROUNDING_NEGINF, false)
+TRANS(FCVTZS_f, do_fcvt_f, a, FPROUNDING_ZERO, true)
+TRANS(FCVTZU_f, do_fcvt_f, a, FPROUNDING_ZERO, false)
+TRANS(FCVTAS_f, do_fcvt_f, a, FPROUNDING_TIEAWAY, true)
+TRANS(FCVTAU_f, do_fcvt_f, a, FPROUNDING_TIEAWAY, false)
+
static bool trans_FJCVTZS(DisasContext *s, arg_FJCVTZS *a)
{
if (!dc_isar_feature(aa64_jscvt, s)) {
@@ -9776,10 +9822,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext
*s, uint32_t insn)
int opcode = extract32(insn, 12, 5);
int size = extract32(insn, 22, 2);
bool u = extract32(insn, 29, 1);
- bool is_fcvt = false;
- int rmode;
- TCGv_i32 tcg_rmode;
- TCGv_ptr tcg_fpstatus;
switch (opcode) {
case 0xc ... 0xf:
@@ -9824,15 +9866,8 @@ static void disas_simd_scalar_two_reg_misc(DisasContext
*s, uint32_t insn)
case 0x5b: /* FCVTMU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
- is_fcvt = true;
- rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
- break;
case 0x1c: /* FCVTAS */
case 0x5c: /* FCVTAU */
- /* TIEAWAY doesn't fit in the usual rounding mode encoding */
- is_fcvt = true;
- rmode = FPROUNDING_TIEAWAY;
- break;
case 0x56: /* FCVTXN, FCVTXN2 */
default:
unallocated_encoding(s);
@@ -9851,59 +9886,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext
*s, uint32_t insn)
unallocated_encoding(s);
return;
}
-
- if (!fp_access_check(s)) {
- return;
- }
-
- if (is_fcvt) {
- tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
- tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
- } else {
- tcg_fpstatus = NULL;
- tcg_rmode = NULL;
- }
-
- if (size == 3) {
- TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
- TCGv_i64 tcg_rd = tcg_temp_new_i64();
-
- handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus);
- write_fp_dreg(s, rd, tcg_rd);
- } else {
- TCGv_i32 tcg_rn = tcg_temp_new_i32();
- TCGv_i32 tcg_rd = tcg_temp_new_i32();
-
- read_vec_element_i32(s, tcg_rn, rn, 0, size);
-
- switch (opcode) {
- case 0x1a: /* FCVTNS */
- case 0x1b: /* FCVTMS */
- case 0x1c: /* FCVTAS */
- case 0x3a: /* FCVTPS */
- case 0x3b: /* FCVTZS */
- gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_constant_i32(0),
- tcg_fpstatus);
- break;
- case 0x5a: /* FCVTNU */
- case 0x5b: /* FCVTMU */
- case 0x5c: /* FCVTAU */
- case 0x7a: /* FCVTPU */
- case 0x7b: /* FCVTZU */
- gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_constant_i32(0),
- tcg_fpstatus);
- break;
- default:
- case 0x7: /* SQABS, SQNEG */
- g_assert_not_reached();
- }
-
- write_fp_sreg(s, rd, tcg_rd);
- }
-
- if (is_fcvt) {
- gen_restore_rmode(tcg_rmode, tcg_fpstatus);
- }
+ g_assert_not_reached();
}
/* AdvSIMD shift by immediate
@@ -10391,30 +10374,26 @@ static void disas_simd_two_reg_misc_fp16(DisasContext
*s, uint32_t insn)
TCGv_i32 tcg_res = tcg_temp_new_i32();
switch (fpop) {
- case 0x1a: /* FCVTNS */
- case 0x1b: /* FCVTMS */
- case 0x1c: /* FCVTAS */
- case 0x3a: /* FCVTPS */
- case 0x3b: /* FCVTZS */
- gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
- break;
case 0x3d: /* FRECPE */
gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x3f: /* FRECPX */
gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
+ case 0x7d: /* FRSQRTE */
+ gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
+ break;
+ default:
+ case 0x1a: /* FCVTNS */
+ case 0x1b: /* FCVTMS */
+ case 0x1c: /* FCVTAS */
+ case 0x3a: /* FCVTPS */
+ case 0x3b: /* FCVTZS */
case 0x5a: /* FCVTNU */
case 0x5b: /* FCVTMU */
case 0x5c: /* FCVTAU */
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
- gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
- break;
- case 0x7d: /* FRSQRTE */
- gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
- break;
- default:
g_assert_not_reached();
}
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index 5e02144f65..f7fcc32adc 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1652,6 +1652,36 @@ UQXTN_s 0111 1110 ..1 00001 01001 0 ..... .....
@rr_e
FCVTXN_s 0111 1110 011 00001 01101 0 ..... ..... @rr_s
+@icvt_h . ....... .. ...... ...... rn:5 rd:5 \
+ &fcvt sf=0 esz=1 shift=0
+@icvt_sd . ....... .. ...... ...... rn:5 rd:5 \
+ &fcvt sf=0 esz=%esz_sd shift=0
+
+FCVTNS_f 0101 1110 011 11001 10101 0 ..... ..... @icvt_h
+FCVTNS_f 0101 1110 0.1 00001 10101 0 ..... ..... @icvt_sd
+FCVTNU_f 0111 1110 011 11001 10101 0 ..... ..... @icvt_h
+FCVTNU_f 0111 1110 0.1 00001 10101 0 ..... ..... @icvt_sd
+
+FCVTPS_f 0101 1110 111 11001 10101 0 ..... ..... @icvt_h
+FCVTPS_f 0101 1110 1.1 00001 10101 0 ..... ..... @icvt_sd
+FCVTPU_f 0111 1110 111 11001 10101 0 ..... ..... @icvt_h
+FCVTPU_f 0111 1110 1.1 00001 10101 0 ..... ..... @icvt_sd
+
+FCVTMS_f 0101 1110 011 11001 10111 0 ..... ..... @icvt_h
+FCVTMS_f 0101 1110 0.1 00001 10111 0 ..... ..... @icvt_sd
+FCVTMU_f 0111 1110 011 11001 10111 0 ..... ..... @icvt_h
+FCVTMU_f 0111 1110 0.1 00001 10111 0 ..... ..... @icvt_sd
+
+FCVTZS_f 0101 1110 111 11001 10111 0 ..... ..... @icvt_h
+FCVTZS_f 0101 1110 1.1 00001 10111 0 ..... ..... @icvt_sd
+FCVTZU_f 0111 1110 111 11001 10111 0 ..... ..... @icvt_h
+FCVTZU_f 0111 1110 1.1 00001 10111 0 ..... ..... @icvt_sd
+
+FCVTAS_f 0101 1110 011 11001 11001 0 ..... ..... @icvt_h
+FCVTAS_f 0101 1110 0.1 00001 11001 0 ..... ..... @icvt_sd
+FCVTAU_f 0111 1110 011 11001 11001 0 ..... ..... @icvt_h
+FCVTAU_f 0111 1110 0.1 00001 11001 0 ..... ..... @icvt_sd
+
# Advanced SIMD two-register miscellaneous
SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e
--
2.43.0
