Re: [PATCH v2] virtio: kconfig: memory devices are PCI only

2024-09-26 Thread David Hildenbrand
On 25.09.24 09:39, Pankaj Gupta wrote: Virtio memory devices rely on PCI BARs to expose the contents of memory. Because of this they cannot be used (yet) with virtio-mmio or virtio-ccw. In fact the code that is common to virtio-mem and virtio-pmem, which is in hw/virtio/virtio-md-pci.c, is only i

Re: [PATCH] softmmu: Support concurrent bounce buffers

2024-09-26 Thread Michael Tokarev
25.09.2024 13:23, Mattias Nissler wrote: On Wed, Sep 25, 2024 at 12:03 PM Michael Tokarev wrote: .. So, the issue has now become CVE-2024-8612 (information leak), with this commit (v9.1.0-134-g637b0aa139) being the fix. Interesting. IIUC, this is triggered by device implementations calling d

[PATCH] MAINTAINERS: Add myself as maintainer of e500 machines

2024-09-26 Thread Bernhard Beschow
Signed-off-by: Bernhard Beschow --- MAINTAINERS | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index ffacd60f40..0a191a03db 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1430,8 +1430,9 @@ F: hw/pci-host/ppc4xx_pci.c F: tests/functional/test_p

Re: [PATCH] softmmu: Support concurrent bounce buffers

2024-09-26 Thread Michael S. Tsirkin
On Thu, Sep 26, 2024 at 10:58:57AM +0300, Michael Tokarev wrote: > 25.09.2024 13:23, Mattias Nissler wrote: > > On Wed, Sep 25, 2024 at 12:03 PM Michael Tokarev wrote: > .. > > > So, the issue has now become CVE-2024-8612 (information leak), with this > > > commit (v9.1.0-134-g637b0aa139) being th

Re: [PATCH v1 10/14] s390x/pv: check initial, not maximum RAM size

2024-09-26 Thread David Hildenbrand
On 24.09.24 22:17, David Hildenbrand wrote: On 24.09.24 18:22, Nina Schoetterl-Glausch wrote: On Tue, 2024-09-10 at 19:58 +0200, David Hildenbrand wrote: We actually want to check the available RAM, not the maximum RAM size. Signed-off-by: David Hildenbrand Reviewed-by: Nina Schoetterl-Glau

Re: [PATCH 00/23] E500 Cleanup

2024-09-26 Thread Bernhard Beschow
Am 24. September 2024 08:33:26 UTC schrieb "Cédric Le Goater" : >On 9/23/24 23:25, Bernhard Beschow wrote: >> >> >> >> Am 23. September 2024 20:23:54 UTC schrieb "Cédric Le Goater" >> : >>> Hello Bernhard, >> >> Hi Cédric, >> >>> >>> On 9/23/24 11:29, Bernhard Beschow wrote: This ser

Re: [PATCH v6] ptp: Add support for the AMZNC10C 'vmclock' device

2024-09-26 Thread Paolo Abeni
On 9/20/24 11:32, David Woodhouse wrote: From: David Woodhouse The vmclock device addresses the problem of live migration with precision clocks. The tolerances of a hardware counter (e.g. TSC) are typically around ±50PPM. A guest will use NTP/PTP/PPS to discipline that counter against an extern

Re: [PATCH v3 00/17] intel_iommu: Enable stage-1 translation for emulated device

2024-09-26 Thread Duan, Zhenzhong
Hi All, Kindly ping, more comments are appreciated:) Thanks Zhenzhong On 9/11/2024 1:22 PM, Zhenzhong Duan wrote: Hi, Per Jason Wang's suggestion, iommufd nesting series[1] is split into "Enable stage-1 translation for emulated device" series and "Enable stage-1 translation for passthrough de

Re: [PULL 00/22] Trivial patches for 2024-09-20

2024-09-26 Thread Peter Maydell
On Fri, 20 Sept 2024 at 08:42, Michael Tokarev wrote: > > The following changes since commit 01dc65a3bc262ab1bec8fe89775e9bbfa627becb: > > Merge tag 'pull-target-arm-20240919' of > https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-09-19 > 14:15:15 +0100) > > are available in t

Re: [PATCH v1 12/14] s390x: introduce s390_get_max_pagesize()

2024-09-26 Thread David Hildenbrand
On 10.09.24 19:58, David Hildenbrand wrote: Let's add a way to return the value (successfully) set via s390_set_max_pagesize() previously. This will be helpful to reject hotplugged memory devices that would exceed this initially set page size. Signed-off-by: David Hildenbrand --- I'll send a

[PATCH 0/2] Xen: Update sector-size handling in block backend

2024-09-26 Thread Anthony PERARD
The specification have been clarified regarding what "sector" is in Xen PV block protocol by Xen commit 221f2748e8da ("blkif: reconcile protocol specification with in-use implementations") and "feature-large-sector-size" have been removed. https://xenbits.xenproject.org/gitweb/?p=xen.git;a=commit;

Re: [PATCH v6] ptp: Add support for the AMZNC10C 'vmclock' device

2024-09-26 Thread David Woodhouse
On Thu, 2024-09-26 at 11:22 +0200, Paolo Abeni wrote: > > Please have a better run at checkpatch before your next submission, > there are still a few ones - most relevant white-space damage. Oops, apparently I missed one. Sorry about that. I'll also add a MAINTAINERS entry, just to make checkpa

[PATCH 1/2] include: update Xen public headers io/blkif.h

2024-09-26 Thread Anthony PERARD
Signed-off-by: Anthony PERARD --- include/hw/xen/interface/io/blkif.h | 52 + 1 file changed, 39 insertions(+), 13 deletions(-) diff --git a/include/hw/xen/interface/io/blkif.h b/include/hw/xen/interface/io/blkif.h index 22f1eef0c0..9b00d633d3 100644 --- a/include/hw

[PATCH 2/2] hw/block/xen-block: Update sector-size handling

2024-09-26 Thread Anthony PERARD
The use of "feature-large-sector-size" have been removed from the protocol, as it hasn't been evenly implemented across all backend and frontend. Linux for example will happily expose "sector-size" != 512 even when "feature-large-sector-size" hasn't been set by the frontend. The specification have

[PATCH] hw/audio/virtio-snd: Remove unnecessary "exec/tswap.h" header

2024-09-26 Thread Philippe Mathieu-Daudé
We were including the "exec/tswap.h" header to get target_words_bigendian() declaration, but since commit a276ec8e26 ("hw/audio/virtio-snd: Always use little endian audio format") removed this method call, we don't need this header anymore. Signed-off-by: Philippe Mathieu-Daudé --- hw/audio/virt

Re: [PATCH v2] tests/qemu-iotests/testenv: Use the "r2d" machine for sh4

2024-09-26 Thread Michael Tokarev
25.09.2024 10:24, Thomas Huth wrote: Commit 0ea0538fae516f9b4 removed the default machine of the sh4 binaries, so a lot of iotests are failing now without such a default machine. Teach the iotest harness to use the "r2d" machine instead to fix this problem. Signed-off-by: Thomas Huth --- v2:

Re: [PATCH v2] tests/qemu-iotests/testenv: Use the "r2d" machine for sh4

2024-09-26 Thread Thomas Huth
On 26/09/2024 12.24, Michael Tokarev wrote: 25.09.2024 10:24, Thomas Huth wrote: Commit 0ea0538fae516f9b4 removed the default machine of the sh4 binaries, so a lot of iotests are failing now without such a default machine. Teach the iotest harness to use the "r2d" machine instead to fix this pro

[PATCH] Remove the unused sh4eb target

2024-09-26 Thread Thomas Huth
Since the "shix" machine has been removed, the "r2d" machine is the only machine that is still available for the sh4 and sh4eb targets. However, the "r2d" machine apparently does not work in big endian mode, see here: https://lore.kernel.org/qemu-devel/87a5fwjjew.wl-ys...@users.sourceforge.jp/ S

Re: [PATCH v2] qemu-timer: Remove unused timer functions

2024-09-26 Thread Bernhard Beschow
Am 19. September 2024 14:41:24 UTC schrieb d...@treblig.org: >From: "Dr. David Alan Gilbert" > >qemu_clock_get_main_loop_timerlist and timerlist_get_clock have been >unused since they were originally added in > ff83c66ecc ("aio / timers: Split QEMUClock into QEMUClock and QEMUTimerList") > >Remov

[PATCH v3 4/6] hw/gpio/aspeed: Fix clear incorrect interrupt status for GPIO index mode

2024-09-26 Thread Jamin Lin via
The interrupt status field is W1C, where a set bit on read indicates an interrupt is pending. If the bit extracted from data is set it should clear the corresponding bit in group_value. However, if the extracted bit is clear then the value of the corresponding bit in group_value should be unchanged

[PATCH v13 04/10] scsi/util: add helper functions for persistent reservation types conversion

2024-09-26 Thread Changqi Lu
This commit introduces two helper functions that facilitate the conversion between the persistent reservation types used in the SCSI protocol and those used in the block layer. Signed-off-by: Changqi Lu Signed-off-by: zhenwei pi Reviewed-by: Stefan Hajnoczi --- include/scsi/utils.h | 8 +

[PATCH v3 5/6] hw/gpio/aspeed: Add AST2700 support

2024-09-26 Thread Jamin Lin via
AST2700 integrates two set of Parallel GPIO Controller with maximum 212 control pins, which are 27 groups. (H, exclude pin: H7 H6 H5 H4) In the previous design of ASPEED SOCs, one register is used for setting one function for one set which are 32 pins and 4 groups. ex: GPIO000 is used for setting

[PATCH v13 02/10] block/raw: add persistent reservation in/out driver

2024-09-26 Thread Changqi Lu
Add persistent reservation in/out operations for raw driver. The following methods are implemented: bdrv_co_pr_read_keys, bdrv_co_pr_read_reservation, bdrv_co_pr_register, bdrv_co_pr_reserve, bdrv_co_pr_release, bdrv_co_pr_clear and bdrv_co_pr_preempt. Signed-off-by: Changqi Lu Signed-off-by: zhe

[PATCH v3 2/6] hw/gpio/aspeed: Support to set the different memory size

2024-09-26 Thread Jamin Lin via
According to the datasheet of ASPEED SOCs, a GPIO controller owns 4KB of register space for AST2700, AST2500, AST2400 and AST1030; owns 2KB of register space for AST2600 1.8v and owns 2KB of register space for AST2600 3.3v. It set the memory region size 2KB by default and it does not compatible re

[PATCH v13 09/10] hw/nvme: add reservation protocal command

2024-09-26 Thread Changqi Lu
Add reservation acquire, reservation register, reservation release and reservation report commands in the nvme device layer. By introducing these commands, this enables the nvme device to perform reservation-related tasks, including querying keys, querying reservation status, registering reservati

[PATCH v13 05/10] hw/scsi: add persistent reservation in/out api for scsi device

2024-09-26 Thread Changqi Lu
Add persistent reservation in/out operations in the SCSI device layer. By introducing the persistent reservation in/out api, this enables the SCSI device to perform reservation-related tasks, including querying keys, querying reservation status, registering reservation keys, initiating and releasin

[PATCH v3 1/6] hw/gpio/aspeed: Fix coding style

2024-09-26 Thread Jamin Lin via
Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin --- hw/gpio/aspeed_gpio.c | 6 +++--- include/hw/gpio/aspeed_gpio.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index 71756664dd..00fb72a509 100644

[PATCH v13 00/10] Support persistent reservation operations

2024-09-26 Thread Changqi Lu
Hi, Patch v13 has been modified, thanks to Stefan for the code review. v12->v13: - Fix byte swaps at hw/nvme/ctrl.c. v11->v12: - Fixed endian conversion during command parsing; - Add the maximum number of keys, currently limited to 128. v10->v11: - Before executing the pr operation, check wheth

[PATCH v3 3/6] hw/gpio/aspeed: Support different memory region ops

2024-09-26 Thread Jamin Lin via
It set "aspeed_gpio_ops" struct which containing read and write callbacks to be used when I/O is performed on the GPIO region. Besides, in the previous design of ASPEED SOCs, one register is used for setting one function for 32 GPIO pins. ex: GPIO000 is used for setting data value for GPIO A, B, C

[PATCH v3 0/6] Support GPIO for AST2700

2024-09-26 Thread Jamin Lin via
v1: Support GPIO for AST2700 v2: Fix clear incorrect interrupt status and adds reviewer suggestions v3: remove nested conditionals and adds reviewer suggestions Jamin Lin (6): hw/gpio/aspeed: Fix coding style hw/gpio/aspeed: Support to set the different memory size hw/gpio/aspeed: Support di

[PATCH v13 06/10] block/nvme: add reservation command protocol constants

2024-09-26 Thread Changqi Lu
Add constants for the NVMe persistent command protocol. The constants include the reservation command opcode and reservation type values defined in section 7 of the NVMe 2.0 specification. Reviewed-by: Stefan Hajnoczi Signed-off-by: Changqi Lu Signed-off-by: zhenwei pi --- include/block/nvme.h

[PATCH v13 07/10] hw/nvme: add helper functions for converting reservation types

2024-09-26 Thread Changqi Lu
This commit introduces two helper functions that facilitate the conversion between the reservation types used in the NVME protocol and those used in the block layer. Reviewed-by: Klaus Jensen Reviewed-by: Stefan Hajnoczi Signed-off-by: Changqi Lu Signed-off-by: zhenwei pi --- hw/nvme/nvme.h |

[PATCH v13 10/10] block/iscsi: add persistent reservation in/out driver

2024-09-26 Thread Changqi Lu
Add persistent reservation in/out operations for iscsi driver. The following methods are implemented: bdrv_co_pr_read_keys, bdrv_co_pr_read_reservation, bdrv_co_pr_register, bdrv_co_pr_reserve, bdrv_co_pr_release, bdrv_co_pr_clear and bdrv_co_pr_preempt. Signed-off-by: Changqi Lu Signed-off-by: z

[PATCH v13 01/10] block: add persistent reservation in/out api

2024-09-26 Thread Changqi Lu
Add persistent reservation in/out operations at the block level. The following operations are included: - read_keys:retrieves the list of registered keys. - read_reservation: retrieves the current reservation status. - register: registers a new reservation key. - reserve:

[PATCH v13 03/10] scsi/constant: add persistent reservation in/out protocol constants

2024-09-26 Thread Changqi Lu
Add constants for the persistent reservation in/out protocol in the scsi/constant module. The constants include the persistent reservation command, type, and scope values defined in sections 6.13 and 6.14 of the SCSI Primary Commands-4 (SPC-4) specification. Signed-off-by: Changqi Lu Signed-off-b

[PATCH v13 08/10] hw/nvme: enable ONCS and rescap function

2024-09-26 Thread Changqi Lu
This commit enables ONCS to support the reservation function at the controller level. Also enables rescap function in the namespace by detecting the supported reservation function in the backend driver. Reviewed-by: Klaus Jensen Signed-off-by: Changqi Lu Signed-off-by: zhenwei pi Reviewed-by: S

[PATCH v3 6/6] aspeed/soc: Support GPIO for AST2700

2024-09-26 Thread Jamin Lin via
Add GPIO model for AST2700 GPIO support. The GPIO controller registers base address is start at 0x14C0_B000 and its address space is 0x1000. The AST2700 GPIO controller interrupt is connected to GICINT130_INTC at bit 18. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 18 +++-

Re: [PATCH v3 1/6] hw/gpio/aspeed: Fix coding style

2024-09-26 Thread Cédric Le Goater
On 9/26/24 09:45, Jamin Lin wrote: Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Thanks, C. --- hw/gpio/aspeed_gpio.c | 6 +++--- include/hw/gpio/aspeed_gpio.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff

Re: [PATCH V3] arm/kvm: add support for MTE

2024-09-26 Thread Gustavo Romero
Hi Cornelia and Ganapatrao, On 9/25/24 14:54, Cornelia Huck wrote: On Fri, Sep 20 2024, Ganapatrao Kulkarni wrote: Mostly nit-picking below, otherwise LGTM. Extend the 'mte' property for the virt machine to cover KVM as well. For KVM, we don't allocate tag memory, but instead enable the cap

Re: [PATCH v3 6/6] aspeed/soc: Support GPIO for AST2700

2024-09-26 Thread Cédric Le Goater
On 9/26/24 09:45, Jamin Lin wrote: Add GPIO model for AST2700 GPIO support. The GPIO controller registers base address is start at 0x14C0_B000 and its address space is 0x1000. The AST2700 GPIO controller interrupt is connected to GICINT130_INTC at bit 18. Signed-off-by: Jamin Lin ---> hw/arm

Re: [PATCH v3 0/6] Support GPIO for AST2700

2024-09-26 Thread Cédric Le Goater
Hello Jamin, On 9/26/24 09:45, Jamin Lin wrote: v1: Support GPIO for AST2700 v2: Fix clear incorrect interrupt status and adds reviewer suggestions v3: remove nested conditionals and adds reviewer suggestions Jamin Lin (6): hw/gpio/aspeed: Fix coding style hw/gpio/aspeed: Support to set t

Re: [PATCH v3 3/6] hw/gpio/aspeed: Support different memory region ops

2024-09-26 Thread Cédric Le Goater
On 9/26/24 09:45, Jamin Lin wrote: It set "aspeed_gpio_ops" struct which containing read and write callbacks to be used when I/O is performed on the GPIO region. Besides, in the previous design of ASPEED SOCs, one register is used for setting one function for 32 GPIO pins. ex: GPIO000 is used fo

Re: Rust BoF and maintainer minutes and planning the roadmap to Rust

2024-09-26 Thread Daniel P . Berrangé
On Thu, Sep 26, 2024 at 03:23:11PM +0100, Alex Bennée wrote: > During the various conversations I didn't hear anyone speak against the > proposed migration although some concerns where raised about review and > knowledge gaps. Yep, this apparent broad acceptance (or at least tolerance) for use of

Re: [PATCH] hw/audio/virtio-snd: Remove unnecessary "exec/tswap.h" header

2024-09-26 Thread Manos Pitsidianakis
On Thu, 26 Sep 2024 13:21, Philippe Mathieu-Daudé wrote: We were including the "exec/tswap.h" header to get target_words_bigendian() declaration, but since commit a276ec8e26 ("hw/audio/virtio-snd: Always use little endian audio format") removed this method call, we don't need this header anymore

[PATCH v6 03/16] backends/igvm: Add IGVM loader and configuration

2024-09-26 Thread Roy Hopkins
Adds an IGVM loader to QEMU which processes a given IGVM file and applies the directives within the file to the current guest configuration. The IGVM loader can be used to configure both confidential and non-confidential guests. For confidential guests, the ConfidentialGuestSupport object for the

[PATCH v6 01/16] meson: Add optional dependency on IGVM library

2024-09-26 Thread Roy Hopkins
The IGVM library allows Independent Guest Virtual Machine files to be parsed and processed. IGVM files are used to configure guest memory layout, initial processor state and other configuration pertaining to secure virtual machines. This adds the --enable-igvm configure option, enabled by default,

[PATCH v6 11/16] docs/interop/firmware.json: Add igvm to FirmwareDevice

2024-09-26 Thread Roy Hopkins
Create an enum entry within FirmwareDevice for 'igvm' to describe that an IGVM file can be used to map firmware into memory as an alternative to pre-existing firmware devices. Signed-off-by: Roy Hopkins Acked-by: Michael S. Tsirkin Reviewed-by: Stefano Garzarella --- docs/interop/firmware.json

[PATCH v6 09/16] i386/sev: Implement ConfidentialGuestSupport functions for SEV

2024-09-26 Thread Roy Hopkins
The ConfidentialGuestSupport object defines a number of virtual functions that are called during processing of IGVM directives to query or configure initial guest state. In order to support processing of IGVM files, these functions need to be implemented by relevant isolation hardware support code

[PATCH v6 16/16] sev: Provide sev_features flags from IGVM VMSA to KVM_SEV_INIT2

2024-09-26 Thread Roy Hopkins
IGVM files can contain an initial VMSA that should be applied to each vcpu as part of the initial guest state. The sev_features flags are provided as part of the VMSA structure. However, KVM only allows sev_features to be set during initialization and not as the guest is being prepared for launch.

[PATCH v6 00/16] Introduce support for IGVM files

2024-09-26 Thread Roy Hopkins
Here is v6 of the set of patches to add support for IGVM files to QEMU. This is based on commit a5dd9ee060 of qemu. This version addresses all of the review comments from v5 [1]. As always, thanks to those that have been following along, reviewing and testing this series. This v6 patch series is a

[PATCH v6 02/16] backends/confidential-guest-support: Add functions to support IGVM

2024-09-26 Thread Roy Hopkins
In preparation for supporting the processing of IGVM files to configure guests, this adds a set of functions to ConfidentialGuestSupport allowing configuration of secure virtual machines that can be implemented for each supported isolation platform type such as Intel TDX or AMD SEV-SNP. These funct

[PATCH v6 06/16] sev: Update launch_update_data functions to use Error handling

2024-09-26 Thread Roy Hopkins
The class function and implementations for updating launch data return a code in case of error. In some cases an error message is generated and in other cases, just the error return value is used. This small refactor adds an 'Error **errp' parameter to all functions which consistently set an error

Re: [PATCH v4] scripts/qcow2-to-stdout.py: Add script to write qcow2 images to stdout

2024-09-26 Thread Alberto Garcia
ping On Tue, Jul 30, 2024 at 04:15:52PM +0200, Alberto Garcia wrote: > This tool converts a disk image to qcow2, writing the result directly > to stdout. This can be used for example to send the generated file > over the network.

[PATCH v6 07/16] target/i386: Allow setting of R_LDTR and R_TR with cpu_x86_load_seg_cache()

2024-09-26 Thread Roy Hopkins
The x86 segment registers are identified by the X86Seg enumeration which includes LDTR and TR as well as the normal segment registers. The function 'cpu_x86_load_seg_cache()' uses the enum to determine which segment to set. However, specifying R_LDTR or R_TR results in an out-of-bounds access of th

Re: [PATCH 1/2] kvm: Allow kvm_arch_get/put_registers to accept Error**

2024-09-26 Thread Julia Suvorova
On Wed, Sep 25, 2024 at 8:53 PM Peter Xu wrote: > > On Wed, Sep 25, 2024 at 05:36:22PM +0200, Julia Suvorova wrote: > > This is necessary to provide discernible error messages to the caller. > > > > Signed-off-by: Julia Suvorova > > Reviewed-by: Peter Xu > > One nitpick below: > > > --- > > acc

Re: [PATCH 09/15] acpi/ghes: make the GHES record generation more generic

2024-09-26 Thread Jonathan Cameron via
On Wed, 25 Sep 2024 06:04:14 +0200 Mauro Carvalho Chehab wrote: > Split the code into separate functions to allow using the > common CPER filling code by different error sources. > > The generic code was moved to ghes_record_cper_errors(), > and ghes_gen_err_data_uncorrectable_recoverable() now

Re: [PATCH v2] tests/qemu-iotests/testenv: Use the "r2d" machine for sh4

2024-09-26 Thread Michael Tokarev
26.09.2024 13:55, Thomas Huth wrote: .. I'm planning to provide a patch to remove sh4eb-softmmu completely (since it is useless nowadays) ... I can add it there, too. That'll do it too, for sure. Thanks, /mjt

Re: [PATCH] MAINTAINERS: Add myself as maintainer of e500 machines

2024-09-26 Thread Daniel Henrique Barboza
On 9/26/24 4:59 AM, Bernhard Beschow wrote: Signed-off-by: Bernhard Beschow --- Reviewed-by: Daniel Henrique Barboza MAINTAINERS | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index ffacd60f40..0a191a03db 100644 --- a/MAINTAINERS ++

Re: Rust BoF and maintainer minutes and planning the roadmap to Rust

2024-09-26 Thread Stefan Hajnoczi
On Thu, 26 Sept 2024 at 10:24, Alex Bennée wrote: > What are candidates for conversion? "Conversion" means "rewrite in Rust" to me. There are other ways of integrating Rust without converting existing code: - Writing new subsystems in Rust where there is no existing C code. - Adding Rust binding

Re: [PATCH] MAINTAINERS: Add myself as maintainer of e500 machines

2024-09-26 Thread Cédric Le Goater
On 9/26/24 09:59, Bernhard Beschow wrote: Signed-off-by: Bernhard Beschow Reviewed-by: Cédric Le Goater Thanks, C. --- MAINTAINERS | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index ffacd60f40..0a191a03db 100644 --- a/MAINTAINERS

Re: [PATCH v3] hw/smbios: support for type 7 (cache information)

2024-09-26 Thread Igor Mammedov
On Wed, 25 Sep 2024 19:04:45 + Hal Martin wrote: > This patch adds support for SMBIOS type 7 (Cache Information) to qemu. add here a use-case for this (i.e. why it would be useful for users) given size semantics it would not be easy for enduser to set correct values here. > level: cache

Re: [PATCH 09/15] acpi/ghes: make the GHES record generation more generic

2024-09-26 Thread Mauro Carvalho Chehab
Em Thu, 26 Sep 2024 13:00:56 +0100 Jonathan Cameron escreveu: > On Wed, 25 Sep 2024 06:04:14 +0200 > Mauro Carvalho Chehab wrote: > > > Split the code into separate functions to allow using the > > common CPER filling code by different error sources. > > > > The generic code was moved to ghes_

Rust BoF and maintainer minutes and planning the roadmap to Rust

2024-09-26 Thread Alex Bennée
Hi, We discussed the topic of Rust for QEMU at KVM Forum over the weekend. Aside from its mention in the QEMU Status update we also held a BoF on Sunday evening and had a smaller discussion amongst some of the maintainers on Monday lunchtime. I'm going to try and summarise points from all of those

Re: [PATCH 12/15] acpi/ghes: don't crash QEMU if ghes GED is not found

2024-09-26 Thread Mauro Carvalho Chehab
Em Thu, 26 Sep 2024 13:09:09 +0100 Jonathan Cameron escreveu: > On Wed, 25 Sep 2024 06:04:17 +0200 > Mauro Carvalho Chehab wrote: > > > Instead, produce an error and continue working > > > > Signed-off-by: Mauro Carvalho Chehab > Make sense as defense in depth. Can we actually hit this for

Re: [RFC 0/1] Introduce vfio-cxl to support CXL type-2 device passthrough

2024-09-26 Thread Cédric Le Goater
Hello Zhi, On 9/21/24 09:14, Zhi Wang wrote: Compute Express Link (CXL) is an open standard interconnect built upon industrial PCI layers to enhance the performance and efficiency of data centers by enabling high-speed, low-latency communication between CPUs and various types of devices such as

Re: [PATCH 10/15] acpi/ghes: move offset calculus to a separate function

2024-09-26 Thread Jonathan Cameron via
On Wed, 25 Sep 2024 06:04:15 +0200 Mauro Carvalho Chehab wrote: > Currently, CPER address location is calculated as an offset of > the hardware_errors table. It is also badly named, as the > offset actually used is the address where the CPER data starts, > and not the beginning of the error sourc

Re: [PATCH 11/15] acpi/ghes: better name GHES memory error function

2024-09-26 Thread Jonathan Cameron via
On Wed, 25 Sep 2024 06:04:16 +0200 Mauro Carvalho Chehab wrote: > The current function used to generate GHES data is specific for > memory errors. Give a better name for it, as we now have a generic > function as well. > > Reviewed-by: Igor Mammedov > Signed-off-by: Mauro Carvalho Chehab In ge

Re: [PATCH 12/15] acpi/ghes: don't crash QEMU if ghes GED is not found

2024-09-26 Thread Jonathan Cameron via
On Wed, 25 Sep 2024 06:04:17 +0200 Mauro Carvalho Chehab wrote: > Instead, produce an error and continue working > > Signed-off-by: Mauro Carvalho Chehab Make sense as defense in depth. Can we actually hit this for existing systems, or is the injection stuff disabled if the ged isn't configured

Re: [PATCH 13/15] acpi/ghes: rename etc/hardware_error file macros

2024-09-26 Thread Jonathan Cameron via
On Wed, 25 Sep 2024 06:04:18 +0200 Mauro Carvalho Chehab wrote: > Now that we have also have a file to store HEST data location, > which is part of GHES, better name the file where CPER records > are stored. > > No functional changes. > > Reviewed-by: Igor Mammedov > Signed-off-by: Mauro Carva

[PATCH 0/5] Building PPTT with root node and identical implementation flag

2024-09-26 Thread Yicong Yang via
From: Yicong Yang OS like Linux is using PPTT processor node's identical implementation flag [1] to infer whether the whole system or a certain CPU cluster is homogeneous or not [2]. QEMU currently only support building homogeneous system, set the flag to indicate the fact. Build a root node in P

[PATCH 1/5] tests: virt: Allow changes to PPTT test table

2024-09-26 Thread Yicong Yang via
From: Yicong Yang Allow changes to PPTT test table, preparing for adding identical implementation flags support and for adding a root node for all the system. Signed-off-by: Yicong Yang --- tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests

[PATCH v6 14/16] backends/igvm: Handle policy for SEV guests

2024-09-26 Thread Roy Hopkins
Adds a handler for the guest policy initialization IGVM section and builds an SEV policy based on this information and the ID block directive if present. The policy is applied using by calling 'set_guest_policy()' on the ConfidentialGuestSupport object. Signed-off-by: Roy Hopkins Acked-by: Michae

[PATCH v6 08/16] i386/sev: Refactor setting of reset vector and initial CPU state

2024-09-26 Thread Roy Hopkins
When an SEV guest is started, the reset vector and state are extracted from metadata that is contained in the firmware volume. In preparation for using IGVM to setup the initial CPU state, the code has been refactored to populate vmcb_save_area for each CPU which is then applied during guest start

[PATCH v6 04/16] hw/i386: Add igvm-cfg object and processing for IGVM files

2024-09-26 Thread Roy Hopkins
An IGVM file contains configuration of guest state that should be applied during configuration of the guest, before the guest is started. This patch allows the user to add an igvm-cfg object to an X86 machine configuration that allows an IGVM file to be configured that will be applied to the guest

[PATCH v6 12/16] backends/confidential-guest-support: Add set_guest_policy() function

2024-09-26 Thread Roy Hopkins
For confidential guests a policy can be provided that defines the security level, debug status, expected launch measurement and other parameters that define the configuration of the confidential platform. This commit adds a new function named set_guest_policy() that can be implemented by each conf

[PATCH v6 10/16] docs/system: Add documentation on support for IGVM

2024-09-26 Thread Roy Hopkins
IGVM support has been implemented for Confidential Guests that support AMD SEV and AMD SEV-ES. Add some documentation that gives some background on the IGVM format and how to use it to configure a confidential guest. Signed-off-by: Roy Hopkins Reviewed-by: Daniel P. Berrangé Reviewed-by: Stefano

[PATCH v6 05/16] i386/pc_sysfw: Ensure sysfw flash configuration does not conflict with IGVM

2024-09-26 Thread Roy Hopkins
When using an IGVM file the configuration of the system firmware is defined by IGVM directives contained in the file. In this case the user should not configure any pflash devices. This commit skips initialization of the ROM mode when pflash0 is not set then checks to ensure no pflash devices have

[PATCH v6 13/16] backends/igvm: Process initialization sections in IGVM file

2024-09-26 Thread Roy Hopkins
The initialization sections in IGVM files contain configuration that should be applied to the guest platform before it is started. This includes guest policy and other information that can affect the security level and the startup measurement of a guest. This commit introduces handling of the init

[PATCH v6 15/16] i386/sev: Add implementation of CGS set_guest_policy()

2024-09-26 Thread Roy Hopkins
The new cgs_set_guest_policy() function is provided to receive the guest policy flags, SNP ID block and SNP ID authentication from guest configuration such as an IGVM file and apply it to the platform prior to launching the guest. The policy is used to populate values for the existing 'policy', 'i

[PATCH 5/5] tests: virt: Update expected ACPI tables for virt test

2024-09-26 Thread Yicong Yang via
From: Yicong Yang Update the ACPI tables according to the acpi aml_build change, also empty bios-tables-test-allowed-diff.h. The disassembled differences between actual and expected PPTT shows below. Only about the root node adding and identification flag set as expected. /* * Intel ACPI C

[PATCH 3/5] hw/acpi/aml-build: Build a root node in the PPTT table

2024-09-26 Thread Yicong Yang via
From: Yicong Yang Currently we build the PPTT starting from the socket node and each socket will be a separate tree. For a multi-socket system it'll be hard for the OS to know the whole system is homogeneous or not (actually we're in the current implementation) since no parent node to telling the

[PATCH 2/5] hw/acpi/aml-build: Set identical implementation flag for PPTT processor nodes

2024-09-26 Thread Yicong Yang via
From: Yicong Yang Per ACPI 6.5 Table 5.158: Processor Structure Flags, the identical implementation flag indicates whether all the children processors of this node share the same identical implementation revision. Currently Linux support parsing this field [1] and maybe used to identify the heter

[PATCH 4/5] hw/acpi/aml-build: Update the revision of PPTT table

2024-09-26 Thread Yicong Yang via
From: Yicong Yang The lastest ACPI spec 6.5 support PPTT revision 3. Update it by handy. This is compatible with previous revision. Signed-off-by: Yicong Yang --- hw/acpi/aml-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c i

Re: [PATCH 14/15] better name the offset of the hardware error firmware

2024-09-26 Thread Jonathan Cameron via
On Wed, 25 Sep 2024 06:04:19 +0200 Mauro Carvalho Chehab wrote: > The hardware error firmware is where HEST error structures are > stored. Those can be GHESv2, but they can also be other types. > > Better name the location of the hardware error. > > No functional changes. > > Signed-off-by: Ma

Re: [PATCH 15/15] docs: acpi_hest_ghes: fix documentation for CPER size

2024-09-26 Thread Jonathan Cameron via
On Wed, 25 Sep 2024 06:04:20 +0200 Mauro Carvalho Chehab wrote: > While the spec defines a CPER size of 4KiB for each record, > currently it is set to 1KiB. Fix the documentation and add > a pointer to the macro name there, as this may help to keep > it updated. > > Signed-off-by: Mauro Carvalho

Re: Are floating-point exceptions usable on AArch64?

2024-09-26 Thread Peter Maydell
On Wed, 4 Sept 2024 at 11:32, Sebastian Huber wrote: > > Hello, > > I tried to provoke a division-by-zero exception on AArch64 using: > > uint64_t value; > __asm__ volatile ( > "mrs %0, FPCR\n" > "orr %0, %0, 0x200\n" > "msr FPCR, %0" : "=&r" ( value ) : : "memory" >

Re: [PATCH V3] arm/kvm: add support for MTE

2024-09-26 Thread Gustavo Romero
Hi Ganapatrao, On 9/25/24 19:40, Ganapatrao Kulkarni wrote: Hi Gustavo, On 25-09-2024 09:17 pm, Gustavo Romero wrote: Hi Ganapatrao, Sorry for the delay on replying it. I was attending KVM Forum and commuting. On 9/20/24 09:37, Ganapatrao Kulkarni wrote: Extend the 'mte' property for the

Re: [PATCH v1 0/2] Drop ignore_memory_transaction_failures for xilink_zynq

2024-09-26 Thread Chao Liu
> The ignore_memory_transaction_failures is used for compatibility > with legacy board models. > > I attempted to remove this property from the > xilink_zynq board and replace it with unimplemented devices to > handle devices that are not implemented on the board. > > Chao Liu (2): > xilink_z

[PATCH v1 0/2] Re: Drop ignore_memory_transaction_failures for xilink_zynq

2024-09-26 Thread Chao Liu
> The ignore_memory_transaction_failures is used for compatibility > with legacy board models. > > I attempted to remove this property from the > xilink_zynq board and replace it with unimplemented devices to > handle devices that are not implemented on the board. > > Chao Liu (2): > xilink_z

Re: [PATCH v3 2/6] hw/gpio/aspeed: Support to set the different memory size

2024-09-26 Thread Cédric Le Goater
On 9/26/24 09:45, Jamin Lin wrote: According to the datasheet of ASPEED SOCs, a GPIO controller owns 4KB of register space for AST2700, AST2500, AST2400 and AST1030; owns 2KB of register space for AST2600 1.8v and owns 2KB of register space for AST2600 3.3v. It set the memory region size 2KB by

Re: [PATCH v1 1/7] migration: Introduce structs for background sync

2024-09-26 Thread Yong Huang
On Thu, Sep 26, 2024 at 3:17 AM Peter Xu wrote: > On Fri, Sep 20, 2024 at 10:43:31AM +0800, Yong Huang wrote: > > Yes, invoke migration_bitmap_sync_precopy more frequently is also my > > first idea but it involves bitmap updating and interfere with the > behavior > > of page sending, it also affe

Re: [PATCH v2 1/1] hw/nvme: add atomic write support

2024-09-26 Thread alan . adamson
On 9/24/24 5:15 AM, Klaus Jensen wrote: On Sep 19 17:07, Alan Adamson wrote: Adds support for the controller atomic parameters: AWUN and AWUPF. Atomic Compare and Write Unit (ACWU) is not currently supported. Writes that adhere to the ACWU and AWUPF parameters are guaranteed to be atomic. Ne

Re: [PATCH v1 1/7] migration: Introduce structs for background sync

2024-09-26 Thread Peter Xu
On Fri, Sep 27, 2024 at 02:13:47AM +0800, Yong Huang wrote: > On Thu, Sep 26, 2024 at 3:17 AM Peter Xu wrote: > > > On Fri, Sep 20, 2024 at 10:43:31AM +0800, Yong Huang wrote: > > > Yes, invoke migration_bitmap_sync_precopy more frequently is also my > > > first idea but it involves bitmap updati

Re: [PATCH v1 0/2] Re: Drop ignore_memory_transaction_failures for xilink_zynq

2024-09-26 Thread Peter Maydell
On Thu, 26 Sept 2024 at 18:05, Chao Liu wrote: > > > The ignore_memory_transaction_failures is used for compatibility > > with legacy board models. > > > > I attempted to remove this property from the > > xilink_zynq board and replace it with unimplemented devices to > > handle devices that are no

Re: [PATCH v2 08/17] migration: Add load_finish handler and associated functions

2024-09-26 Thread Maciej S. Szmigiero
On 20.09.2024 18:45, Peter Xu wrote: On Fri, Sep 20, 2024 at 05:23:08PM +0200, Maciej S. Szmigiero wrote: On 19.09.2024 23:11, Peter Xu wrote: On Thu, Sep 19, 2024 at 09:49:10PM +0200, Maciej S. Szmigiero wrote: On 9.09.2024 22:03, Peter Xu wrote: On Tue, Aug 27, 2024 at 07:54:27PM +0200, Mac

RE: [PATCH v3 08/17] intel_iommu: Set accessed and dirty bits during first stage translation

2024-09-26 Thread Duan, Zhenzhong
>-Original Message- >From: Jason Wang >Subject: Re: [PATCH v3 08/17] intel_iommu: Set accessed and dirty bits >during first stage translation > >On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan > wrote: >> >> From: Clément Mathieu--Drif >> >> Signed-off-by: Clément Mathieu--Drif >> Signe

RE: [PATCH v3 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode

2024-09-26 Thread Duan, Zhenzhong
>-Original Message- >From: Jason Wang >Subject: Re: [PATCH v3 14/17] intel_iommu: Set default aw_bits to 48 in >scalable modern mode > >On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan > wrote: >> >> According to VTD spec, stage-1 page table could support 4-level and >> 5-level paging. >>

RE: [PATCH v3 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

2024-09-26 Thread Duan, Zhenzhong
>-Original Message- >From: Jason Wang >Subject: Re: [PATCH v3 04/17] intel_iommu: Flush stage-2 cache in PASID- >selective PASID-based iotlb invalidation > >On Wed, Sep 11, 2024 at 1:26 PM Zhenzhong Duan > wrote: >> >> Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will

RE: [PATCH v3 0/6] Support GPIO for AST2700

2024-09-26 Thread Jamin Lin
Hi Cedric, > Subject: Re: [PATCH v3 0/6] Support GPIO for AST2700 > > Hello Jamin, > > >> Could you please to add tests in tests/qtest/aspeed_gpio-test.c for > >> this changes ? At least one with the ast2700-evb machine if possible. > >> > > > > Will add > Thanks for the effort. I appreciate. >

RE: [PATCH v3 15/17] intel_iommu: Modify x-scalable-mode to be string option to expose scalable modern mode

2024-09-26 Thread Duan, Zhenzhong
>-Original Message- >From: Jason Wang >Subject: Re: [PATCH v3 15/17] intel_iommu: Modify x-scalable-mode to be >string option to expose scalable modern mode > >On Wed, Sep 11, 2024 at 1:27 PM Zhenzhong Duan > wrote: >> >> From: Yi Liu >> >> Intel VT-d 3.0 introduces scalable mode, and i

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