Hi All, Kindly ping, more comments are appreciated:)
Thanks Zhenzhong On 9/11/2024 1:22 PM, Zhenzhong Duan wrote:
Hi, Per Jason Wang's suggestion, iommufd nesting series[1] is split into "Enable stage-1 translation for emulated device" series and "Enable stage-1 translation for passthrough device" series. This series enables stage-1 translation support for emulated device in intel iommu which we called "modern" mode. PATCH1-5: Some preparing work before support stage-1 translation PATCH6-8: Implement stage-1 translation for emulated device PATCH9-13: Emulate iotlb invalidation of stage-1 mapping PATCH14: Set default aw_bits to 48 in scalable modren mode PATCH15-16:Expose scalable "modern" mode and "x-cap-fs1gp" to cmdline PATCH17: Add qtest Note in spec revision 3.4, it renames "First-level" to "First-stage", "Second-level" to "Second-stage". But the scalable mode was added before that change. So we keep old favor using First-level/fl/Second-level/sl in code but change to use stage-1/stage-2 in commit log. But keep in mind First-level/fl/stage-1 all have same meaning, same for Second-level/sl/stage-2. Qemu code can be found at [2] The whole nesting series can be found at [3] [1] https://lists.gnu.org/archive/html/qemu-devel/2024-01/msg02740.html [2] https://github.com/yiliu1765/qemu/tree/zhenzhong/iommufd_stage1_emu_v3 [3] https://github.com/yiliu1765/qemu/tree/zhenzhong/iommufd_nesting_rfcv2 Thanks Zhenzhong Changelog: v3: - drop unnecessary !(s->ecap & VTD_ECAP_SMTS) (Clement) - simplify calculation of return value for vtd_iova_fl_check_canonical() (Liuyi) - make A/D bit setting atomic (Liuyi) - refine error msg (Clement, Liuyi) v2: - check ecap/cap bits instead of s->scalable_modern in vtd_pe_type_check() (Clement) - declare VTD_ECAP_FLTS/FS1GP after the feature is implemented (Clement) - define VTD_INV_DESC_PIOTLB_G (Clement) - make error msg consistent in vtd_process_piotlb_desc() (Clement) - refine commit log in patch16 (Clement) - add VTD_ECAP_IR to ECAP_MODERN_FIXED1 (Clement) - add a knob x-cap-fs1gp to control stage-1 1G paging capability - collect Clement's R-B v1: - define VTD_HOST_AW_AUTO (Clement) - passing pgtt as a parameter to vtd_update_iotlb (Clement) - prefix sl_/fl_ to second/first level specific functions (Clement) - pick reserved bit check from Clement, add his Co-developed-by - Update test without using libqtest-single.h (Thomas) rfcv2: - split from nesting series (Jason) - merged some commits from Clement - add qtest (jason) Clément Mathieu--Drif (4): intel_iommu: Check if the input address is canonical intel_iommu: Set accessed and dirty bits during first stage translation intel_iommu: Add an internal API to find an address space with PASID intel_iommu: Add support for PASID-based device IOTLB invalidation Yi Liu (3): intel_iommu: Rename slpte to pte intel_iommu: Implement stage-1 translation intel_iommu: Modify x-scalable-mode to be string option to expose scalable modern mode Yu Zhang (1): intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan (9): intel_iommu: Make pasid entry type check accurate intel_iommu: Add a placeholder variable for scalable modern mode intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation intel_iommu: Flush stage-1 cache in iotlb invalidation intel_iommu: Process PASID-based iotlb invalidation intel_iommu: piotlb invalidation should notify unmap intel_iommu: Set default aw_bits to 48 in scalable modern mode intel_iommu: Introduce a property to control FS1GP cap bit setting tests/qtest: Add intel-iommu test MAINTAINERS | 1 + hw/i386/intel_iommu_internal.h | 91 ++++- include/hw/i386/intel_iommu.h | 9 +- hw/i386/intel_iommu.c | 694 +++++++++++++++++++++++++++------ tests/qtest/intel-iommu-test.c | 70 ++++ tests/qtest/meson.build | 1 + 6 files changed, 735 insertions(+), 131 deletions(-) create mode 100644 tests/qtest/intel-iommu-test.c
