On 3/9/24 16:45, Alireza Sanaee wrote:
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
avail
weird...
On Tue, Sep 3, 2024, 14:13 Alex Bennée wrote:
> Alex Bennée writes:
>
> > Elisha Hollander writes:
> >
> >> Sure!
> >>
> >> `build/qemu-system-i386 -plugin build/contrib/plugins/libips.so,ips=1
> -display curses -bios bios.raw`
> >>
> >> Also, I just tested with 9.1.0-rc4 and it resul
Steve Sistare writes:
> Add the helper function cpr_get_fd_param, for use by tap and vdpa.
>
> Signed-off-by: Steve Sistare
Reviewed-by: Fabiano Rosas
Remove the deprecated SH4 SHIX machine, along
with the TC58128 NAND EEPROM.
Philippe Mathieu-Daudé (3):
hw/sh4: Remove the deprecated SHIX machine
hw/block: Remove TC58128 NAND EEPROM
hw/sh4: Remove sh7750_register_io_device() helper
MAINTAINERS | 11 --
docs/a
The TC58128 NAND EEPROM is not user creatable and
needs to be instanciated in the code via tc58128_init().
Only the SHIX machine was using it, and it was removed
in the previous commit. Since the TC58128 has no more
users, remove it too.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS
The SHIX machine is deprecated since v9.0 (commit
322b038c94 "target/sh4: Deprecate the shix machine").
Time to remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 7 +-
docs/about/deprecated.rst | 6 --
docs/about/removed-features.rst
sh7750_register_io_device() was only used by the TC58128
NAND EEPROM which has been removed in the previous commit.
Remove it as unused code.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sh4/sh.h | 16 -
hw/sh4/sh7750.c | 57 ++---
This patchset removes the various Arm machines which we deprecated
for the 9.0 release and are therefore allowed to remove for the 9.2
release:
akita, borzoi, cheetah, connex, mainstone, n800, n810,
spitz, terrier, tosa, verdex, z2
We get to drop over 30,000 lines of unmaintained code. So it's
a
The pxa27x-timer can be removed now we have removed the PXA2xx
SoC models. The pxa25x-timer device must remain as it is still
used by strongarm.
Signed-off-by: Peter Maydell
---
hw/timer/pxa2xx_timer.c | 24
1 file changed, 24 deletions(-)
diff --git a/hw/timer/pxa2xx_t
Remove the pxa2xx-specific interrupt controller device.
As this is the last user of the pxa.h header file and the
CONFIG_PXA2XX define we can remove those too.
This completes the removal of the pxa2xx specific code. We leave:
* pxa2xx_timer -- still used by the Collie board (strongarm)
* the de
The MAX111X ADC device was used only by the XScale-based
Zaurus machine types. Now they have all been removed, we can
drop this device model too.
Signed-off-by: Peter Maydell
---
MAINTAINERS | 2 -
include/hw/adc/max111x.h | 56 --
hw/adc/max111x.c | 236 -
The MAX7310 GPIO controller was used only by the XScale-based Zaurus
machine types. Now they have been removed we can remove this device
model as well.
Signed-off-by: Peter Maydell
---
MAINTAINERS | 1 -
hw/gpio/max7310.c | 217
hw/gpio/K
The connex and verdex machines have been deprecated since
9.0 and so can be removed for the 9.2 release.
Signed-off-by: Peter Maydell
---
MAINTAINERS | 8 --
docs/system/arm/gumstix.rst | 21
docs/system/target-arm.rst | 1 -
configs
The Sharp XScale-based PDA board models akita, borzoi, spitz,
terrier, and tosa were all deprecated in 9.0, so our deprecation
cycle permits removing them for the 9.2 release.
Remove the source files for the board models themselves, and their
documentation. There were no tests for these boards.
W
Remove the pxa2xx specific pcmcia device.
Signed-off-by: Peter Maydell
---
include/hw/arm/pxa.h | 8 --
hw/pcmcia/pxa2xx.c| 248 --
hw/pcmcia/meson.build | 1 -
3 files changed, 257 deletions(-)
delete mode 100644 hw/pcmcia/pxa2xx.c
diff --git a
The ADS7846 touchscreen controller device was used only by
the XScale-based PDA machine types. Now that they have been
removed, this device is not used in the tree and can be
deleted.
Signed-off-by: Peter Maydell
---
MAINTAINERS | 1 -
hw/input/ads7846.c | 186 --
Now we have removed all the board types that it covers, we can move
the text about old Arm boards from deprecated.rst to
removed-features.rst, tweaking it appropriately.
Signed-off-by: Peter Maydell
---
docs/about/deprecated.rst | 15 ---
docs/about/removed-features.rst | 15 ++
We've removed the OMAP2 SoC, so we can remove the OMAP2 GPIO
device. (The source file remains, as it also has the model of
the OMAP1 GPIO device.)
Signed-off-by: Peter Maydell
---
include/hw/arm/omap.h | 8 -
hw/gpio/omap_gpio.c | 557 --
2 files chang
pxa2xx_timer includes pxa.h, but it doesn't actually make
use of any of the #defines, function prototypes or structs
defined there. Remove the unnecessary include (we will
shortly be removing the whole header file).
Signed-off-by: Peter Maydell
---
hw/timer/pxa2xx_timer.c | 1 -
1 file changed,
We have two command line options that are specific to the now-removed
pxa2xx LCD display device, that allowed the user to rotate the
display output by 90, 180 or 270 degrees. Since these are now
useless, we can remove them, and the corresponding code in ui/input.c
that transformed the input coordi
Remove the pxa2xx-specific GPIO device.
Signed-off-by: Peter Maydell
---
include/hw/arm/pxa.h | 5 -
hw/arm/pxa2xx_gpio.c | 365 ---
hw/arm/meson.build | 2 +-
3 files changed, 1 insertion(+), 371 deletions(-)
delete mode 100644 hw/arm/pxa2xx_gpio.c
The ecc.c code was used only by the PXA2xx and OMAP2 SoC devices,
which we have removed, so it is now completely unused.
Note that hw/misc/eccmemctl.c does not in fact use any of the
code frome ecc.c, so that KConfig dependency was incorrect.
Signed-off-by: Peter Maydell
---
include/hw/block/fl
Currently the STRONGARM KConfig symbol pulls in PXA2XX. Since we've now
removed all the true uses of PXA2XX, we'd like to remove the PXA2XX
symbol too. To permit that, make STRONGARM directly select the things
it truly depends on:
* pxa25x-timer
* SSI
Signed-off-by: Peter Maydell
---
hw/arm/Kc
The ZAURUS KConfig symbol used to do multiple things:
* pull in the tc6393xb display device
* pull in the Zaurus SCOOP GPIO device
* pull in hw/block/nand.c code
* pull in hw/block/ecc.c code
and was used by multiple machine types in the Zaurus family.
Now that we've removed all the Zaurus mac
The 'z2' machine was deprecated in 9.0, so we can remove it for
9.2.
Signed-off-by: Peter Maydell
---
MAINTAINERS | 1 -
configs/devices/arm-softmmu/default.mak | 1 -
hw/arm/z2.c | 355
hw/arm/Kconfig
The tc6393xb was used only by the XScale-based Zaurus machine types.
Now they have been removed we can remove this device too.
Signed-off-by: Peter Maydell
---
MAINTAINERS | 2 -
include/hw/display/tc6393xb.h | 21 --
hw/display/tc6393xb.c | 568 -
Remove the tsc2005 touchscreen controller, which was only used
by the n800 and n810 machines.
Signed-off-by: Peter Maydell
---
MAINTAINERS| 1 -
include/hw/input/tsc2xxx.h | 5 -
hw/input/tsc2005.c | 571 -
hw/input/Kconfig
Remove the OMAP2 specific code from omap_mmc.c.
Signed-off-by: Peter Maydell
---
include/hw/arm/omap.h | 5
hw/sd/omap_mmc.c | 63 ---
2 files changed, 68 deletions(-)
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
index 67bb83dff5d
Remove the OMAP2 specific code from omap_uart.c.
Signed-off-by: Peter Maydell
---
include/hw/arm/omap.h | 5 --
hw/char/omap_uart.c | 113 --
2 files changed, 118 deletions(-)
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
index b569580b09
Remove the pxa2xx-specific pxa2xx_mmci device.
Signed-off-by: Peter Maydell
---
include/hw/arm/pxa.h | 10 -
hw/sd/pxa2xx_mmci.c | 594 ---
hw/sd/meson.build| 1 -
hw/sd/trace-events | 4 -
4 files changed, 609 deletions(-)
delete mode 100644
The DSCM-1 microdrive device model was used only by the
XScale-based Zaurus machine types. Now they have been removed, we
can delete this device too.
Signed-off-by: Peter Maydell
---
include/hw/pcmcia.h | 3 -
hw/ide/microdrive.c | 644
hw/ide/
The omap_dma4 device was only used in the OMAP2 SoC, which has
been removed.
Signed-off-by: Peter Maydell
---
include/hw/arm/omap.h | 1 -
hw/dma/omap_dma.c | 451 +-
2 files changed, 3 insertions(+), 449 deletions(-)
diff --git a/include/hw/arm/oma
Remove the OMAP2 specific code from omap_intc.c.
Signed-off-by: Peter Maydell
---
hw/intc/omap_intc.c | 276
1 file changed, 276 deletions(-)
diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c
index 435c47600fc..c14b22d3819 100644
--- a/hw/intc/o
Remove some defines and enums that are OMAP2 specific and
no longer used anywhere.
Signed-off-by: Peter Maydell
---
include/hw/arm/omap.h | 207 --
1 file changed, 207 deletions(-)
diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h
index 3f9860070
Remove the pxa2xx-specific pxa2xx_dma device.
Signed-off-by: Peter Maydell
---
include/hw/arm/pxa.h | 4 -
hw/dma/pxa2xx_dma.c | 591 ---
hw/dma/meson.build | 1 -
3 files changed, 596 deletions(-)
delete mode 100644 hw/dma/pxa2xx_dma.c
diff --git
The MAINSTONE_FPGA device was used only by the 'mainstone' machine
type, so we can remove it now.
Signed-off-by: Peter Maydell
---
MAINTAINERS | 1 -
hw/misc/mst_fpga.c | 269
hw/misc/meson.build | 1 -
3 files changed, 271 deletions(-)
The 'mainstone' machine has been deprecated since 9.0, and
so we can remove it for the 9.2 release.
Signed-off-by: Peter Maydell
---
MAINTAINERS | 2 -
docs/system/arm/mainstone.rst | 25
docs/system/target-arm.rst | 1 -
configs/devic
Remove the tsc210x touchscreen controller device, which was
only used by the n800 and n810.
The uWireSlave struct is still used in omap1.c (at least for
compilation purposes -- nothing any longer calls omap_uwire_attach()
and so the struct's members will not be used at runtime), so
we move it into
The only PCMCIA subsystem was the PXA2xx SoC and the machines
using it, which have now been removed. Although in theory
we have a few machine types which have PCMCIA (e.g. kzm,
the strongarm machines, sh4's sh7750), none of those machines
implement their PCMCIA controller, and they're all old and
n
Remove the pxa2xx-specific pxa2xx_lcd device.
Signed-off-by: Peter Maydell
---
include/hw/arm/pxa.h|6 -
hw/display/pxa2xx_lcd.c | 1451 ---
hw/display/meson.build |1 -
3 files changed, 1458 deletions(-)
delete mode 100644 hw/display/pxa2xx_lcd.
Remove the handling for all non-OMAP1 SoCs.
Signed-off-by: Peter Maydell
---
hw/misc/omap_clk.c | 527 +
1 file changed, 2 insertions(+), 525 deletions(-)
diff --git a/hw/misc/omap_clk.c b/hw/misc/omap_clk.c
index c77ca2fc74e..0157c9be759 100644
--- a
All the callers of pxa270_init() and pxa255_init() have now been removed,
so we can remove pxa2xx.c. This also removes the only uses of a lot of
pxa2xx specific devices, which will be removed in subsequent commits.
Signed-off-by: Peter Maydell
---
include/hw/arm/pxa.h | 78 --
hw/arm/pxa2xx.c
On Tue, 3 Sept 2024 at 16:28, Philippe Mathieu-Daudé wrote:
>
> The CRIS target is deprecated since v9.0 (commit c7bbef40234
> "docs: mark CRIS support as deprecated").
>
> Remove:
> - Buildsys / CI infra
> - User emulation
> - System emulation (axis-dev88 machine and ETRAX devices)
> - Tests
>
>
The 'cheetah' machine has been deprecated since 9.0, so we can
remove it for the 9.2 release.
(tsc210x.c is also used by nseries, so move its MAINTAINER file
line there; the nseries boards are also about to be removed.)
Signed-off-by: Peter Maydell
---
MAINTAINERS |
Remove the pxa2xx-specific pxa2xx_keypad device.
Signed-off-by: Peter Maydell
---
include/hw/arm/pxa.h | 12 --
hw/input/pxa2xx_keypad.c | 331 ---
hw/input/meson.build | 1 -
3 files changed, 344 deletions(-)
delete mode 100644 hw/input/pxa2xx_key
On Tue, 3 Sept 2024 at 16:40, Philippe Mathieu-Daudé wrote:
>
> Remove the deprecated SH4 SHIX machine, along
> with the TC58128 NAND EEPROM.
>
> Philippe Mathieu-Daudé (3):
> hw/sh4: Remove the deprecated SHIX machine
> hw/block: Remove TC58128 NAND EEPROM
> hw/sh4: Remove sh7750_register_i
On 9/2/24 06:21, Peter Maydell wrote:
On Fri, 30 Aug 2024 at 16:21, Peter Maydell wrote:
In vfp.decode we have the names of the VFNMA and VFNMS instructions
the wrong way around. The architecture says that bit 6 is the 'op'
bit, which is 1 for VFNMA and 1 for VFNMS, but we label these two
D
On Fri, 30 Aug 2024 at 09:05, Edgar E. Iglesias
wrote:
>
> On Thu, Aug 29, 2024 at 01:50:02PM +0100, Peter Maydell wrote:
> > On Wed, 28 Aug 2024 at 01:51, Sebastian Huber
> > wrote:
> > >
> > > The system supports the Security Extensions (core and GIC). This change
> > > is
> > > necessary to
On Tue, 3 Sept 2024 at 14:52, Philippe Mathieu-Daudé wrote:
>
> On 3/9/24 15:39, Changbin Du wrote:
> > Print errors before exit. Do not exit silently.
> >
> > Cc: Philippe Mathieu-Daudé
> > Signed-off-by: Changbin Du
> >
> > ---
> > v3: use load_elf_strerror() to format errno.
> > v2: remove ms
On Tue, 3 Sept 2024 at 15:41, Philippe Mathieu-Daudé wrote:
>
> If the file is not an ELF file, arm_setup_direct_kernel_boot()
> falls back to try it as a uimage or an AArch64 Image file or as
> last resort a bare raw binary. We can discard load_elf_hdr()
> error and silently return.
>
> Signed-of
The linux-user hppa target crashes randomly for me since commit
081a0ed188d8 ("target/hppa: Do not mask in copy_iaoq_entry").
That commit dropped the masking of the IAOQ addresses while copying them
from other registers and instead keeps them with all 64 bits up until
the full gva is formed with t
On 9/2/24 10:52, Alex Bennée wrote:
Pierrick Bouvier writes:
Hi Xingran,
On 9/2/24 03:42, Alex Bennée wrote:
Xingran Wang writes:
Currently, the instruction count obtained by plugins using the translation
block execution callback is larger than the actual value. Adding callbacks
in cpu_re
On Sat, Aug 31, 2024, 2:02 AM Markus Armbruster wrote:
> John Snow writes:
>
> > On Fri, Aug 30, 2024 at 7:09 AM Markus Armbruster
> wrote:
> >
> >> John Snow writes:
> >>
> >> > qemu.git/python/setup.cfg disallows checking in any code with "XXX",
> >> > "FIXME" or "TODO" in the comments. Soft
On Fri, 30 Aug 2024 at 11:47, Xingtao Yao (Fujitsu) via
wrote:
>
>
>
> > -Original Message-
> > From: qemu-devel-bounces+yaoxt.fnst=fujitsu@nongnu.org
> > On Behalf Of Gao
> > Shiyuan via
> > Sent: Thursday, August 29, 2024 9:10 PM
> > To: Paolo Bonzini
> > Cc: qemu-devel@nongnu.org;
On 3.09.2024 15:55, Stefan Hajnoczi wrote:
On Tue, 27 Aug 2024 at 13:58, Maciej S. Szmigiero
wrote:
From: "Maciej S. Szmigiero"
Migration code wants to manage device data sending threads in one place.
QEMU has an existing thread pool implementation, however it was limited
to queuing AIO ope
On 9/3/24 18:06, Peter Maydell wrote:
This patchset removes the various Arm machines which we deprecated
for the 9.0 release and are therefore allowed to remove for the 9.2
release:
akita, borzoi, cheetah, connex, mainstone, n800, n810,
spitz, terrier, tosa, verdex, z2
We get to drop over 30,
On Tue, 3 Sept 2024 at 17:55, Paolo Bonzini wrote:
>
> On 9/3/24 18:06, Peter Maydell wrote:
> > This patchset removes the various Arm machines which we deprecated
> > for the 9.0 release and are therefore allowed to remove for the 9.2
> > release:
> > akita, borzoi, cheetah, connex, mainstone,
On Tue, Sep 3, 2024 at 7:04 PM Peter Maydell wrote:
> The PXA display device doesn't pass anything through to the guest,
> by the way -- it just draws the pixels in the guest framebuffer
> in a different place in the UI window. As the FIXME comment in
> pxa2xx_lcd.c notes, this should really have
Richard Henderson writes:
> On 9/2/24 10:52, Alex Bennée wrote:
>> Pierrick Bouvier writes:
>>
>>> Hi Xingran,
>>>
>>> On 9/2/24 03:42, Alex Bennée wrote:
Xingran Wang writes:
> Currently, the instruction count obtained by plugins using the translation
> block execution callb
On Mon, Sep 2, 2024, 4:51 AM Daniel P. Berrangé wrote:
> On Fri, Aug 30, 2024 at 02:22:50PM -0400, John Snow wrote:
> > Gave Dan a related answer. For you, my explanation is:
> >
> > - It's nice to have just one configuration for static analysis in just
> one
> > place
> > - It's nice to have tha
On 3/9/24 18:13, Peter Maydell wrote:
On Tue, 3 Sept 2024 at 16:28, Philippe Mathieu-Daudé wrote:
The CRIS target is deprecated since v9.0 (commit c7bbef40234
"docs: mark CRIS support as deprecated").
Remove:
- Buildsys / CI infra
- User emulation
- System emulation (axis-dev88 machine and ET
On 3/9/24 17:21, Daniel P. Berrangé wrote:
On Tue, Sep 03, 2024 at 05:02:44PM +0200, Philippe Mathieu-Daudé wrote:
On 3/9/24 15:37, Clément Léger wrote:
On 03/09/2024 15:34, Philippe Mathieu-Daudé wrote:
On 3/9/24 09:53, Clément Léger wrote:
On 02/09/2024 21:38, Philippe Mathieu-Daudé wrote:
I know that the `cache` parameter for `-drive` controls the caching behavior when
writing from the guest to the host, but is there a way to control the reading
behavior host->guest? Currently, on HEAD, if I open a file on both the guest
and host, and write some data to the drive on the (macOS)
On 3.09.2024 16:26, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
On 3.09.2024 00:07, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
From: "Maciej S. Szmigiero"
Migration code wants to manage device data sending threads in one place.
QEMU has an existing thread pool implementat
On 9/3/24 03:28, Helge Deller wrote:
While adding hppa64 support, the psw_v variable got extended from 32 to 64
bits. So, when packaging the PSW-V bit from the psw_v variable for interrupt
processing, check bit 31 instead the 63th (sign) bit.
This fixes a hard to find Linux kernel boot issue wh
On 3.09.2024 16:42, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
On 30.08.2024 22:22, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
From: "Maciej S. Szmigiero"
Add a basic support for receiving device state via multifd channels -
channels that are shared with RAM transfers.
T
On Tue, 3 Sept 2024 at 12:54, Maciej S. Szmigiero
wrote:
>
> On 3.09.2024 15:55, Stefan Hajnoczi wrote:
> > On Tue, 27 Aug 2024 at 13:58, Maciej S. Szmigiero
> > wrote:
> >>
> >> From: "Maciej S. Szmigiero"
> >>
> >> Migration code wants to manage device data sending threads in one place.
> >>
>
While adding hppa64 support, the psw_v variable got extended from 32 to 64
bits. So, when packaging the PSW-V bit from the psw_v variable for interrupt
processing, check bit 31 instead the 63th (sign) bit.
This fixes a hard to find Linux kernel boot issue where the loss of the PSW-V
bit due to an
On 9/3/2024 6:44 AM, Euan Turner wrote:
Hi Steve,
On 30/08/2024 12:56, Steve Sistare wrote:
This reverts commit e6383293eb01928692047e617665a742cca87e23.
The reset function is needed for CPR.
Signed-off-by: Steve Sistare
---
hw/virtio/vhost-backend.c | 6 ++
1 file changed, 6 insertion
On Thu, Aug 29, 2024 at 1:11 AM Michael S. Tsirkin wrote:
>
> On Thu, Aug 29, 2024 at 01:04:05AM +0600, Dorjoy Chowdhury wrote:
> > On Thu, Aug 29, 2024 at 12:28 AM Michael S. Tsirkin wrote:
> > >
> > > On Thu, Aug 22, 2024 at 09:08:46PM +0600, Dorjoy Chowdhury wrote:
> > > > Nitro Secure Module
The omap2_mmc device -- deprecated and about to be
removed -- was the last user of the legacy sd_set_cb()
and sd_enable() methods. Remove them too along with
the me_no_qdev_me_kill_mammoth_with_rocks kludge.
Based-on: <20240903160751.4100218-1-peter.mayd...@linaro.org>
Philippe Mathieu-Daudé (2):
On 3.09.2024 17:01, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
On 30.08.2024 20:13, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
From: "Maciej S. Szmigiero"
This is necessary for multifd_send() to be able to be called
from multiple threads.
Signed-off-by: Maciej S. Szmigie
sd_set_cb() was only used by omap2_mmc_init() which
got recently removed. Time to remove it. For historical
background on the me_no_qdev_me_kill_mammoth_with_rocks
kludge, see commit 007d1dbf72 ("sd: Hide the qdev-but-not-quite
thing created by sd_init()").
Signed-off-by: Philippe Mathieu-Daudé
-
On 9/3/24 09:41, Helge Deller wrote:
The linux-user hppa target crashes randomly for me since commit
081a0ed188d8 ("target/hppa: Do not mask in copy_iaoq_entry").
That commit dropped the masking of the IAOQ addresses while copying them
from other registers and instead keeps them with all 64 bits
sd_enable() was only used by omap_mmc_enable() which
got recently removed. Time to remove it.
Since the SDState::enable boolean is now always %true,
we can remove it and simplify.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/sd/sd.h| 1 -
include/hw/sd/sdcard_legacy.h | 9
(Cc'ing Guenter who asked to keep the SX1 machine)
On 3/9/24 22:04, Philippe Mathieu-Daudé wrote:
sd_set_cb() was only used by omap2_mmc_init() which
got recently removed. Time to remove it. For historical
background on the me_no_qdev_me_kill_mammoth_with_rocks
kludge, see commit 007d1dbf72 ("sd
Hi,
In this new version the only significant code change was made in patch
3, where we're no longer modifying the host address with the translated
address. The remaining of the changes consist in adding more in-code
docs (a.k.a comments) on the design choices made in the emulation.
The docs were
From: Tomasz Jeznach
The RISC-V IOMMU specification is now ratified as-per the RISC-V
international process. The latest frozen specifcation can be found at:
https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
Add the foundation of the device emulation for RISC-V
To test the RISC-V IOMMU emulation we'll use its PCI representation.
Create a new 'riscv-iommu-pci' libqos device that will be present with
CONFIG_RISCV_IOMMU. This config is only available for RISC-V, so this
device will only be consumed by the RISC-V libqos machine.
Start with basic tests: a PC
From: Tomasz Jeznach
Generate device tree entry for riscv-iommu PCI device, along with
mapping all PCI device identifiers to the single IOMMU device instance.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
---
hw/r
Add an additional test to further exercise the IOMMU where we attempt to
initialize the command, fault and page-request queues.
These steps are taken from chapter 6.2 of the RISC-V IOMMU spec,
"Guidelines for initialization". It emulates what we expect from the
software/OS when initializing the IO
The RISC-V IOMMU PCI device we're going to add next is a reference
implementation of the riscv-iommu spec [1], which predicts that the
IOMMU can be implemented as a PCIe device.
However, RISC-V International (RVI), the entity that ratified the
riscv-iommu spec, didn't bother assigning a PCI ID for
Add a simple guideline to use the existing RISC-V IOMMU support we just
added.
This doc will be updated once we add the riscv-iommu-sys device.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
---
docs/specs/index.rst | 1 +
docs/specs/riscv-iommu.rst | 90 ++
From: Tomasz Jeznach
Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
This will add support for ATS translation requests in Fault/Event
queues, Page-request queue and IOATC invalidations.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Fr
From: Tomasz Jeznach
This header will be used by the RISC-V IOMMU emulation to be added
in the next patch. Due to its size it's being sent in separate for
an easier review.
One thing to notice is that this header can be replaced by the future
Linux RISC-V IOMMU driver header, which would become
From: Tomasz Jeznach
The RISC-V IOMMU can be modelled as a PCIe device following the
guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU
as a PCIe device".
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair F
From: Tomasz Jeznach
The RISC-V IOMMU spec predicts that the IOMMU can use translation caches
to hold entries from the DDT. This includes implementation for all cache
commands that are marked as 'not implemented'.
There are some artifacts included in the cache that predicts s-stage and
g-stage e
From: Tomasz Jeznach
Extend memory transaction attributes with process identifier to allow
per-request address translation logic to use requester_id / process_id
to identify memory mapping (e.g. enabling IOMMU w/ PASID translations).
Signed-off-by: Tomasz Jeznach
Reviewed-by: Frank Chang
Revie
From: Tomasz Jeznach
DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
tr_response.
The DBG cap is always enabled. No on/off toggle is provided for it.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair F
Cc'ing the qemu-block@ list
On 3/9/24 20:13, DUO Labs wrote:
I know that the `cache` parameter for `-drive` controls the caching
behavior when writing from the guest to the host, but is there a way to
control the reading behavior host->guest? Currently, on HEAD, if I open
a file on both the gu
On 9/3/24 13:16, Daniel Henrique Barboza wrote:
From: Tomasz Jeznach
Extend memory transaction attributes with process identifier to allow
per-request address translation logic to use requester_id / process_id
to identify memory mapping (e.g. enabling IOMMU w/ PASID translations).
Signed-off-b
On Wed, Sep 04, 2024 at 01:58:15AM +0600, Dorjoy Chowdhury wrote:
> On Thu, Aug 29, 2024 at 1:11 AM Michael S. Tsirkin wrote:
> >
> > On Thu, Aug 29, 2024 at 01:04:05AM +0600, Dorjoy Chowdhury wrote:
> > > On Thu, Aug 29, 2024 at 12:28 AM Michael S. Tsirkin
> > > wrote:
> > > >
> > > > On Thu, A
On 3/9/24 18:07, Peter Maydell wrote:
Remove the pxa2xx-specific pxa2xx_mmci device.
Signed-off-by: Peter Maydell
---
include/hw/arm/pxa.h | 10 -
hw/sd/pxa2xx_mmci.c | 594 ---
hw/sd/meson.build| 1 -
hw/sd/trace-events | 4 -
4 files c
On 3/9/24 18:07, Peter Maydell wrote:
Remove the OMAP2 specific code from omap_mmc.c.
Signed-off-by: Peter Maydell
---
include/hw/arm/omap.h | 5
hw/sd/omap_mmc.c | 63 ---
2 files changed, 68 deletions(-)
-struct omap_mmc_s *omap2_mmc_
Update the Sun mouse implementation to use QemuInputHandler instead of the
legacy qemu_add_mouse_event_handler() function.
Note that this conversion adds extra sunmouse_* members to ESCCChannelState
but they are not added to the migration stream (similar to the Sun keyboard
members). If this were
On 9/3/24 13:38, Mark Cave-Ayland wrote:
Update the Sun mouse implementation to use QemuInputHandler instead of the
legacy qemu_add_mouse_event_handler() function.
Note that this conversion adds extra sunmouse_* members to ESCCChannelState
but they are not added to the migration stream (similar
On Wed, Sep 4, 2024, 2:32 AM Michael S. Tsirkin wrote:
> On Wed, Sep 04, 2024 at 01:58:15AM +0600, Dorjoy Chowdhury wrote:
> > On Thu, Aug 29, 2024 at 1:11 AM Michael S. Tsirkin
> wrote:
> > >
> > > On Thu, Aug 29, 2024 at 01:04:05AM +0600, Dorjoy Chowdhury wrote:
> > > > On Thu, Aug 29, 2024 at
On 9/3/24 13:10, Philippe Mathieu-Daudé wrote:
(Cc'ing Guenter who asked to keep the SX1 machine)
On 3/9/24 22:04, Philippe Mathieu-Daudé wrote:
sd_set_cb() was only used by omap2_mmc_init() which
got recently removed. Time to remove it. For historical
background on the me_no_qdev_me_kill_mammo
On 9/3/24 5:31 PM, Richard Henderson wrote:
On 9/3/24 13:16, Daniel Henrique Barboza wrote:
From: Tomasz Jeznach
Extend memory transaction attributes with process identifier to allow
per-request address translation logic to use requester_id / process_id
to identify memory mapping (e.g. enab
On 3/9/24 18:07, Peter Maydell wrote:
Now we have removed all the board types that it covers, we can move
the text about old Arm boards from deprecated.rst to
removed-features.rst, tweaking it appropriately.
Signed-off-by: Peter Maydell
---
docs/about/deprecated.rst | 15 ---
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