Hi, In this new version the only significant code change was made in patch 3, where we're no longer modifying the host address with the translated address. The remaining of the changes consist in adding more in-code docs (a.k.a comments) on the design choices made in the emulation.
The docs were also changed to mention that, to test this emulation, we're using the following kernel: https://github.com/ventanamicro/linux/tree/dev-upstream it is based on the latest kernel support posted by Tomasz with additional features like VFIO passthrough and irqbypass. Users can use this kernel for testing, if they want, until the kernel upstream support is more feature completed. At that point we'll remove this Ventana Micro github repo from the docs and point to the upstream kernel. Patches based on alistair/riscv-to-apply.next. All patches reviewed/acked. Changes from v6: - patch 2: - align RISCV_IOMMU_REG_ICVEC macro value 0x02F8 - patch 3: - do not modify the host address with the translated (guest) address in riscv_iommu_msi_write(), RISCV_IOMMU_MSI_PTE_M_BASIC case - added a comment explaining the need for the IOVA == GPA check - patch 8: - added a comment explaining the design decision to not cache identity-mapped translations in riscv_iommu_translate() - patch 12: - added extra info about how the IOMMU emulation is being tested and which kernel branch users can try it out - v6 link: https://lore.kernel.org/qemu-riscv/20240801154334.1009852-1-dbarb...@ventanamicro.com/ Daniel Henrique Barboza (4): pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device test/qtest: add riscv-iommu-pci tests qtest/riscv-iommu-test: add init queues test docs/specs: add riscv-iommu Tomasz Jeznach (8): exec/memtxattr: add process identifier to the transaction attributes hw/riscv: add riscv-iommu-bits.h hw/riscv: add RISC-V IOMMU base emulation hw/riscv: add riscv-iommu-pci reference device hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) hw/riscv/riscv-iommu: add ATS support hw/riscv/riscv-iommu: add DBG support docs/specs/index.rst | 1 + docs/specs/pci-ids.rst | 2 + docs/specs/riscv-iommu.rst | 90 ++ docs/system/riscv/virt.rst | 13 + hw/riscv/Kconfig | 4 + hw/riscv/meson.build | 1 + hw/riscv/riscv-iommu-bits.h | 421 ++++++ hw/riscv/riscv-iommu-pci.c | 202 +++ hw/riscv/riscv-iommu.c | 2431 ++++++++++++++++++++++++++++++ hw/riscv/riscv-iommu.h | 149 ++ hw/riscv/trace-events | 17 + hw/riscv/trace.h | 1 + hw/riscv/virt.c | 33 +- include/exec/memattrs.h | 5 + include/hw/pci/pci.h | 1 + include/hw/riscv/iommu.h | 36 + meson.build | 1 + tests/qtest/libqos/meson.build | 4 + tests/qtest/libqos/riscv-iommu.c | 76 + tests/qtest/libqos/riscv-iommu.h | 101 ++ tests/qtest/meson.build | 1 + tests/qtest/riscv-iommu-test.c | 220 +++ 22 files changed, 3809 insertions(+), 1 deletion(-) create mode 100644 docs/specs/riscv-iommu.rst create mode 100644 hw/riscv/riscv-iommu-bits.h create mode 100644 hw/riscv/riscv-iommu-pci.c create mode 100644 hw/riscv/riscv-iommu.c create mode 100644 hw/riscv/riscv-iommu.h create mode 100644 hw/riscv/trace-events create mode 100644 hw/riscv/trace.h create mode 100644 include/hw/riscv/iommu.h create mode 100644 tests/qtest/libqos/riscv-iommu.c create mode 100644 tests/qtest/libqos/riscv-iommu.h create mode 100644 tests/qtest/riscv-iommu-test.c -- 2.45.2
