On 3/9/24 16:45, Alireza Sanaee wrote:
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
available in tcg to decribe caches. One function `make_ccsidr` supports
two cases by carrying a parameter as FORMAT that can be LEGACY and
CCIDX which determines the specification of the register.
For CCSIDR register, 32 bit version follows specification [1].
Conversely, 64 bit version follows specification [2].
[1] B4.1.19, ARM Architecture Reference Manual ARMv7-A and ARMv7-R
edition, https://developer.arm.com/documentation/ddi0406
[2] D23.2.29, ARM Architecture Reference Manual for A-profile Architecture,
https://developer.arm.com/documentation/ddi0487/latest/
Signed-off-by: Alireza Sanaee <alireza.san...@huawei.com>
---
target/arm/cpu-features.h | 50 ++++++++++++++++++
target/arm/cpu64.c | 19 ++++---
target/arm/tcg/cpu64.c | 108 +++++++++++++++++++-------------------
3 files changed, 117 insertions(+), 60 deletions(-)
For minor / doc changes it helps reviewer to carry their tag ;)
https://www.qemu.org/docs/master/devel/submitting-a-patch.html#proper-use-of-reviewed-by-tags-can-aid-review
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
