Re: [PATCH v3 2/2] intel_iommu: Make PASID-cache and PIOTLB type invalid in legacy mode

On Wed, Aug 14, 2024 at 03:05:33AM +, Duan, Zhenzhong wrote: > > > >-Original Message- > >From: Liu, Yi L > >Subject: Re: [PATCH v3 2/2] intel_iommu: Make PASID-cache and PIOTLB > >type invalid in legacy mode > > > >On 2024/8/14 10:26, Zhenzhong Duan wrote: > >> In vtd_process_inv_de

Re: [PATCH v2 16/21] virtio-net: Use replay_schedule_bh_event for bhs that affect machine state

On Wed, Aug 14, 2024 at 04:05:34PM +1000, Nicholas Piggin wrote: > On Wed Aug 14, 2024 at 6:48 AM AEST, Michael S. Tsirkin wrote: > > On Tue, Aug 13, 2024 at 09:23:24PM +0100, Alex Bennée wrote: > > > From: Nicholas Piggin > > > > > > The regular qemu_bh_schedule() calls result in non-determinist

[PATCH v4 0/2] intel_iommu minor fixes

Hi Fixes two minor issues in intel iommu. See patch for details. Tested scalable mode and legacy mode with vfio device passthrough: PASS Tested intel-iommu.flat in kvm-unit-test: PASS Thanks Zhenzhong Changelog: v4: - Use 12 bytes commit id in fix tag (Liu Yi) v3: - add fix tag (Liu Yi) - coll

[PATCH v4 1/2] intel_iommu: Fix invalidation descriptor type field

According to spec, invalidation descriptor type is 7bits which is concatenation of bits[11:9] and bits[3:0] of invalidation descriptor. Currently we only pick bits[3:0] as the invalidation type and treat bits[11:9] as reserved zero. This is not a problem for now as bits[11:9] is zero for all curre

[PATCH v4 2/2] intel_iommu: Make PASID-cache and PIOTLB type invalid in legacy mode

In vtd_process_inv_desc(), VTD_INV_DESC_PC and VTD_INV_DESC_PIOTLB are bypassed without scalable mode check. These two types are not valid in legacy mode and we should report error. Fixes: 4a4f219e8a10 ("intel_iommu: add scalable-mode option to make scalable mode work") Suggested-by: Yi Liu Sign

Re: [PATCH v7 01/10] acpi/generic_event_device: add an APEI error device

On Wed, Aug 14, 2024 at 01:23:23AM +0200, Mauro Carvalho Chehab wrote: > Adds a generic error device to handle generic hardware error > events as specified at ACPI 6.5 specification at 18.3.2.7.2: > https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#event-notification-for-generic-err

Re: [PATCH v1 03/15] tcg: Fix register allocation constraints

On 2024/8/14 12:18, Richard Henderson wrote: On 8/14/24 13:30, LIU Zhiwei wrote: On 2024/8/14 11:08, Richard Henderson wrote: On 8/14/24 12:27, LIU Zhiwei wrote: On 2024/8/14 10:04, Richard Henderson wrote: On 8/14/24 10:58, LIU Zhiwei wrote: Thus if we want to use all registers of vector

[PATCH 2/9] i386/cpu: Enable fdp-excptn-only and zero-fcs-fds

- CPUID.(EAX=07H,ECX=0H):EBX[bit 6]: x87 FPU Data Pointer updated only on x87 exceptions if 1. - CPUID.(EAX=07H,ECX=0H):EBX[bit 13]: Deprecates FPU CS and FPU DS values if 1. i.e., X87 FCS and FDS are always zero. Define names for them so that they can be exposed to guest with -cpu host. Als

[PATCH 7/9] i386/cpu: Suppress CPUID values not defined by Intel

Some CPUID leaves are defined by AMD while it also gets exposed to Intel VMs by QEMU. It causes no issue with current VMs however it will not work with Intel TDX because these CPUID leaves are enforced by TDX module as reserved. Stop to advertise them to Intel VMs when vendor_cpuid_only is true.

[PATCH 3/9] i386/cpu: Add support for bits in CPUID.7_2.EDX

KVM started to report the support of bit 0-5 since commit eefe5e668209 ("Advertise CPUID.(EAX=7,ECX=2):EDX[5:0] to userspace") Allow them to be exposed to guest in QEMU. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targe

[PATCH 8/9] i386/cpu: Drop AMD alias bits in FEAT_8000_0001_EDX for non-AMD guests

The AMD alias bits are reserved for Intel. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fed805e04aeb..85ce405ece80 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6118,6 +6118,11 @@

[PATCH 5/9] i386/cpu: Construct CPUID 2 as stateful iff times > 1

When times == 1, the CPUID leaf 2 is not stateful. Signed-off-by: Xiaoyao Li --- target/i386/kvm/kvm.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index c168ff5691df..6618259f265c 100644 --- a/target/i386/kvm/kvm.c +++ b

[PATCH 1/9] i386/cpu: Don't construct a all-zero entry for CPUID[0xD 0x3f]

Currently, QEMU always constructs a all-zero CPUID entry for CPUID[0xD 0x3f]. It's meaningless to construct such a leaf as the end of leaf 0xD. Rework the logic of how subleaves of 0xD are constructed to get rid of such all-zero value of subleaf 0x3f. Signed-off-by: Xiaoyao Li --- target/i386/k

[PATCH 9/9] i386/cpu: Make invtsc migratable when user sets tsc-khz explicitly

When user sets tsc-frequency explicitly, the invtsc feature is actually migratable because the tsc-frequency is supposed to be fixed during the migration. See commit d99569d9d856 ("kvm: Allow invtsc migration if tsc-khz is set explicitly") for referrence. Signed-off-by: Xiaoyao Li --- target/i3

[PATCH 6/9] i386/cpu: Set topology info in 0x80000008.ECX only for AMD CPUs

The whole ECX of CPUID 0x8008 is reserved for Intel. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5bee84333089..7a4835289760 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu

[PATCH 4/9] i386/cpu: Construct valid CPUID leaf 5 iff CPUID_EXT_MONITOR

When CPUID_EXT_MONITOR is not set, it means no support of MONITOR/MWAIT leaf, i.e., CPUID leaf 5. Signed-off-by: Xiaoyao Li --- target/i386/cpu.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 03376ccf3e75..5bee8433308

[PATCH 0/9] Misc patches for x86 CPUID

This series is a misc collection of patches for x86 CPUID. It contains patches to add support for new CPUID bit, to fix the construction of some CPUID leaves, to not expose AMD defined bits on Intel guest, and to make invtsc migratable contioned on user_tsc_khz. All of them are found during TDX de

Re: [PATCH v3 2/5] machine/nitro-enclave: Add vhost-user-vsock device

On 13.08.24 20:02, Dorjoy Chowdhury wrote: On Mon, Aug 12, 2024 at 8:24 PM Daniel P. Berrangé wrote: On Sat, Aug 10, 2024 at 10:44:59PM +0600, Dorjoy Chowdhury wrote: AWS Nitro Enclaves have built-in vhost-vsock device support which enables applications in enclave VMs to communicate with the

Re: [PATCH v1 05/15] tcg/riscv: Add riscv vset{i}vli support

On 8/13/24 21:34, LIU Zhiwei wrote: From: TANG Tiancheng In RISC-V, vector operations require initial configuration using the vset{i}vl{i} instruction. This instruction: 1. Sets the vector length (vl) in bytes 2. Configures the vtype register, which includes: SEW (Single Element Wid

Re: [PATCH v2 08/21] buildsys: Fix building without plugins on Darwin

On 13/8/24 22:23, Alex Bennée wrote: From: Philippe Mathieu-Daudé Since commit 0082475e26 the plugin symbol list is unconditionally added to the linker flags, leading to a build failure: Undefined symbols for architecture arm64: "_qemu_plugin_entry_code", referenced from:

[PATCH 00/11] RISC-V: support CLIC v0.9 specification

[Resending to include qemu-devel and add numbers to the patches] This patch set gives an implementation of "RISC-V Core-Local Interrupt Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where you can find the pdf format or the source code. This is based on the implementation from 2

[PATCH 03/11] hw/intc: Add CLIC device

From: Ian Brockbank The Core-Local Interrupt Controller (CLIC) provides low-latency, vectored, pre-emptive interrupts for RISC-V systems. The CLIC also supports a new Selective Hardware Vectoring feature that allow users to optimize each interrupt for either faster response or smaller code size.

[PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode

From: Ian Brockbank The interrupt-level threshold (xintthresh) CSR holds an 8-bit field for the threshold level of the associated privilege mode. For horizontal interrupts, only the ones with higher interrupt levels than the threshold level are allowed to preempt. Signed-off-by: Ian Brockbank

[PATCH 01/11] target/riscv: Add CLIC CSR mintstatus

From: Ian Brockbank CSR mintstatus holds the active interrupt level for each supported privilege mode. sintstatus, and user, uintstatus, provide restricted views of mintstatus. Signed-off-by: Ian Brockbank Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 3 +++ target/riscv/cpu_bits.h

[PATCH 04/11] target/riscv: Update CSR xie in CLIC mode

From: Ian Brockbank The xie CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt enables (clicintie[i]). Writes to xie will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei Signed-off-by: Ian Brockbank --- target/riscv/csr.c

[PATCH 05/11] target/riscv: Update CSR xip in CLIC mode

From: Ian Brockbank The xip CSR appears hardwired to zero in CLIC mode, replaced by separate memory-mapped interrupt pendings (clicintip[i]). Writes to xip will be ignored and will not trap (i.e., no access faults). Signed-off-by: LIU Zhiwei Signed-off-by: Ian Brockbank --- target/riscv/csr.c

[PATCH 07/11] target/riscv: Update CSR xnxti in CLIC mode

From: Ian Brockbank The CSR can be used by software to service the next horizontal interrupt when it has greater level than the saved interrupt context (held in xcause`.pil`) and greater level than the interrupt threshold of the corresponding privilege mode, Signed-off-by: LIU Zhiwei Signed-off

[PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode

From: Ian Brockbank The new CLIC interrupt-handling mode is encoded as a new state in the existing WARL xtvec register, where the low two bits of are 11. Signed-off-by: LIU Zhiwei Signed-off-by: Ian Brockbank --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 2 ++ target/riscv/c

Re: [PATCH-for-9.1 v3 1/2] target/mips: Pass page table entry size as MemOp to get_pte()

On 13/8/24 23:44, Richard Henderson wrote: On 8/13/24 23:53, Philippe Mathieu-Daudé wrote: @@ -607,11 +607,11 @@ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size,   }   static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry, -    int entry_size, int ptei

Re: [PATCH v1 06/15] tcg/riscv: Implement vector load/store

On 8/13/24 21:34, LIU Zhiwei wrote: @@ -827,14 +850,59 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, intptr_t arg2) { -RISCVInsn insn = type == TCG_TYPE_I32 ? OP

[PATCH-for-9.1 v4 0/3] target/mips: Use correct MMU index in get_pte()

Since v3: - Fixed size in get_tlb_entry_layout (rth) Since v2: - Use MemOp (rth) Propage ptw_mmu_idx to get_pte() and use it via the cpu_ld/st_code_mmu() API. Philippe Mathieu-Daudé (3): target/mips: Pass page table entry size as MemOp to get_pte() target/mips: Use correct MMU index in get

[PATCH-for-9.1 v4 1/3] target/mips: Pass page table entry size as MemOp to get_pte()

In order to simplify the next commit, pass the PTE size as MemOp. Rename: native_shift -> native_op directory_shift -> directory_mop leaf_shift -> leaf_mop Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/sysemu/tl

[PATCH-for-9.1 v4 2/3] target/mips: Use correct MMU index in get_pte()

When refactoring page_table_walk_refill() in commit 4e999bf419 we missed the indirect call to cpu_mmu_index() in get_pte(): page_table_walk_refill() -> get_pte() -> cpu_ld[lq]_code() -> cpu_mmu_index() Since we don't mask anymore the modes in hflags, cpu_mmu_index() can return UM

[PATCH-for-9.1 v4 3/3] target/mips: Load PTE as DATA

PTE is not CODE so load it as normal DATA access. Fixes: 074cfcb4da ("Implement hardware page table walker for MIPS32") Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/sysemu/tlb_helper.c | 4 ++-- 1 file changed, 2 inser

Re: [PATCH v1 07/15] tcg/riscv: Implement vector mov/dup{m/i}

On 8/13/24 21:34, LIU Zhiwei wrote: @@ -641,6 +645,13 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) case TCG_TYPE_I64: tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); break; +case TCG_TYPE_V64: +case TCG_TYPE_V128: +case TCG_TYPE

Re: [PATCH v1 08/15] tcg/riscv: Add support for basic vector opcodes

On 8/13/24 21:34, LIU Zhiwei wrote: From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 33 + 2 files changed, 34 insertions(+) diff --git a/tcg/riscv/tcg-ta

Re: [PATCH v1 08/15] tcg/riscv: Add support for basic vector opcodes

On 8/13/24 21:34, LIU Zhiwei wrote: +OPC_VADD_VV = 0x57 | V_OPIVV, +OPC_VSUB_VV = 0x857 | V_OPIVV, +OPC_VAND_VV = 0x2457 | V_OPIVV, +OPC_VOR_VV = 0x2857 | V_OPIVV, +OPC_VXOR_VV = 0x2c57 | V_OPIVV, Immediate operand variants to be handled as a follow-up? r~

Re: [PATCH v1 09/15] tcg/riscv: Implement vector cmp ops

On 8/13/24 21:34, LIU Zhiwei wrote: From: TANG Tiancheng 1.Address immediate value constraints in RISC-V Vector Extension 1.0 for comparison instructions. 2.Extend comparison results from mask registers to SEW-width elements, following recommendations in The RISC-V SPEC Volume I (Version 20

Re: [PATCH v1 10/15] tcg/riscv: Implement vector not/neg ops

On 8/13/24 21:34, LIU Zhiwei wrote: @@ -2312,6 +2314,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_xor_vec: tcg_out_opc_vv(s, OPC_VXOR_VV, a0, a1, a2, true); break; +case INDEX_op_not_vec: +tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1,

Re: [PATCH v1 14/15] tcg/riscv: Implement vector roti/v/x shi ops

On 8/13/24 21:34, LIU Zhiwei wrote: +case INDEX_op_shli_vec: +if (a2 > 31) { +t2 = tcg_temp_new_i32(); +tcg_gen_movi_i32(t2, (int32_t)a2); +tcg_gen_shls_vec(vece, v0, v1, t2); Drop the movi, just pass tcg_constant_i32(a2) as the second source. +

[PATCH] meson: add 'qemuutil' dependency for block.c

The macro block_module_load() used by block.c is a wrapper around module_load(), which is implemented in util/module.c. Fixes linking for a future binary or downstream binary that does not depend on 'qemuutil' directly, but does depend on 'block'. Signed-off-by: Fiona Ebner --- meson.build | 2

Re: [PATCH v2 0/3] MIPS misc patches

On 21/6/24 15:11, Jiaxun Yang wrote: Jiaxun Yang (3): hw/mips/loongson3_virt: Store core_iocsr into LoongsonMachineState hw/mips/loongson3_virt: Fix condition of IPI IOCSR connection linux-user/mips64: Use MIPS64R2-generic as default CPU type Reviewed-by: Philippe Mathieu-

Re: [PATCH v1 15/15] tcg/riscv: Enable vector TCG host-native

On 8/13/24 21:34, LIU Zhiwei wrote: From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.h | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index eb5129a976..fe6c50e

Re: [PATCH v5 06/16] sev: Update launch_update_data functions to use Error handling

The class function and implementations for updating launch data return a code in case of error. In some cases an error message is generated and in other cases, just the error return value is used. This small refactor adds an 'Error **errp' parameter to all functions which consistently set an erro

Re: [PATCH 0/2] target/i386: Fix carry flag for BLSI

On 8/7/24 15:41, Richard Henderson wrote: On 8/1/24 17:58, Richard Henderson wrote: Fix #2175. r~ Richard Henderson (2):    target/i386: Split out gen_prepare_val_nz    target/i386: Fix carry flag for BLSI   target/i386/cpu.h    |  5 +   target/i386/tcg/cc_helper.c

Re: [PATCH for-9.2 01/10] hw/s390/virtio-ccw: Convert to three-phase reset

On 13/08/2024 18.52, Peter Maydell wrote: Convert the virtio-ccw code to three-phase reset. This allows us to remove a call to device_class_set_parent_reset(), replacing it with the three-phase equivalent resettable_class_set_parent_phases(). Removing all the device_class_set_parent_reset() uses

Re: [PATCH for-9.2 05/10] hw/dma/xilinx_axidma: Use semicolon at end of statement, not comma

On 13/08/2024 18.52, Peter Maydell wrote: In axidma_class_init() we accidentally used a comma at the end of a statement rather than a semicolon. This has no ill effects, but it's obviously not intended and it means that Coccinelle scripts for instance will fail to match on the two statements. Use

Re: [PATCH for-9.2 02/10] target/s390: Convert CPU to Resettable interface

On 14/08/2024 01.03, Richard Henderson wrote: On 8/14/24 02:52, Peter Maydell wrote:   static void sigp_cpu_reset(CPUState *cs, run_on_cpu_data arg)   { -    S390CPU *cpu = S390_CPU(cs); -    S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);   SigpInfo *si = arg.host_ptr;   cpu_synchronize_st

Re: [RFC PATCH 0/2] meson: Specify Rust edition by rust_std=20XX

On Wed, 14 Aug 2024 12:08, Junjie Mao wrote: The official way to specify Rust edition in meson is the rust_std build option [1]. It is used for generating --edition rustc options and filling rust-project.json which provides project layout information to rust-analyzer. Specifying Rust edition by

Re: [PATCH v2 08/17] intel_iommu: Set accessed and dirty bits during first stage translation

On 2024/8/5 14:27, Zhenzhong Duan wrote: From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 3 +++ hw/i386/intel_iommu.c | 24 2 files changed, 27 insertions(+) diff --git

Re: [PATCH 6/9] i386/cpu: Set topology info in 0x80000008.ECX only for AMD CPUs

On 8/14/2024 3:54 PM, Xiaoyao Li wrote: > The whole ECX of CPUID 0x8008 is reserved for Intel. > > Signed-off-by: Xiaoyao Li > --- > target/i386/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 5bee84333089..7a48

Re: [PATCH v1 04/10] hw/arm: xenpvh: Add support for SMP guests

On Tue, Aug 13, 2024 at 03:52:32PM -0700, Stefano Stabellini wrote: > On Tue, 13 Aug 2024, Edgar E. Iglesias wrote: > > On Mon, Aug 12, 2024 at 06:47:17PM -0700, Stefano Stabellini wrote: > > > On Mon, 12 Aug 2024, Edgar E. Iglesias wrote: > > > > From: "Edgar E. Iglesias" > > > > > > > > Add SMP

Re: [PATCH] qemu-guest-agent: Update the logfile path of qga-fsfreeze-hook.log

This bug looks specific to the RedHat SELinux configuration. Is this any reason to move LOGFILE except this? Best Regards, Konstantin Kostiuk. On Tue, Aug 13, 2024 at 6:11 AM Dehan Meng wrote: > Since '/var/log/qga-fsfreeze-hook.log' is not included to proper > selinux context 'system_u:object

[PATCH v5 1/3] tests/acpi: pc: allow DSDT acpi table changes

Signed-off-by: Ricardo Ribalda --- tests/qtest/bios-tables-test-allowed-diff.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..f81f4e2469 100644 --- a/tests/qtest/bios

[PATCH v5 3/3] tests/acpi: pc: update golden masters for DSDT

Signed-off-by: Ricardo Ribalda --- tests/data/acpi/x86/pc/DSDT | Bin 6830 -> 8527 bytes tests/data/acpi/x86/pc/DSDT.acpierst| Bin 6741 -> 8438 bytes tests/data/acpi/x86/pc/DSDT.acpihmat| Bin 8155 -> 9852 bytes tests/data/acpi/x86/pc/DSDT.bridge | Bin 13

[PATCH v5 2/3] hw/i386/acpi-build: Return a pre-computed _PRT table

When qemu runs without kvm acceleration the ACPI executions take a great amount of time. If they take more than the default time (30sec), the ACPI calls fail and the system might not behave correctly. Now the _PRT table is computed on the fly. We can drastically reduce the execution of the _PRT me

[PATCH v5 0/3] hw/i386/acpi: Pre-compute the _PRT table

Today for x86 the _PRT() table is computed in runtime. Under some configurations, computing the _PRT table can take more than 30 seconds and the ACPI timeout is violated. This patchset modifies _PRT() to return a pre-computed table. Changelog v3->v4 Thanks Richard: - Make link_name struct static

Re: [PATCH v2 07/17] intel_iommu: Check if the input address is canonical

On 2024/8/5 14:27, Zhenzhong Duan wrote: From: Clément Mathieu--Drif First stage translation must fail if the address to translate is not canonical. Signed-off-by: Clément Mathieu--Drif Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 2 ++ hw/i386/intel_iommu.c

Re: [PATCH v1 05/10] hw/arm: xenpvh: Break out a common PVH module

On Mon, Aug 12, 2024 at 06:47:51PM -0700, Stefano Stabellini wrote: > On Mon, 12 Aug 2024, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > Break out a common Xen PVH module in preparation for > > adding a x86 Xen PVH Machine. > > > > Signed-off-by: Edgar E. Iglesias > > --- > >

Re: [PATCH v2 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting

On 2024/8/5 14:27, Zhenzhong Duan wrote: When host IOMMU doesn't support FS1GP but vIOMMU does, host IOMMU can't translate stage-1 page table from guest correctly. this series is for emulated devices, so the above statement does not belong to this series. Is there any other reason to have this

Re: [PATCH v2 14/17] intel_iommu: Set default aw_bits to 48 in scalable modren mode

On 2024/8/5 14:27, Zhenzhong Duan wrote: According to VTD spec, stage-1 page table could support 4-level and 5-level paging. However, 5-level paging translation emulation is unsupported yet. That means the only supported value for aw_bits is 48. So default aw_bits to 48 in scalable modern mode.

Re: [PATCH v2 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation

On 2024/8/5 14:27, Zhenzhong Duan wrote: Per spec 6.5.2.4, PADID-selective PASID-based iotlb invalidation will flush stage-2 iotlb entries with matching domain id and pasid. With scalable modern mode introduced, guest could send PASID-selective PASID-based iotlb invalidation to flush both stage-

Re: [PATCH v7 01/10] acpi/generic_event_device: add an APEI error device

On Wed, 14 Aug 2024 01:23:23 +0200 Mauro Carvalho Chehab wrote: > Adds a generic error device to handle generic hardware error > events as specified at ACPI 6.5 specification at 18.3.2.7.2: > https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#event-notification-for-generic-error-so

Re: [PATCH v2 2/4] reset: Add RESET_TYPE_WAKEUP

On Tue, Aug 13, 2024 at 6:37 PM Peter Maydell wrote: > > On Tue, 13 Aug 2024 at 16:39, Juraj Marcin wrote: > > > > Some devices need to distinguish cold start reset from waking up from a > > suspended state. This patch adds new value to the enum, and updates the > > i386 wakeup method to use this

Re: [PATCH v7 02/10] arm/virt: Wire up a GED error device for ACPI / GHES

On Wed, 14 Aug 2024 01:23:24 +0200 Mauro Carvalho Chehab wrote: > Adds support to ARM virtualization to allow handling > generic error ACPI Event via GED & error source device. > > It is aligned with Linux Kernel patch: > https://lore.kernel.org/lkml/1272350481-27951-8-git-send-email-ying.hu...@

Re: [PATCH for-9.2 10/10] hw: Remove device_phases_reset()

On Wed, 14 Aug 2024 at 01:53, Richard Henderson wrote: > > On 8/14/24 02:52, Peter Maydell wrote: > > Currently we have transitional machinery between legacy reset > > and three phase reset that works in two directions: > > * if you invoke three phase reset on a device which has set > > theD

Re: [PATCH] hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values

On Wed, 14 Aug 2024 at 05:35, Michael Tokarev wrote: > > 18.06.2024 16:55, Zheyu Ma wrote: > > This commit adds validation checks for the MCOPRE and MCOSEL values in > > the rcc_update_cfgr_register function. If the MCOPRE value exceeds > > 0b100 or the MCOSEL value exceeds 0b111, an error is logg

[PATCH-for-9.1 2/4] linux-user/mips: Select Octeon68XX CPU for Octeon binaries

The Octeon68XX CPU is available since commit 9a6046a655 ("target/mips: introduce Cavium Octeon CPU model"). Cc: Pavel Dovgalyuk Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1722 Reported-by: Johnathan Hữu Trí Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé ---

[PATCH-for-9.1 0/4] linux-user/mips: Select correct CPUs

Improve CPU type selection: - Remove R5900 - Cover Octeon / R2 / Loongson* Philippe Mathieu-Daudé (4): linux-user/mips: Do not try to use removed R5900 CPU linux-user/mips: Select Octeon68XX CPU for Octeon binaries linux-user/mips: Select MIPS64R2-generic for Rel2 binaries linux-user/mips:

[PATCH-for-9.1 1/4] linux-user/mips: Do not try to use removed R5900 CPU

R5900 emulation was removed in commit 823f2897bd. Remove it from ELF parsing in order to avoid: $ qemu-mipsn32 ./test5900 qemu-mipsn32: unable to find CPU model 'R5900' This reverts commit 4d9e5a0eb7df6e98ac6cf5e16029f35dd05b9537. Fixes: 823f2897bd ("target/mips: Disable R5900 support") Sign

[PATCH-for-9.1? 4/4] linux-user/mips: Select Loongson CPU for Loongson binaries

Signed-off-by: Philippe Mathieu-Daudé --- linux-user/mips64/target_elf.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/linux-user/mips64/target_elf.h b/linux-user/mips64/target_elf.h index a3a8b2e385..502af9d278 100644 --- a/linux-user/mips64/target_elf.h +++ b/linux-user/mips64/targe

[PATCH-for-9.1 3/4] linux-user/mips: Select MIPS64R2-generic for Rel2 binaries

Cc: YunQiang Su Reported-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- linux-user/mips64/target_elf.h | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/linux-user/mips64/target_elf.h b/linux-user/mips64/target_elf.h index ce6fb6541e..a3a8b2e385 100644 --- a/l

Re: [PATCH for-9.2 06/10] hw/remote/message.c: Don't directly invoke DeviceClass:reset

On 13/8/24 18:52, Peter Maydell wrote: Directly invoking the DeviceClass::reset method is a bad idea, because if the device is using three-phase reset then it relies on transitional reset machinery which is likely to disappear at some point. This seems like fix-for-9.1 material. Reset the dev

Re: [PATCH v7 03/10] acpi/ghes: Add support for GED error device

On Wed, 14 Aug 2024 01:23:25 +0200 Mauro Carvalho Chehab wrote: > From: Jonathan Cameron > > As a GED error device is now defined, add another type > of notification. > > Add error notification to GHES v2 using a GED error device GED > triggered via interrupt. > > [mchehab: do some cleanups a

Re: [PATCH v7 04/10] qapi/acpi-hest: add an interface to do generic CPER error injection

On Wed, 14 Aug 2024 01:23:26 +0200 Mauro Carvalho Chehab wrote: > Creates a QMP command to be used for generic ACPI APEI hardware error > injection (HEST) via GHESv2. > > The actual GHES code will be added at the followup patch. > > Signed-off-by: Mauro Carvalho Chehab > Signed-off-by: Shiju J

[PATCH] hw/cxl: fixed the determination of illegal physical addresses

When physical address range in the input payload of scan media command exceeds static_mem_size but does not exceed the sum of static and dynamic memory, the scan media mailbox command unexpectedly returns an invalid input. It is handled differently depending on whether dynamic memory is present or

Re: [PATCH for-9.2 00/10] s390: Convert virtio-ccw, cpu to three-phase reset, and followup cleanup

Am 13.08.24 um 18:52 schrieb Peter Maydell: The main aim of this patchseries is to remove the two remaining uses of device_class_set_parent_reset() in the tree, which are virtio-ccw and the s390 CPU class. Doing that lets us do some followup cleanup. (The diffstat looks alarming but is almost all

Re: [PATCH] contrib/plugins: Add a plugin to generate basic block vectors

On 8/13/24 23:32, Akihiko Odaki wrote: On 2024/08/14 14:41, Pierrick Bouvier wrote: On 8/13/24 21:56, Akihiko Odaki wrote: On 2024/08/14 4:20, Pierrick Bouvier wrote: Hi Akihiko, and thanks for contributing this new plugin. Hi, Thanks for reviewing Recently, plugins documentation has bee

Re: [PATCH v1 08/10] hw/xen: pvh-common: Add support for creating PCIe/GPEX

On Mon, Aug 12, 2024 at 06:48:37PM -0700, Stefano Stabellini wrote: > On Mon, 12 Aug 2024, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > Add support for optionally creating a PCIe/GPEX controller. > > > > Signed-off-by: Edgar E. Iglesias > > --- > > hw/xen/xen-pvh-common.c

Re: [PATCH v1 09/10] hw/i386/xen: Add a Xen PVH x86 machine

On Mon, Aug 12, 2024 at 06:48:52PM -0700, Stefano Stabellini wrote: > On Mon, 12 Aug 2024, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > This adds a Xen PVH x86 machine based on the PVH Common > > module used by the ARM PVH machine. > > > > Signed-off-by: Edgar E. Iglesias > >

RE: [PATCH 00/11] RISC-V: support CLIC v0.9 specification

Apologies. Please ignore this patchset. Something seems to have gone wrong during the preparation and merge to current; I am working on a replacement, and will send v2 once I am happy with it. Ian Brockbank C.Eng. Senior Staff Software Engineer Cirrus Logic | cirrus.com | t: +44 131 272 7145 | m

[PULL 1/1] target/i386: Fix arguments for vmsr_read_thread_stat()

From: Anthony Harivel Snapshot of the stat utime and stime for each thread, taken before and after the pause, must be stored in separate locations Signed-off-by: Anthony Harivel Link: https://lore.kernel.org/r/20240807124320.1741124-2-ahari...@redhat.com Signed-off-by: Paolo Bonzini --- targe

[PULL 0/1] target/i386 patch for QEMU 9.1

The following changes since commit 3ef11c991e501768f2fa646e8438f075be1cd2f5: po: update Italian translation (2024-08-13 19:01:42 +0200) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you to fetch changes up to a6e65975c3fac1b2f067fef8eeed92

[PATCH 1/4] meson: hide tsan related warnings

When building with gcc-12 -fsanitize=thread, gcc reports some constructions not supported with tsan. Found on debian stable. qemu/include/qemu/atomic.h:36:52: error: ‘atomic_thread_fence’ is not supported with ‘-fsanitize=thread’ [-Werror=tsan] 36 | #define smp_mb() ({ barr

[PATCH 0/4] build qemu with gcc and tsan

While working on a concurrency bug, I gave a try to tsan builds for QEMU. I noticed it didn't build out of the box with recent gcc, so I fixed compilation. In more, updated documentation to explain how to build a sanitized glib to avoid false positives related to glib synchronisation primitives. P

[PATCH 2/4] target/i386: fix build warning (gcc-12 -fsanitize=thread)

Found on debian stable. ../target/i386/kvm/kvm.c: In function ‘kvm_handle_rdmsr’: ../target/i386/kvm/kvm.c:5345:1: error: control reaches end of non-void function [-Werror=return-type] 5345 | } | ^ ../target/i386/kvm/kvm.c: In function ‘kvm_handle_wrmsr’: ../target/i386/kvm/kvm.c:5364:1: e

[PATCH 3/4] target/s390x: fix build warning (gcc-12 -fsanitize=thread)

Found on debian stable. ../target/s390x/tcg/translate.c: In function ‘get_mem_index’: ../target/s390x/tcg/translate.c:398:1: error: control reaches end of non-void function [-Werror=return-type] 398 | } --- target/s390x/tcg/translate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/

[PATCH 4/4] docs/devel: update tsan build documentation

Mention it's now possible to build with gcc, instead of clang, and explain how to build a sanitized glib version. --- docs/devel/testing.rst | 26 ++ 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/docs/devel/testing.rst b/docs/devel/testing.rst index af73d3d

Re: [PATCH v7 04/10] qapi/acpi-hest: add an interface to do generic CPER error injection

Em Wed, 14 Aug 2024 14:53:22 +0100 Jonathan Cameron escreveu: > On Wed, 14 Aug 2024 01:23:26 +0200 > Mauro Carvalho Chehab wrote: > > > Creates a QMP command to be used for generic ACPI APEI hardware error > > injection (HEST) via GHESv2. > > > > The actual GHES code will be added at the follo

Re: [PATCH v2 16/21] virtio-net: Use replay_schedule_bh_event for bhs that affect machine state

"Michael S. Tsirkin" writes: > On Wed, Aug 14, 2024 at 04:05:34PM +1000, Nicholas Piggin wrote: >> On Wed Aug 14, 2024 at 6:48 AM AEST, Michael S. Tsirkin wrote: >> > On Tue, Aug 13, 2024 at 09:23:24PM +0100, Alex Bennée wrote: >> > > From: Nicholas Piggin >> > > >> > > The regular qemu_bh_sche

[PATCH 0/5] Serial device cleanup

This series extracts TYPE_SERIAL_MM into its own module and introduces a dedicated header for TYPE_SERIAL_ISA. The result is that no board directly depends on CONFIG_SERIAL or includes hw/char/serial.h any more. Bernhard Beschow (5): hw: Remove unused inclusion of hw/char/serial.h hw/char/seri

[PATCH 3/5] hw/ppc/Kconfig: Add missing SERIAL_ISA dependency to POWERNV machine

The machine calls serial_hds_isa_init() which is provided by serial-isa.c, guarded by SERIAL_ISA. Signed-off-by: Bernhard Beschow --- hw/ppc/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index c235519881..5addad1124 100644 --- a/hw/ppc/Kconfig +++ b/

[PATCH 5/5] hw/char: Extract serial-mm

hw/char/serial currently contains the implementation of both TYPE_SERIAL and TYPE_SERIAL_MM. According to serial_class_init(), TYPE_SERIAL is an internal class while TYPE_SERIAL_MM is used by numerous machine types directly. Let's move the latter into its own module which makes the dependencies mor

[PATCH 2/5] hw/char/serial: Remove unused funtion

The serial port's frequency is set via the "baudbase" property nowadays. Signed-off-by: Bernhard Beschow --- include/hw/char/serial.h | 2 -- hw/char/serial.c | 7 --- 2 files changed, 9 deletions(-) diff --git a/include/hw/char/serial.h b/include/hw/char/serial.h index 6e14099ee7..

[PATCH 1/5] hw: Remove unused inclusion of hw/char/serial.h

Signed-off-by: Bernhard Beschow --- hw/char/riscv_htif.c | 1 - hw/ppc/prep.c| 1 - hw/riscv/sifive_e.c | 1 - hw/riscv/sifive_u.c | 1 - 4 files changed, 4 deletions(-) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 9bef60def1..54fd55c3e6 100644 --- a/hw/char/riscv_hti

[PATCH 4/5] hw/char/serial.h: Extract serial-isa.h

The includes where updated based on compile errors. Now, the inclusion of the header roughly matches Kconfig dependencies: # grep -r -e "select SERIAL_ISA" hw/ppc/Kconfig:select SERIAL_ISA hw/isa/Kconfig:select SERIAL_ISA hw/sparc64/Kconfig:select SERIAL_ISA hw/i386/Kconfig:

Re: [PATCH v1 1/1] block/file-posix: Avoid maybe-uninitialized warning

On Mon, Aug 12, 2024 at 04:43:23PM GMT, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Avoid a maybe-uninitialized warning in raw_refresh_zoned_limits() > by initializing zoned. > > With GCC 14.1.0: > In function ‘raw_refresh_zoned_limits’, > inlined from ‘raw_refresh_limits’ at ..

[PATCH v2] target/sparc: emulate floating point queue when raising fp traps

From 9265233081fae546c0459792598a9f1688ddb020 Mon Sep 17 00:00:00 2001 From: Carl Hauser Date: Sat, 10 Aug 2024 15:09:39 -0700 Subject: [PATCH v2] target/sparc: emulate floating point queue when raising fp traps Sparc 32-bit machines perform floating point operations in an asynchronous co-p

Re: [RFC V1 2/7] migration: skip dirty memory tracking for cpr

On 8/12/2024 2:57 PM, Fabiano Rosas wrote: Steve Sistare writes: CPR preserves memory in place, so there is no need to track dirty memory. By skipping it, CPR can support devices that do not support tracking. Signed-off-by: Steve Sistare --- system/memory.c | 11 +++ 1 file change

Re: [PATCH for-9.2 00/10] s390: Convert virtio-ccw, cpu to three-phase reset, and followup cleanup

On Wed, 14 Aug 2024 at 15:22, Christian Borntraeger wrote: > > Am 13.08.24 um 18:52 schrieb Peter Maydell: > > The main aim of this patchseries is to remove the two remaining uses > > of device_class_set_parent_reset() in the tree, which are virtio-ccw > > and the s390 CPU class. Doing that lets u

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