Deprecate SD spec v1.10, use v3.01 as new default.
Philippe Mathieu-Daudé (3):
hw/sd/sdcard: Deprecate support for spec v1.10
hw/sd/sdcard: Use spec v3.01 by default
hw/sd/sdcard: Remove support for spec v1.10
docs/about/removed-features.rst | 5 +
include/hw/sd/sd.h | 1
Recent SDHCI expect cards to support the v3.01 spec
to negociate lower I/O voltage. Select it by default.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index a48010cfc1..d0a1d5db18 100644
--- a/hw/
Support for spec v1.10 was deprecated in QEMU v9.1.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/about/deprecated.rst | 6 --
docs/about/removed-features.rst | 5 +
include/hw/sd/sd.h | 1 -
hw/sd/sd.c | 12 ++--
4 files changed, 7 ins
We use the v2.00 spec by default since commit 2f0939c234
("sdcard: Add a 'spec_version' property, default to Spec v2.00").
Time to deprecate the v1.10 which doesn't bring much, and
is not tested.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/about/deprecated.rst | 6 ++
1 file changed, 6 in
Alexey Baturo 於 2024年5月11日 週六 下午6:12寫道：
>
> From: Alexey Baturo
>
> Signed-off-by: Alexey Baturo
>
> Reviewed-by: Alistair Francis
> ---
> target/riscv/cpu.h | 8
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/cpu_cfg.h | 3 +++
> target/riscv/csr.c | 11 +++
>
> -Original Message-
> From: Yichen Wang
> Sent: Thursday, June 27, 2024 8:17 AM
> To: Liu, Yuan1
> Cc: Bryan Zhang ; qemu-devel@nongnu.org;
> pet...@redhat.com; faro...@suse.de; berra...@redhat.com; Zou, Nanhai
> ; hao.xi...@linux.dev
> Subject: Re: [PATCH v2 2/5] migration: Add migratio
On 6/26/24 11:05 AM, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI responder.
This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI function control is mapped into the SPI register space to enable full
control by firmware. I
Alexey Baturo 於 2024年5月11日 週六 下午6:12寫道：
>
> From: Alexey Baturo
>
> Signed-off-by: Alexey Baturo
>
> Reviewed-by: Alistair Francis
> ---
> target/riscv/cpu.h | 8
> target/riscv/cpu_bits.h | 3 +++
> target/riscv/cpu_cfg.h | 3 +++
> target/riscv/csr.c | 11 +++
>
On 6/27/24 9:10 AM, Philippe Mathieu-Daudé wrote:
We use the v2.00 spec by default since commit 2f0939c234
("sdcard: Add a 'spec_version' property, default to Spec v2.00").
Time to deprecate the v1.10 which doesn't bring much, and
is not tested.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed
On Jun 26 2024, Warner Losh wrote:
> On Wed, Jun 26, 2024 at 9:48 AM Richard Henderson <
> richard.hender...@linaro.org> wrote:
>
>> On 6/26/24 01:23, Andreas Schwab wrote:
>> > On Jun 25 2024, Richard Henderson wrote:
>> >
>> >> can always force the use of a non-zero base with -B or -R.
>> >
>> >
On 6/27/24 9:10 AM, Philippe Mathieu-Daudé wrote:
Recent SDHCI expect cards to support the v3.01 spec
to negociate lower I/O voltage. Select it by default.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/sd/sd.c | 2 +-
1 file changed, 1
On Thu, 27 Jun 2024 00:32, Paolo Bonzini wrote:
On Tue, Jun 25, 2024 at 9:17 PM Manos Pitsidianakis
wrote:
>Move the macro to compiler.h and, while at it, move it under #ifndef
>__cplusplus to emphasize that it uses C-only constructs. A C++ version
>of typeof_strip_qual() using type traits is
On Wed, Jun 26, 2024 at 3:45 PM Michael S. Tsirkin wrote:
>
> On Wed, Jun 26, 2024 at 10:44:31AM +0800, Cindy Lu wrote:
> > The crash was reported in MAC OS and NixOS, here is the link for this bug
> > https://gitlab.com/qemu-project/qemu/-/issues/2334
> > https://gitlab.com/qemu-project/qemu/-/is
On Thu, Jun 27, 2024 at 10:38 AM Manos Pitsidianakis
wrote:
>
> On Thu, 27 Jun 2024 00:32, Paolo Bonzini wrote:
> >On Tue, Jun 25, 2024 at 9:17 PM Manos Pitsidianakis
> > wrote:
> >> >Move the macro to compiler.h and, while at it, move it under #ifndef
> >> >__cplusplus to emphasize that it uses
On Thu, 27 Jun 2024 11:48, Paolo Bonzini wrote:
because if anyone ended up using [..] C++ [..] the error message would
be very very long.
I thought that comes with the territory 😀
On Thu, Jun 27, 2024 at 04:40:33PM +0800, Cindy Lu wrote:
> On Wed, Jun 26, 2024 at 3:45 PM Michael S. Tsirkin wrote:
> >
> > On Wed, Jun 26, 2024 at 10:44:31AM +0800, Cindy Lu wrote:
> > > The crash was reported in MAC OS and NixOS, here is the link for this bug
> > > https://gitlab.com/qemu-proj
On Thu, Jun 27, 2024 at 4:55 PM Michael S. Tsirkin wrote:
>
> On Thu, Jun 27, 2024 at 04:40:33PM +0800, Cindy Lu wrote:
> > On Wed, Jun 26, 2024 at 3:45 PM Michael S. Tsirkin wrote:
> > >
> > > On Wed, Jun 26, 2024 at 10:44:31AM +0800, Cindy Lu wrote:
> > > > The crash was reported in MAC OS and
Hi Zhenzhong,
On 6/27/24 05:06, Duan, Zhenzhong wrote:
> Hi Eric,
>
>> -Original Message-
>> From: Eric Auger
>> Subject: [PATCH 4/7] HostIOMMUDevice: Introduce get_page_size_mask()
>> callback
>>
>> This callback will be used to retrieve the page size mask supported
>> along a given Host
On Fri, Jun 21, 2024 at 03:29:06PM GMT, Roy Hopkins wrote:
Adds an IGVM loader to QEMU which processes a given IGVM file and
applies the directives within the file to the current guest
configuration.
The IGVM loader can be used to configure both confidential and
non-confidential guests. For conf
Reviewed-by: Alwalid Salama
On 6/20/2024 5:22 PM, Alex Bennée wrote:
Expose the ability to control time through the plugin API. Only one
plugin can control time so it has to request control when loaded.
There are probably more corner cases to catch here.
Signed-off-by: Pierrick Bouvier
[AJB:
Reviewed-by: Alwalid Salama
On 6/20/2024 5:22 PM, Alex Bennée wrote:
From: Pierrick Bouvier
This plugin uses the new time control interface to make decisions
about the state of time during the emulation. The algorithm is
currently very simple. The user specifies an ips rate which applies
per
Reviewed-by: Alwalid Salama
On 6/20/2024 5:22 PM, Alex Bennée wrote:
If the plugin in controlling time there is some state that might be
missing from the plugin tracking it. Migration is unlikely to work in
this case so lets put a migration blocker in to let the user know if
they try.
Signed-o
Reviewed-by: Alwalid Salama
On 6/20/2024 5:22 PM, Alex Bennée wrote:
From: Pierrick Bouvier
These are not booleans, but masks.
Issue found by Richard Henderson.
Fixes: f86fd4d8721 ("plugins: distinct types for callbacks")
Signed-off-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
Mes
Reviewed-by: Alwalid Salama
On 6/20/2024 5:22 PM, Alex Bennée wrote:
From: Max Chou
If there are not any QEMU plugin memory callback functions, checking
before calling the qemu_plugin_vcpu_mem_cb function can reduce the
function call overhead.
Signed-off-by: Max Chou
Reviewed-by: Richard He
On Thu, Jun 27, 2024 at 11:06:50AM +0200, Stefano Garzarella wrote:
> On Fri, Jun 21, 2024 at 03:29:06PM GMT, Roy Hopkins wrote:
> > Adds an IGVM loader to QEMU which processes a given IGVM file and
> > applies the directives within the file to the current guest
> > configuration.
> >
> > The IGVM
On 26.06.2024 18:23, Peter Xu wrote:
On Wed, Jun 26, 2024 at 05:47:34PM +0200, Maciej S. Szmigiero wrote:
On 26.06.2024 03:51, Peter Xu wrote:
On Wed, Jun 26, 2024 at 12:44:29AM +0200, Maciej S. Szmigiero wrote:
On 25.06.2024 19:25, Peter Xu wrote:
On Mon, Jun 24, 2024 at 09:51:18PM +0200, Ma
On Wed, Jun 26, 2024 at 11:23 PM Alvin Chang via wrote:
>
> According to RISC-V Debug specification ratified version 0.13 [1]
> (also applied to version 1.0 [2] but it has not been ratified yet), the
> enabled privilege levels of the trigger is common match conditions for
> all the types of the tr
From: thomas
Patch 06b12970174 ("virtio-net: fix network stall under load")
added double-check to test whether the available buffer size
can satisfy the request or not, in case the guest has added
some buffers to the avail ring simultaneously after the first
check. It will be lucky if the availab
v-to-apply-20240627-1
for you to fetch changes up to 2f5a2315b84a9b1f089ecfc3f31b29813609a7b7:
target/riscv: Apply modularized matching conditions for icount trigger
(2024-06-27 13:09:16 +1000)
RISC-V PR for 9.1
* Extend virtua
From: "Fea.Wang"
Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH
and HEDELEGH for exception codes 32-47 for reserving and exception codes
48-63 for custom use. Add the CSR number though the implementation is
just reading zero and writing ignore. Besides, for accessing HEDELEGH
From: "Fea.Wang"
Based on the priv-1.13.0, add the exception codes for Software-check and
Hardware-error.
Signed-off-by: Fea.Wang
Reviewed-by: Frank Chang
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Message-ID: <20240606135454.119186-6-fea.w...@sifive.com>
Signed-off-by: Alistair F
From: Chao Du
If the breakpoint belongs to the userspace then set the ret value.
Signed-off-by: Chao Du
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Message-ID: <20240606014501.20763-3-duc...@eswincomputing.com>
Signed-off-by: Alistair Francis
--
From: Jim Shu
Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c
could also use it.
Signed-off-by: Jim Shu
Signed-off-by: Fea.Wang
Reviewed-by: Frank Chang
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Message-ID: <20240606135454.119186-2-fea.w...@sifive.com>
Si
From: Daniel Henrique Barboza
The DT docs for riscv,imsics [1] predicts a 'qemu,imsics' enum in the
'compatible' property.
[1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
Reported-by: Conor Dooley
Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support
From: Daniel Henrique Barboza
The DT docs for riscv,aplic [1] predicts a 'riscv,delegation' property.
Not 'riscv,delegate'.
[1] Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
Reported-by: Conor Dooley
Fixes: e6faee65855b ("hw/riscv: virt: Add optional AIA APLIC support
From: Frank Chang
Add multi extension implied rules to enable the implied extensions of
the multi extension recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Acked-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20240625114629.2
From: "Fea.Wang"
Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in
mstateen0 that controls access to the hedeleg.
Signed-off-by: Fea.Wang
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Message-ID: <20240606135454.119186-4-fea.w...@sifive.com>
From: Alvin Chang
We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level. We
can invoke trigger_common_match() to check the privilege levels of the
type 3 triggers.
Signed-off-by: Alvin Chang
Acked-by: Alistair
From: Branislav Brzak
helper_froundnx_h function mistakenly uses single percision nanbox
check instead of the half percision one. This patch fixes the issue.
Signed-off-by: Branislav Brzak
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-ID: <20240608214546.226963-1-brzakb
From: Clément Léger
When icount is enabled, rather than returning the virtual CPU time, we
should return the instruction count itself. Add an instructions bool
parameter to get_ticks() to correctly return icount_get_raw() when
icount_enabled() == 1 and instruction count is queried. This will modi
From: Alvin Chang
According to RISC-V Debug specification version 0.13 [1] (also applied
to version 1.0 [2] but it has not been ratified yet), there are several
common matching conditions before firing a trigger, including the
enabled privilege levels of the trigger.
This commit adds trigger_com
From: Daniel Henrique Barboza
We'll change the aplic DT nodename in the next patch and the name is
hardcoded in 2 different functions. Create a helper to change a single
place later.
While we're at it, in create_fdt_socket_aplic(), move 'aplic_name'
inside the conditional to avoid allocating a s
From: Rajnesh Kanwal
AIA extends the width of all IRQ CSRs to 64bit even
in 32bit systems by adding missing half CSRs.
This seems to be missed while adding support for
virtual IRQs. The whole logic seems to be correct
except the width of the masks.
Fixes: 1697837ed9 ("target/riscv: Add M-mode v
From: "Fea.Wang"
Add macros and variables for RISC-V privilege 1.13 support.
Signed-off-by: Fea.Wang
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Message-ID: <20240606135454.119186-3-fea.w...@sifive.com>
Signed-off-by: Alistair Franci
From: Daniel Henrique Barboza
We need #address-cells properties in all interrupt controllers that are
referred by an interrupt-map [1]. For the RISC-V machine, both PLIC and
APLIC controllers must have this property.
PLIC already sets it in create_fdt_socket_plic(). Set the property for
APLIC in
From: Frank Chang
Add MISA extension implied rules to enable the implied extensions
of MISA recursively.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20240625114629.27793-4-frank.
From: Daniel Henrique Barboza
The Linux DT docs for imsic [1] predicts an 'interrupt-controller@addr'
node, not 'imsic@addr', given this node inherits the
'interrupt-controller' node.
[1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
Reported-by: Conor Dooley
Fixes:
From: Sunil V L
RISC-V virt is currently missing default type for block devices. Without
this being set, proper backend is not created when option like -cdrom
is used. So, make the virt board's default block device type be
IF_VIRTIO similar to other architectures.
We also need to set no_cdrom to
From: Frank Chang
Remove the old-fashioned extension auto-update check statements as
they are replaced by the extension implied rules.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20240625114629.27793-7-frank.c
From: "Fea.Wang"
Add RISC-V privilege 1.13 support.
Signed-off-by: Fea.Wang
Signed-off-by: Fea.Wang
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20240606135454.119186-7-fea.w...@sifive.com>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c
From: Frank Chang
RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offset of the extension defined in RISCVCP
From: Frank Chang
Zc extension has special implied rules that need to be handled separately.
Signed-off-by: Frank Chang
Reviewed-by: Jerry Zhang Jian
Tested-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20240625114629.27793-6-frank.ch...@sifive.com>
Signed-off-by: Alistair F
From: Chao Du
This patch implements insert/remove software breakpoint process.
For RISC-V, GDB treats single-step similarly to breakpoint: add a
breakpoint at the next step address, then continue. So this also
works for single-step debugging.
Implement kvm_arch_update_guest_debug(): Set the con
From: Daniel Henrique Barboza
The DT docs for riscv,aplic [1] predicts a 'qemu,aplic' enum in the
'compatible' property.
[1] Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
Reported-by: Conor Dooley
Fixes: e6faee65855b ("hw/riscv: virt: Add optional AIA APLIC support to
From: Jerry Zhang Jian
According to RISC-V crypto spec, Zvkb extension is a
subset of the Zvbb extension [1].
1:
https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10
Signed-off-by: Jerry Zhang Jian
Reviewed-by
From: Daniel Henrique Barboza
The DT docs for riscv,imsics [1] requires a 'msi-cell' property. Add one
and set it zero.
[1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
Reported-by: Conor Dooley
Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to
From: Daniel Henrique Barboza
The correct name of the aplic controller node, as per Linux kernel DT
docs [1], is 'interrupt-controller@addr'.
[1] Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
Reported-by: Conor Dooley
Fixes: e6faee65855b ("hw/riscv: virt: Add optional
From: Alvin Chang
We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level.
Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke
trigger_common_match() to check the privilege levels of the type
From: Chao Du
To enable the KVM GUEST DEBUG for RISC-V at QEMU side.
Signed-off-by: Chao Du
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
Acked-by: Alistair Francis
Message-ID: <20240606014501.20763-4-duc...@eswincomputing.com>
Signed-off-by: Alistair Francis
---
configs/t
From: Frank Chang
Introduce helpers to enable the extensions based on the implied rules.
The implied extensions are enabled recursively, so we don't have to
expand all of them manually. This also eliminates the old-fashioned
ordering requirement. For example, Zvksg implies Zvks, Zvks implies
Zvks
From: Rajnesh Kanwal
Qemu maps IRQs 0:15 for core interrupts and 16 onward for
guest interrupts which are later translated to hgiep in
`riscv_cpu_set_irq()` function.
With virtual IRQ support added, software now can fully
use the whole local interrupt range without any actual
hardware attached.
John Snow writes:
> This function has been unused since fd62bff901b.
>
> Signed-off-by: John Snow
Reviewed-by: Markus Armbruster
I assume you won't mind me adding a bit of polish: "since commit
fd62bff901b (sphinx/qapidoc: Drop code to generate doc for simple union
tag)".
John Snow writes:
> Change get_doc_indented() to preserve indentation on all subsequent text
> lines, and create a compatibility dedent() function for qapidoc.py that
> removes indentation the same way get_doc_indented() did.
>
> This is being done for the benefit of a new qapidoc generator which
Accidental duplicate, please ignore.
Accidental duplicate, please ignore.
John Snow writes:
> This function has been unused since fd62bff901b.
>
> Signed-off-by: John Snow
Reviewed-by: Markus Armbruster
I assume you won't mind me adding a bit of polish: "since commit
fd62bff901b (sphinx/qapidoc: Drop code to generate doc for simple union
tag)".
John Snow writes:
> Change get_doc_indented() to preserve indentation on all subsequent text
> lines, and create a compatibility dedent() function for qapidoc.py that
> removes indentation the same way get_doc_indented() did.
>
> This is being done for the benefit of a new qapidoc generator which
John Snow writes:
> The double-colon synax is rST formatting that precedes a literal code
> block. We do not want to capture these as QAPI-specific sections.
>
> Coerce blocks that start with e.g. "Example::" to be parsed as untagged
> paragraphs instead of special tagged sections.
>
> Signed-off
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 16
1 file changed, 16 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 257110ac703..aeb7bc4d51b 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@
Philippe Mathieu-Daudé writes:
> On 27/6/24 06:13, Gustavo Romero wrote:
>> Make the gdb_first_attached_cpu and gdb_hextomem non-internal so they
>> are not confined to use only in gdbstub.c.
>> Signed-off-by: Gustavo Romero
>> Reviewed-by: Richard Henderson
>> ---
>> gdbstub/internals.h
On 20/6/24 17:22, Alex Bennée wrote:
Move the key functionality of moving time forward into the clock
sub-system itself. This will allow us to plumb in time control into
plugins.
Signed-off-by: Pierrick Bouvier
Signed-off-by: Alex Bennée
Message-Id: <20240530220610.1245424-4-pierrick.bouv...@l
Remove dpy_cursor_define_supported() as it brings no benefit today and
it has a few inherent problems.
All graphical displays except egl-headless support cursor composition
without DMA-BUF, and egl-headless is meant to be used in conjunction
with another graphical display, so dpy_cursor_define_sup
CGImageCreate | Apple Developer Documentation
https://developer.apple.com/documentation/coregraphics/1455149-cgimagecreate
> The color space is retained; on return, you may safely release it.
Signed-off-by: Akihiko Odaki
---
ui/cocoa.m | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
d
Add accelerated cursor composition to ui/cocoa. This does not only
improve performance for display devices that exposes the capability to
the guest according to dpy_cursor_define_supported(), but fixes the
cursor display for devices that unconditionally expects the availability
of the capability (e
Signed-off-by: Akihiko Odaki
---
include/ui/console.h| 4 ++--
hw/display/ati.c| 2 +-
hw/display/virtio-gpu.c | 3 +--
hw/display/vmware_vga.c | 2 +-
ui/console.c| 5 +++--
ui/dbus-listener.c | 2 +-
ui/gtk.c| 2 +-
ui/sdl2.c |
Add accelerated cursor composition to ui/cocoa. This does not only
improve performance for display devices that exposes the capability to
the guest according to dpy_cursor_define_supported(), but fixes the
cursor display for devices that unconditionally expects the availability
of the capability (e
>-Original Message-
>From: Eric Auger
>Subject: Re: [PATCH 4/7] HostIOMMUDevice: Introduce
>get_page_size_mask() callback
>
>Hi Zhenzhong,
>
>On 6/27/24 05:06, Duan, Zhenzhong wrote:
>> Hi Eric,
>>
>>> -Original Message-
>>> From: Eric Auger
>>> Subject: [PATCH 4/7] HostIOMMUDev
Hi Eric,
>-Original Message-
>From: Eric Auger
>Subject: [PATCH 5/7] virtio-iommu : Retrieve page size mask on
>virtio_iommu_set_iommu_device()
>
>Retrieve the Host IOMMU Device page size mask when this latter is set.
>This allows to get the information much sooner than when relying on
>I
On Thu, Jun 27, 2024 at 12:59:19PM +0200, Paolo Bonzini wrote:
> Date: Thu, 27 Jun 2024 12:59:19 +0200
> From: Paolo Bonzini
> Subject: [PATCH] target/i386/tcg: remove unused enum
> X-Mailer: git-send-email 2.45.2
>
> Signed-off-by: Paolo Bonzini
> ---
> target/i386/tcg/translate.c | 16 ---
Hi Paolo,
A gentle poke for this series.
Thanks,
Zhao
On Thu, Jun 06, 2024 at 05:25:31PM +0800, Zhao Liu wrote:
> Date: Thu, 6 Jun 2024 17:25:31 +0800
> From: Zhao Liu
> Subject: Re: [PATCH v2 0/6] target/i386: Misc cleanup on KVM PV defs and
> outdated comments
>
> Hi Paolo,
>
> Just a ping
Am 26.06.2024 um 18:27 hat Nir Soffer geschrieben:
> On Wed, Jun 26, 2024 at 12:17 PM Daniel P. Berrangé
> wrote:
>
> > On Mon, Jun 24, 2024 at 06:08:26PM +0200, Kevin Wolf wrote:
> > > Am 24.06.2024 um 17:23 hat Stefan Hajnoczi geschrieben:
> > > > On Wed, Jun 19, 2024 at 08:43:25PM +0300, Nir S
Hi Julien,
On Fri, May 24, 2024 at 06:22:12PM +0100, Julien Grall wrote:
> Hi Mostafa,
>
> On 29/04/2024 04:24, Mostafa Saleh wrote:
> > Use the new SMMU property to make the SMMU OAS match the CPU PARANGE.
> > That's according to SMMU manual ARM IHI 0070F.b: > 6.3.6 SMMU_IDR5,
> > OAS must
Hi,
Thanks for fixing my patch and adding this follow-up.
I incorporated your fix with some change with v2 so please review it and
rebase this patch to it.
On 2024/06/25 22:49, Phil Dennis-Jordan wrote:
When pointer input is absolute, use the native macOS host’s Cocoa
NSCursor to render the
Hi Eric,
On Tue, May 21, 2024 at 11:32:48AM +0200, Eric Auger wrote:
> Hi Mostafa,
>
> On 4/29/24 05:24, Mostafa Saleh wrote:
> > Add property that sets the OAS of the SMMU, this in not used in this
> > patch.
> >
> > Signed-off-by: Mostafa Saleh
> > ---
> > hw/arm/smmuv3-internal.h | 3 ++-
>
在 2024/6/27 下午2:38, Philippe Mathieu-Daudé 写道:
On 27/6/24 06:13, Jiaxun Yang wrote:
Signed-off-by: Jiaxun Yang
---
Jiaxun Yang (2):
hw/intc/loongson_ipi: Gate MMIO regions creation with property
MAINTAINERS: Add myself as a reviewer of LoongArch virt machine
Maybe s/has-mmio/
On Tue, 25 Jun 2024 20:38:39 +0530
Sunil V L wrote:
> As per the step 5 in the process documented in bios-tables-test.c,
> generate the expected ACPI AML data files for RISC-V using the
> rebuild-expected-aml.sh script and update the
> bios-tables-test-allowed-diff.h.
>
> These are all new files
On 27/6/24 13:05, Alex Bennée wrote:
Philippe Mathieu-Daudé writes:
On 27/6/24 06:13, Gustavo Romero wrote:
Make the gdb_first_attached_cpu and gdb_hextomem non-internal so they
are not confined to use only in gdbstub.c.
Signed-off-by: Gustavo Romero
Reviewed-by: Richard Henderson
---
gd
Restore 'loongarch_ipi.c' for LoongArch.
This reverts commit 5f82fb2a3a71bb510b3e1b7229929d468c01740a.
---
hw/intc/loongarch_ipi.c | 347
1 file changed, 347 insertions(+)
create mode 100644 hw/intc/loongarch_ipi.c
diff --git a/hw/intc/loongarch_ipi.c b/
Currently LoongArch and MIPS architectures share loongson_ipi,
and modifications to loongson_ipi by the MIPS architecture may
lead to some unknown problems in the LoongArch architecture.
In order to minimize the impact of this inter-architectural
interaction, we believe that it is necessary to rest
Currently LoongArch and MIPS architectures share loongson_ipi,
and modifications to loongson_ipi by the MIPS architecture may
lead to some unknown problems in the LoongArch architecture.
In order to minimize the impact of this inter-architectural
interaction, we believe that it is necessary to rest
On Fri, Jun 21, 2024 at 03:29:08PM GMT, Roy Hopkins wrote:
When using an IGVM file the configuration of the system firmware is
defined by IGVM directives contained in the file. In this case the user
should not configure any pflash devices.
This commit skips initialization of the ROM mode when pf
On Thu, 20 Jun 2024 17:03:11 +0100
Jonathan Cameron wrote:
> Rather than attempting to create a generic function with mess of the two
> different device handle types, use a PCI handle specific variant. If the
> ACPI handle form is needed then that can be introduced alongside this
> with little d
On Thu, 20 Jun 2024 17:03:10 +0100
Jonathan Cameron wrote:
> Before making additional modification, tidy up this misleading indentation.
>
> Reviewed-by: Ankit Agrawal
> Signed-off-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
> ---
> v3: Unchanged
> ---
> hw/acpi/acpi_generic_initiator.
On Thu, Jun 27, 2024 at 02:42:44PM +0200, Igor Mammedov wrote:
> On Thu, 20 Jun 2024 17:03:11 +0100
> Jonathan Cameron wrote:
>
> > Rather than attempting to create a generic function with mess of the two
> > different device handle types, use a PCI handle specific variant. If the
> > ACPI handl
On Thu, 20 Jun 2024 17:03:09 +0100
Jonathan Cameron wrote:
> The ordering in ACPI specification [1] has bus number in the lowest byte.
> As ACPI tables are little endian this is the reverse of the ordering
> used by PCI_BUILD_BDF(). As a minimal fix split the QEMU BDF up
> into bus and devfn and
On Thu, 27 Jun 2024 08:44:14 -0400
"Michael S. Tsirkin" wrote:
> On Thu, Jun 27, 2024 at 02:42:44PM +0200, Igor Mammedov wrote:
> > On Thu, 20 Jun 2024 17:03:11 +0100
> > Jonathan Cameron wrote:
> >
> > > Rather than attempting to create a generic function with mess of the two
> > > different
On Fri, Jun 21, 2024 at 03:29:09PM GMT, Roy Hopkins wrote:
The class function and implementations for updating launch data return
a code in case of error. In some cases an error message is generated and
in other cases, just the error return value is used.
This small refactor adds an 'Error **err
On Thu, 20 Jun 2024 17:03:17 +0100
Jonathan Cameron wrote:
> The test to be added exercises many corners of the SRAT and HMAT table
did you mean 'corner cases"?
> generation.
>
> Signed-off-by: Jonathan Cameron
> ---
> v3: No change
> ---
> tests/qtes
On Fri, Jun 21, 2024 at 03:29:13PM GMT, Roy Hopkins wrote:
Create an enum entry within FirmwareDevice for 'igvm' to describe that
an IGVM file can be used to map firmware into memory as an alternative
to pre-existing firmware devices.
Signed-off-by: Roy Hopkins
---
docs/interop/firmware.json |
On 27/6/24 14:13, gaosong wrote:
在 2024/6/27 下午2:38, Philippe Mathieu-Daudé 写道:
On 27/6/24 06:13, Jiaxun Yang wrote:
Signed-off-by: Jiaxun Yang
---
Jiaxun Yang (2):
hw/intc/loongson_ipi: Gate MMIO regions creation with property
MAINTAINERS: Add myself as a reviewer of LoongArch
1 - 100 of 335 matches
Mail list logo
