Re: [PATCH 3/3] tests/tcg/s390x: Test VSTRS

On 8/5/23 01:03, Ilya Leoshkevich wrote: > Add a small test to prevent regressions. > > Signed-off-by: Ilya Leoshkevich > --- > tests/tcg/s390x/Makefile.target | 1 + > tests/tcg/s390x/vxeh2_vstrs.c | 88 + > 2 files changed, 89 insertions(+) > create mode 100

Re: [PATCH 4/7] spapr: Fix record-replay machine reset consuming too many events

On Fri Aug 4, 2023 at 6:50 PM AEST, Pavel Dovgalyuk wrote: > BTW, there is a function qemu_register_reset_nosnapshotload that can be > used in similar cases. > Can you just use it without changing the code of the reset handler? I didn't know that, thanks for pointing it out. I'll take a closer lo

Re: [PATCH for-8.2 0/7] tcg/ppc: Support power10 prefixed instructions

On Sat Aug 5, 2023 at 7:33 AM AEST, Richard Henderson wrote: > Emit one 64-bit instruction for large constants and pc-relatives. > With pc-relative addressing, we don't need REG_TB, which means we > can re-enable direct branching for goto_tb. Very cool. I tested this on a POWER10 and it has been s

Re: [PATCH 6/7] tcg/ppc: Disable USE_REG_TB for Power v3.1

Patch 7 is not reqired for this? Thanks, Nick On Sat Aug 5, 2023 at 7:33 AM AEST, Richard Henderson wrote: > With Power v3.1, we have pc-relative addressing and so > do not require a register holding the current TB. > > Signed-off-by: Richard Henderson > --- > tcg/ppc/tcg-target.c.inc | 2 +- >

[PATCH 11/23] target/s390x: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/s390x/cpu.h | 10 +- 1 file changed, 5 insertions(+), 5 deletion

[PATCH 06/23] target/hexagon: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/hexagon/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) dif

[PATCH 19/23] target/ppc: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/ppc/cpu.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) di

[PATCH 10/23] target/riscv: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/riscv/cpu.h| 4 ++-- target/riscv/cpu_helper.c | 2 +- 2 files c

[PATCH 08/23] target/mips: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/mips/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

[PATCH 16/23] target/m68k: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/m68k/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

[PATCH 01/23] cpu-defs.h; Add MMU_INDEX() helper

Add a MMU_INDEX() helper to specify which MMU entry to use. Currently this is just an 1:1 mapper, but in a follow-up patch it will enable us to generate smaller (and maybe faster) tcg code. Signed-off-by: Helge Deller --- include/exec/cpu-defs.h | 5 + 1 file changed, 5 insertions(+) diff

[PATCH 04/23] target/alpha: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/alpha/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

[PATCH 02/23] target/i386: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/i386/cpu.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions

[PATCH 15/23] target/cris: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/cris/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) di

[PATCH 17/23] target/microblaze: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/microblaze/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletion

[PATCH 13/23] target/xtensa: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/xtensa/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

[PATCH 03/23] target/hppa: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/hppa/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

[PATCH 00/23] Introduce MMU_INDEX()

This patchset introduces the new helper macro MMU_INDEX(). whill will (after applying the last patch) allow to generate smaller code by the tcg. Patch #1 adds the MMU_INDEX() helper macro, which simply wraps the given value. Patches #2-#23 are trivial patches which convert each target to use the

[PATCH 12/23] target/sparc: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/sparc/cpu.h | 20 ++-- 1 file changed, 10 insertions(+),

[PATCH 18/23] target/m68k: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/nios2/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) d

[PATCH 09/23] target/openrisc: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/openrisc/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(

[PATCH 05/23] target/avr: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/avr/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) dif

[PATCH 14/23] target/arm: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) dif

[PATCH 07/23] target/loongarch: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/loongarch/cpu.h | 8 1 file changed, 4 insertions(+), 4 deletio

[PATCH v2 14/23] target/arm: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) dif

[PATCH v2 07/23] target/loongarch: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/loongarch/cpu.h | 8 1 file changed, 4 insertions(+), 4 deletio

[PATCH v2 09/23] target/openrisc: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/openrisc/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(

[PATCH v2 13/23] target/xtensa: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/xtensa/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

[PATCH v2 18/23] target/m68k: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/nios2/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) d

[PATCH v2 17/23] target/microblaze: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/microblaze/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletion

[PATCH v2 04/23] target/alpha: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/alpha/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

[PATCH v2 21/23] target/sh4: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/sh4/cpu.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-)

[PATCH v2 03/23] target/hppa: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/hppa/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

[PATCH v2 19/23] target/ppc: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/ppc/cpu.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) di

[PATCH v2 06/23] target/hexagon: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/hexagon/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) dif

[PATCH v2 10/23] target/riscv: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/riscv/cpu.h| 4 ++-- target/riscv/cpu_helper.c | 2 +- 2 files c

[PATCH v2 00/23] Introduce MMU_INDEX()

This is v2 of the patchset. It is *identical* to v1, but v1 missed patches #20-24 since I hit a mail batch limit with my email provider. This patchset introduces the new helper macro MMU_INDEX(). whill will (after applying the last patch) allow to generate smaller code by the tcg. Patch #1 adds

[PATCH v2 02/23] target/i386: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/i386/cpu.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions

[PATCH v2 16/23] target/m68k: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/m68k/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

[PATCH v2 08/23] target/mips: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/mips/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)

[PATCH v2 01/23] cpu-defs.h; Add MMU_INDEX() helper

Add a MMU_INDEX() helper to specify which MMU entry to use. Currently this is just an 1:1 mapper, but in a follow-up patch it will enable us to generate smaller (and maybe faster) tcg code. Signed-off-by: Helge Deller --- include/exec/cpu-defs.h | 5 + 1 file changed, 5 insertions(+) diff

[PATCH v2 20/23] target/rx: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/rx/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --g

[PATCH v2 12/23] target/sparc: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/sparc/cpu.h | 20 ++-- 1 file changed, 10 insertions(+),

[PATCH v2 11/23] target/s390x: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/s390x/cpu.h | 10 +- 1 file changed, 5 insertions(+), 5 deletion

[PATCH v2 05/23] target/avr: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/avr/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) dif

[PATCH v2 15/23] target/cris: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/cris/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) di

[PATCH v2 23/23] cpu-defs.h: Reduce generated code size by inverting MMU_INDEX()

The MMU is placed within CPUNegativeOffsetState, which means the smallest negative offsets are at the end of the struct (see comment for struct CPUTLB). But in target/cpu.h usually MMU indexes in the range 0-8 are used, which means that the negative offsets are bigger than if MMU indexes 9-15 woul

[PATCH v2 22/23] target/tricore: Use MMU_INDEX() helper

Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/tricore/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

Re: [PATCH 2/3] target/s390x: Fix the "ignored match" case in VSTRS

On 8/5/23 01:03, Ilya Leoshkevich wrote: > Currently the emulation of VSTRS recognizes partial matches in presence > of \0 in the haystack, which, according to PoP, is not correct: > > If the ZS flag is one and a zero byte was detected > in the second operand, then there can not be a >

Re: [PATCH 7/7] tcg/ppc: Use prefixed instructions for tcg_out_goto_tb

On Sat Aug 5, 2023 at 7:33 AM AEST, Richard Henderson wrote: > When a direct branch is out of range, we can load the destination for > the indirect branch using PLA (for 16GB worth of buffer) and PLD from > the TranslationBlock for everything larger. > > This means the patch affects exactly one ins

Re: [PATCH 6/7] tcg/ppc: Disable USE_REG_TB for Power v3.1

On 8/6/23 04:58, Nicholas Piggin wrote: Patch 7 is not reqired for this? No, USE_REG_TB has never been *required*. The fallback path through tcg_out_movi will generate the 5 insn sequence for a full 64-bit constant load. Mitigating that here is that patch 1 will emit PADDI for most of those

Re: [PATCH 7/7] tcg/ppc: Use prefixed instructions for tcg_out_goto_tb

On 8/6/23 05:55, Nicholas Piggin wrote: On Sat Aug 5, 2023 at 7:33 AM AEST, Richard Henderson wrote: When a direct branch is out of range, we can load the destination for the indirect branch using PLA (for 16GB worth of buffer) and PLD from the TranslationBlock for everything larger. This means

[PATCH 3/3] target/loongarch: Mark CSR.PWCH as LoongArch64-only

LoongArch32 does not provide CSR.PWCH, thus the CSR is marked as LoongArch64-only. Signed-off-by: Jiajie Chen --- target/loongarch/insn_trans/trans_privileged.c.inc | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/ta

[PATCH 2/3] target/loongarch: Support LoongArch32 TLB entry

The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen --- target/loongarch/cpu-csr.h| 9 + target/loongarch/tlb_helper.c | 17 - 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/target/loo

[PATCH 1/3] target/loongarch: Introduce loongarch32-softmmu target

This commit introduces new loongarch32-softmmu target. Compared to loongarch64-softmmu, the new target is different at least in: - GPRs and CSRs are 32-bits wide, but FPRs are still 64-bits wide - LA32 lacks some 64-bit-only instructions - CSR.DMW0-3 introduces PSEG More differences are to be han

Re: [PATCH for-8.2 0/7] tcg/ppc: Support power10 prefixed instructions

On 8/6/23 04:55, Nicholas Piggin wrote: On Sat Aug 5, 2023 at 7:33 AM AEST, Richard Henderson wrote: Emit one 64-bit instruction for large constants and pc-relatives. With pc-relative addressing, we don't need REG_TB, which means we can re-enable direct branching for goto_tb. Very cool. I test

Re: [PATCH v2 10/23] target/riscv: Use MMU_INDEX() helper

On 8/6/23 05:17, Helge Deller wrote: Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/riscv/cpu.h| 4 ++-- ta

Re: [PATCH v2 14/23] target/arm: Use MMU_INDEX() helper

On 8/6/23 05:17, Helge Deller wrote: Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used. Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --- target/arm/cpu.h | 4 ++-- 1 file chan

Re: [PATCH 1/3] target/loongarch: Introduce loongarch32-softmmu target

On 8/6/23 07:13, Jiajie Chen wrote: This commit introduces new loongarch32-softmmu target. Compared to loongarch64-softmmu, the new target is different at least in: - GPRs and CSRs are 32-bits wide, but FPRs are still 64-bits wide - LA32 lacks some 64-bit-only instructions - CSR.DMW0-3 introduce

Re: [PATCH v2 10/23] target/riscv: Use MMU_INDEX() helper

On 8/6/23 16:30, Richard Henderson wrote: On 8/6/23 05:17, Helge Deller wrote: Use the new MMU_INDEX() helper to specify the index of the CPUTLB which should be used.  Additionally, in a follow-up patch this helper allows then to optimize the tcg code generation. Signed-off-by: Helge Deller --

Re: [PATCH for-8.2 v2 1/2] qapi/migration: Deduplicate migration parameter field comments

On Sat, Aug 05, 2023 at 10:12:00AM +0200, Markus Armbruster wrote: > Peter Xu writes: > > > On Fri, Aug 04, 2023 at 05:48:49PM +0100, Daniel P. Berrangé wrote: > >> On Fri, Aug 04, 2023 at 12:46:18PM -0400, Peter Xu wrote: > >> > On Fri, Aug 04, 2023 at 05:29:19PM +0100, Daniel P. Berrangé wrote:

Re: [PULL 0/7] ppc queue

On 8/5/23 08:56, Michael Tokarev wrote: 04.08.2023 18:29, Daniel Henrique Barboza wrote: .. Nicholas Piggin (3):    target/ppc: Implement ASDR register for ISA v3.0 for HPT    target/ppc: Fix pending HDEC when entering PM state    target/ppc: Fix VRMA page size for ISA v3.0 Should

about QEMU TLS

Hi all, According to qemu docs [1], TLS parameters are specified as an object in the QEMU command line: -object tls-creds-x509,id=id,endpoint=endpoint,dir=/path/to/cred/dir ... of which "endpoint" is a type of "QCryptoTLSCredsEndpoint" and can be either a "server" or a "client". I'd like to

Re: [PULL 07/24] linux-user: Do not call get_errno() in do_brk()

On 8/5/23 23:53, Michael Tokarev wrote: 06.08.2023 06:36, Richard Henderson wrote: --- a/linux-user/syscall.c +++ b/linux-user/syscall.c -    mapped_addr = get_errno(target_mmap(brk_page, new_alloc_size, -    PROT_READ|PROT_WRITE, -

Re: [PULL 00/24] tcg + linux-user queue for 8.1-rc3

On 8/5/23 20:36, Richard Henderson wrote: The following changes since commit 6db03ccc7f4ca33c99debaac290066f4500a2dfb: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2023-08-04 14:47:00 -0700) are available in the Git repository at: https://gitlab.com/rth7680/

Re: [PATCH 7/7] tcg/ppc: Use prefixed instructions for tcg_out_goto_tb

On Mon Aug 7, 2023 at 12:13 AM AEST, Richard Henderson wrote: > On 8/6/23 05:55, Nicholas Piggin wrote: > > On Sat Aug 5, 2023 at 7:33 AM AEST, Richard Henderson wrote: > >> When a direct branch is out of range, we can load the destination for > >> the indirect branch using PLA (for 16GB worth of b

Re: [PATCH v3 01/17] i386: Fix comment style in topology.h

On 8/1/2023 6:35 PM, Zhao Liu wrote: From: Zhao Liu For function comments in this file, keep the comment style consistent with other places. Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daudé missing '>' at the end. Reviewed-by: Yanan Wang Acked-by: Michael S. Tsirkin Reviewed-by

Re: [PATCH 1/3] target/loongarch: Introduce loongarch32-softmmu target

Cc: Jun Yi 在 2023/8/6 下午10:13, Jiajie Chen 写道: This commit introduces new loongarch32-softmmu target. Compared to loongarch64-softmmu, the new target is different at least in: - GPRs and CSRs are 32-bits wide, but FPRs are still 64-bits wide - LA32 lacks some 64-bit-only instructions - CSR.DMW

Re: [PATCH 1/3] target/loongarch: Introduce loongarch32-softmmu target

在 2023/8/7 上午10:31, gaosong 写道: Cc: Jun Yi CC: shenjiny...@loongson.cn 在 2023/8/6 下午10:13, Jiajie Chen 写道: This commit introduces new loongarch32-softmmu target. Compared to loongarch64-softmmu, the new target is different at least in: - GPRs and CSRs are 32-bits wide, but FPRs are still 64

Re: [PATCH] print memory in MB units in initrd-too-large errmsg

On Sat, Aug 5, 2023 at 12:26 AM Markus Armbruster wrote: > > Jim Cromie writes: > > > Change 2 error messages to display sizes in MB, not bytes. > > > > qemu: initrd is too large, cannot support this. (max: 2047 MB, need 5833 MB) > > > > Also, distinguish 2 sites by adding "it" and "this" respect

[PATCH v2 5/5] target/loongarch: Support LoongArch32 DMW

LA32 uses a different encoding for CSR.DMW and a new direct mapping mechanism. Signed-off-by: Jiajie Chen --- target/loongarch/cpu-csr.h| 7 +++ target/loongarch/tlb_helper.c | 26 +++--- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/target/loongarc

[PATCH v2 1/5] target/loongarch: Add loongarch32 mode for loongarch64-softmmu

This commit adds loongarch32 mode to loongarch64-softmmu. Signed-off-by: Jiajie Chen --- target/loongarch/cpu.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index fa371ca8ba..43c73e6363 100644 --- a/target/loongarch/cpu.h +++ b/target

[PATCH v2 3/5] target/loongarch: Add GDB support for loongarch32 mode

GPRs and PC are 32-bit wide in loongarch32 mode. Signed-off-by: Jiajie Chen --- configs/targets/loongarch64-softmmu.mak | 2 +- gdb-xml/loongarch-base32.xml| 45 + target/loongarch/cpu.c | 10 +- target/loongarch/gdbstub.c |

[PATCH v2 2/5] target/loongarch: Add loongarch32 cpu la132

Add la132 as a loongarch32 cpu type and allow virt machine to be used with la132 instead of la464. Signed-off-by: Jiajie Chen --- hw/loongarch/virt.c| 5 - target/loongarch/cpu.c | 41 + target/loongarch/cpu.h | 11 +++ 3 files changed, 52

[PATCH v2 4/5] target/loongarch: Support LoongArch32 TLB entry

The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen --- target/loongarch/cpu-csr.h| 9 + target/loongarch/tlb_helper.c | 17 - 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/target/loo

Re: [PATCH 3/7] tcg/ppc: Use prefixed instructions in tcg_out_mem_long

On Sat, Aug 5, 2023 at 7:33 AM Richard Henderson wrote: > > When the offset is out of range of the non-prefixed insn, but > fits the 34-bit immediate of the prefixed insn, use that. > > Signed-off-by: Richard Henderson > --- > tcg/ppc/tcg-target.c.inc | 66 +++

Re: [PATCH 2/7] tcg/ppc: Use PADDI in tcg_out_movi

On Sat, Aug 5, 2023 at 7:33 AM Richard Henderson wrote: > > PADDI can load 34-bit immediates and 34-bit pc-relative addresses. > > Signed-off-by: Richard Henderson > --- > tcg/ppc/tcg-target.c.inc | 47 > 1 file changed, 47 insertions(+) > > diff --git a/

Re: [PATCH 7/7] tcg/ppc: Use prefixed instructions for tcg_out_goto_tb

On Sat, Aug 5, 2023 at 7:34 AM Richard Henderson wrote: > > When a direct branch is out of range, we can load the destination for > the indirect branch using PLA (for 16GB worth of buffer) and PLD from > the TranslationBlock for everything larger. > > This means the patch affects exactly one instr

Re: [PATCH v2 4/5] target/loongarch: Support LoongArch32 TLB entry

On 2023/8/7 11:18, Jiajie Chen wrote: The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen --- target/loongarch/cpu-csr.h| 9 + target/loongarch/tlb_helper.c | 17 - 2 files changed, 17 insertion

Re: [RFC PATCH] arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE

On 7/26/23 01:00, Shameer Kolothum wrote: Now that we have Eager Page Split support added for ARM in the kernel[0], enable it in Qemu. This adds, -eager-split-size to Qemu options to set the eager page split chunk size. -enable KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE. The chunk size specifies h

Re: [PATCH v3 01/17] i386: Fix comment style in topology.h

Hi Xiaoyao, On Mon, Aug 07, 2023 at 10:16:46AM +0800, Xiaoyao Li wrote: > Date: Mon, 7 Aug 2023 10:16:46 +0800 > From: Xiaoyao Li > Subject: Re: [PATCH v3 01/17] i386: Fix comment style in topology.h > > On 8/1/2023 6:35 PM, Zhao Liu wrote: > > From: Zhao Liu > > > > For function comments in th

Re: [PATCH v2 4/5] target/loongarch: Support LoongArch32 TLB entry

Hi, Jiajie 在 2023/8/7 下午1:17, Jiajie Chen 写道: On 2023/8/7 11:18, Jiajie Chen wrote: The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen ---   target/loongarch/cpu-csr.h    |  9 +   target/loongarch/tlb_helper.c | 17 ++