On 8/6/23 04:58, Nicholas Piggin wrote:
Patch 7 is not reqired for this?
No, USE_REG_TB has never been *required*.
The fallback path through tcg_out_movi will generate the 5 insn sequence for a full 64-bit
constant load. Mitigating that here is that patch 1 will emit PADDI for most of those
constants.
r~
Thanks,
Nick
On Sat Aug 5, 2023 at 7:33 AM AEST, Richard Henderson wrote:
With Power v3.1, we have pc-relative addressing and so
do not require a register holding the current TB.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index e8eced7cf3..5b243b2353 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -83,7 +83,7 @@
#define TCG_VEC_TMP2 TCG_REG_V1
#define TCG_REG_TB TCG_REG_R31
-#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
+#define USE_REG_TB (TCG_TARGET_REG_BITS == 64 && !have_isa_3_10)
/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
#define SZP ((int)sizeof(void *))
