On 5/5/23 05:03, Thomas Huth wrote:
On 04/05/2023 23.19, Daniel Henrique Barboza wrote:
On 5/4/23 15:05, Thomas Huth wrote:
When building QEMU with "--without-default-devices", the pseries
machine fails to start even when running with the --nodefaults option:
$ ./qemu-system-ppc64 --nod
On Wed, 3 May 2023 at 08:08, Richard Henderson
wrote:
>
> Notice when the host has additional atomic instructions.
> The new variables will also be used in generated code.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 3 May 2023 at 08:19, Richard Henderson
wrote:
>
> These features are present for Apple M1.
>
> Tested-by: Philippe Mathieu-Daudé
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> +#ifdef CONFIG_DARWIN
> +static bool sysctl_for_bool(const char *name)
> +{
> +
On Wed, 3 May 2023 at 08:09, Richard Henderson
wrote:
>
> Reorg TCG_OPF_64BIT and TCG_OPF_VECTOR into a two-bit field so
> that we can add TCG_OPF_128BIT without requiring another bit.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
migration/rdma.c has
/*
* Print and error on both the Monitor and the Log file.
*/
#define ERROR(errp, fmt, ...) \
do { \
fprintf(stderr, "RDMA ERROR: " fmt "\n", ## __VA_ARGS__); \
if (errp && (*(errp) == NULL)) { \
error_setg(errp
On 5/3/23 06:09, Nicholas Piggin wrote:
Rather than use a copy of CPUPPCState to store the host state while
the environment has been switched to the L2, use a new struct for
this purpose.
Have helper functions to save and load this host state.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spap
On 5/3/23 06:09, Nicholas Piggin wrote:
Arguably this is just shuffling around register accesses, but one nice
thing it does is allow the exit to save away the L2 state then switch
the environment to the L1 before copying L2 data back to the L1, which
logically flows more naturally and simplifi
On 5/3/23 06:09, Nicholas Piggin wrote:
Create spapr_nested.c for the nested HV implementation (modulo small
pieces in MMU and exception handling).
This separation of nested code in its own file is very much needed, but
this could have been a pre-patch to all the previous patches (at least
2
This series adds support for KVM AIA in RISC-V architecture.
In order to test these patches, we require Linux with KVM AIA support which can
be found in the qemu_kvm_aia branch at https://github.com/yong-xuan/linux.git
This kernel branch is based on the riscv_aia_v1 branch available at
https://git
From: Marc-André Lureau
The following changes since commit f6b761bdbd8ba63cee7428d52fb6b46e4224ddab:
Merge tag 'qga-pull-2023-05-04' of https://github.com/kostyanf14/qemu into
staging (2023-05-04 12:08:00 +0100)
are available in the Git repository at:
https://gitlab.com/marcandre.lureau/q
From: Dorinda Bassey
This commit adds a new audiodev backend to allow QEMU to use Pipewire as
both an audio sink and source. This backend is available on most systems
Add Pipewire entry points for QEMU Pipewire audio backend
Add wrappers for QEMU Pipewire audio backend in qpw_pcm_ops()
qpw_write
Update the linux headers to get the latest KVM RISC-V headers with AIA support
by the scripts/update-linux-headers.sh.
The linux headers is comes from the riscv_aia_v1 branch available at
https://github.com/avpatel/linux.git. It hasn't merged into the mainline kernel.
Signed-off-by: Yong-Xuan Wang
Remove M mode AIA devices when using KVM acceleration
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
---
hw/riscv/virt.c | 198 +---
1 file changed, 104 insertions(+), 94 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4e3efbee1
We check the in-kernel irqchip support when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
---
target/riscv/kvm.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 0f932a5b96..eb469e8ca5 10
implement a function to create an KVM AIA chip
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
---
target/riscv/kvm.c | 83
target/riscv/kvm_riscv.h | 3 ++
2 files changed, 86 insertions(+)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
On Fri, May 05, 2023 at 03:39:47PM +0400, marcandre.lur...@redhat.com wrote:
> From: Dorinda Bassey
>
> This commit adds a new audiodev backend to allow QEMU to use Pipewire as
> both an audio sink and source. This backend is available on most systems
>
> Add Pipewire entry points for QEMU Pipew
- Do not set the mmio operations of APLIC and IMSIC when using KVM AIA
- Send interrupt signal to KVM AIA via KVM_IRQ_LINE API
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
---
hw/intc/riscv_aplic.c | 19 +++
hw/intc/riscv_imsic.c | 16 +++-
2 files changed, 26
Select KVM AIA when the host kernel has in-kernel AIA chip support.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
---
hw/riscv/virt.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 396025b5a5..9fad01a5ab 100644
--- a/hw/riscv/virt.c
Hi
On Fri, May 5, 2023 at 3:43 PM Daniel P. Berrangé
wrote:
> On Fri, May 05, 2023 at 03:39:47PM +0400, marcandre.lur...@redhat.com
> wrote:
> > From: Dorinda Bassey
> >
> > This commit adds a new audiodev backend to allow QEMU to use Pipewire as
> > both an audio sink and source. This backend
Le 03/05/2023 à 17:34, Palmer Dabbelt a écrit :
On Wed, 03 May 2023 08:30:12 PDT (-0700), sch...@suse.de wrote:
From 912af433fa5d93ce81d2054135ed475ab7462d2d Mon Sep 17 00:00:00 2001
From: Andreas Schwab
Date: Tue, 18 Apr 2023 11:54:01 +0200
Signed-off-by: Andreas Schwab
---
v3: fix isa order
On Wed, 3 May 2023 at 08:09, Richard Henderson
wrote:
>
> Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
> This will allow the fast path to increase alignment to implement atomicity
> while not immediately raising an alignment exception.
>
> Signed-off-by: Richard Hend
Add new -run-with option with an async-teardown=on|off parameter. It
is visible in the output of query-command-line-options QMP command, so
it can be discovered and used by libvirt.
The option -async-teardown is now redundant, deprecate it.
v6->v7
* move variable declaration inside #ifdef to avoi
Am 04.05.2023 um 13:57 hat Kevin Wolf geschrieben:
> This QMP handler runs in a coroutine, so it must use the corresponding
> no_co_wrappers instead.
>
> Signed-off-by: Kevin Wolf
> Reviewed-by: Eric Blake
> Reviewed-by: Stefan Hajnoczi
I just noticed that this actually fixes a reported hang i
On Wed, 3 May 2023 at 08:11, Richard Henderson
wrote:
>
> Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
> This will allow the fast path to increase alignment to implement atomicity
> while not immediately raising an alignment exception.
>
> Signed-off-by: Richard Hend
On Wed, 3 May 2023 at 08:11, Richard Henderson
wrote:
>
> Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
> This will allow the fast path to increase alignment to implement atomicity
> while not immediately raising an alignment exception.
>
> Signed-off-by: Richard Hend
On Wed, 3 May 2023 at 08:12, Richard Henderson
wrote:
>
> Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
> This will allow the fast path to increase alignment to implement atomicity
> while not immediately raising an alignment exception.
>
> Signed-off-by: Richard Hend
On Wed, 3 May 2023 at 08:27, Richard Henderson
wrote:
>
> Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
> This will allow the fast path to increase alignment to implement atomicity
> while not immediately raising an alignment exception.
>
> Signed-off-by: Richard Hend
Bochs card is normal PCI Express card so it fits better in system with
PCI Express bus. VGA is simple legacy PCI card.
Signed-off-by: Marcin Juszkiewicz
---
hw/arm/sbsa-ref.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 3e3671f66
On Wed, 3 May 2023 at 08:10, Richard Henderson
wrote:
>
> Always reserve r3 for tlb softmmu lookup. Fix a bug in user-only
> ALL_QLDST_REGS, in that r14 is clobbered by the BLNE that leads
> to the misaligned trap.
>
> Signed-off-by: Richard Henderson
> ---
> /*
> - * r0-r2 will be overwritten
Daniel P. Berrangé wrote:
>> >
>> > This has a slight semantic behavioural change.
>>
>> Yeap.
>>
>> See the answer to Peter. But three things came to mind:
>>
>> a - the size of the buffer is small (between 32KB and 256KB depending
>> how you count it). So we are going to call qemu_fflus
On Wed, 3 May 2023 at 08:09, Richard Henderson
wrote:
>
> Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
> This will allow the fast path to increase alignment to implement atomicity
> while not immediately raising an alignment exception.
>
> Signed-off-by: Richard Hend
On Wed, 3 May 2023 at 08:29, Richard Henderson
wrote:
>
> Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
> This will allow the fast path to increase alignment to implement atomicity
> while not immediately raising an alignment exception.
>
> Signed-off-by: Richard Hend
On Wed, 3 May 2023 at 08:17, Richard Henderson
wrote:
>
> Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
> This will allow the fast path to increase alignment to implement atomicity
> while not immediately raising an alignment exception.
>
> Signed-off-by: Richard Hend
Add new -run-with option with an async-teardown=on|off parameter. It is
visible in the output of query-command-line-options QMP command, so it
can be discovered and used by libvirt.
The option -async-teardown is now redundant, deprecate it.
Reported-by: Boris Fiuczynski
Fixes: c891c24b1a ("os-po
On Wed, 3 May 2023 at 08:17, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/sparc64/tcg-target.c.inc | 15 +++
> 1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
> index e997db2645.
On Wed, 3 May 2023 at 08:12, Richard Henderson
wrote:
>
> Emphasize that the constant is signed.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/sparc64/tcg-target.c.inc | 30 +++---
> 1 file changed, 15 insertions(+), 15 deletions(-)
Commit message says we're just doin
On Wed, 3 May 2023 at 08:15, Richard Henderson
wrote:
>
> Emphasize that the constant is unsigned.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/sparc64/tcg-target.c.inc | 24 ++--
> 1 file changed, 10 insertions(+), 14 deletions(-)
>
> diff --git a/tcg/sparc64/tcg-target.
On Wed, 3 May 2023 at 08:09, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/sparc64/tcg-target.c.inc | 10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 3 May 2023 at 08:11, Richard Henderson
wrote:
>
> Drop the target-specific trampolines for the standard slow path.
> This lets us use tcg_out_helper_{ld,st}_args, and handles the new
> atomicity bits within MemOp.
>
> At the same time, use the full load/store helpers for user-only mode.
>
On Wed, 3 May 2023 at 08:19, Richard Henderson
wrote:
>
> These functions are now unused.
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 3 May 2023 at 08:15, Richard Henderson
wrote:
>
> This should be true of all server class loongarch64.
By this do you mean "anything that runs Linux" ?
If not, we should be a bit more user-friendly about bailing
out than just assert()ing. For the "tried to run on an
ARMv5" case we use er
Since v1:
Used the 'select if TCG' pattern for both build issues.
We don't want to use imply for semihosting because we'd need to
unpoison* CONFIG_SEMIHOSTING and include CONFIG_DEVICES from helper.c
when building with '--enable-tcg --without-default-devices'.
*- I see the config at build/config
On Wed, 3 May 2023 at 08:25, Richard Henderson
wrote:
>
> Test the final byte of an unaligned access.
> Use BSTRINS.D to clear the range of bits, rather than AND.
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
(at least, it's the same general shape as other architectures
On a build configured with: --disable-tcg --enable-xen it is possible
to produce a QEMU binary with no TCG nor KVM support. Skip the test if
that's the case.
Fixes: 0c1ae3ff9d ("tests/qtest: Fix tests when no KVM or TCG are present")
Reviewed-by: Paolo Bonzini
Signed-off-by: Fabiano Rosas
---
t
We cannot allow this config to be disabled at the moment as not all of
the relevant code is protected by it.
Commit 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a
KVM-only build") moved the CONFIGs of several boards to Kconfig, so it
is now possible that nothing selects ARM_V7M (e.g.
Semihosting has been made a 'default y' entry in Kconfig, which does
not work because when building --without-default-devices, the
semihosting code would not be available.
Make semihosting unconditional when TCG is present.
Fixes: 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a KVM-on
Le 09/04/2023 à 12:53, Michael Tokarev a écrit :
linux-user getgroups(), setgroups(), getgroups32() and setgroups32()
used alloca() to allocate grouplist arrays, with unchecked gidsetsize
coming from the "guest". With NGROUPS_MAX being 65536 (linux, and it
is common for an application to allocat
On Wed, 3 May 2023 at 08:20, Richard Henderson
wrote:
>
> Replace the unparameterized TCG_TARGET_HAS_MEMORY_BSWAP macro
> with a function with a memop argument.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 3 May 2023 at 08:13, Richard Henderson
wrote:
>
> Add opcodes for backend support for 128-bit memory operations.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On 05.05.23 11:53, Eugenio Perez Martin wrote:
On Fri, May 5, 2023 at 11:03 AM Hanna Czenczek wrote:
On 04.05.23 23:14, Stefan Hajnoczi wrote:
On Thu, 4 May 2023 at 13:39, Hanna Czenczek wrote:
[...]
All state is lost and the Device Initialization process
must be followed to make the devi
On Wed, 3 May 2023 at 08:12, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
ppc hypervisors turn HEAI interrupts into program interrupts injected
into the guest that executed the illegal instruction, if the hypervisor
doesn't handle it some other way.
The nexted-hv implementation failed to account for this HEAI->program
conversion. The virtual hypervisor wants to see the
On Wed, 3 May 2023 at 08:27, Richard Henderson
wrote:
>
> Examine MemOp for atomicity and alignment, adjusting alignment
> as required to implement atomicity on the host.
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
Hi Tobias/Peter,
Greetings.
In the following commit, I see you have added R52 support in Qemu.
commit 5f536d01d1141a56f5057b62c82fa94826d367f0
Author: Tobias Röhmel
Date: Tue Dec 6 11:25:04 2022 +0100
target/arm: Add ARM Cortex-R52 CPU
1. Do you have quick instructions on how to build
Support attaching/detaching namespaces during runtime.
Signed-off-by: Daniel Wagner
---
hw/nvme/ctrl.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index ac24eeb5ed5a..7bddbc644cae 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -8314,6 +
This is a follow up on a very old thread[1]. My aim is to attach/detatch nvme
devices during runtime and test the Linux nvme subsystem in the guest.
In order to it working, I had first to add hotplug able PCI bus and the
nvme-subsystem. The nvme-subsystem can't be instatiated during runtime so far
On Wed, 3 May 2023 at 08:12, Richard Henderson
wrote:
>
> No change to the ultimate load/store routines yet, so some atomicity
> conditions not yet honored, but plumbs the change to alignment through
> the relevant functions.
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
On Wed, 3 May 2023 at 08:14, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.c.inc | 38 +++-
> 1 file changed, 20 insertions(+), 18 deletions(-)
>
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 3 May 2023 at 08:12, Richard Henderson
wrote:
>
> No change to the ultimate load/store routines yet, so some atomicity
> conditions not yet honored, but plumbs the change to alignment through
> the relevant functions.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
than
On Wed, 3 May 2023 at 08:12, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 3 May 2023 at 08:41, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/mips/tcg-target.c.inc | 11 ---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
> index cd0254a0d7..43a8ffac17 1
On Wed, 3 May 2023 at 08:13, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/ppc/tcg-target.c.inc | 17 -
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
> index f0a4118bbb..60375804c
On Wed, 3 May 2023 at 08:13, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/riscv/tcg-target.c.inc | 8 ++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 37870c89fc..4dd33c73e8 10
On Wed, 3 May 2023 at 08:20, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/s390x/tcg-target.c.inc | 14 ++
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 3 May 2023 at 08:13, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/sparc64/tcg-target.c.inc | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
> index bb23038529..4f9ec02b1
Hi,
On 2023/5/3 15:06, Richard Henderson wrote:
This should be true of all server class loongarch64.
And desktop-class (i.e. all Loongson-3 series).
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 6 ++
1 file changed, 6 insertions(+)
diff --git a/tcg/loongarc
On Wed, 3 May 2023 at 08:18, Richard Henderson
wrote:
>
> Use the fpu to perform 64-bit loads and stores.
>
> Signed-off-by: Richard Henderson
> @@ -2091,7 +2095,20 @@ static void tcg_out_qemu_ld_direct(TCGContext *s,
> TCGReg datalo, TCGReg datahi,
> datalo = datahi;
>
On Wed, 3 May 2023 at 08:13, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> tcg/i386/tcg-target.h | 3 +-
> tcg/i386/tcg-target.c.inc | 184 +-
> 2 files changed, 182 insertions(+), 5 deletions(-)
>
Reviewed-by: Peter Maydell
th
Nicholas Piggin writes:
> ppc hypervisors turn HEAI interrupts into program interrupts injected
> into the guest that executed the illegal instruction, if the hypervisor
> doesn't handle it some other way.
>
> The nexted-hv implementation failed to account for this HEAI->program
> conversion. The
On Wed, 3 May 2023 at 08:12, Richard Henderson
wrote:
>
> We will need to allocate a second general-purpose temporary.
> Rename the existing temps to add a distinguishing number.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 3 May 2023 at 08:21, Richard Henderson
wrote:
>
> Use LDXP+STXP when LSE2 is not present and 16-byte atomicity is required,
> and LDP/STP otherwise. This requires allocating a second general-purpose
> temporary, as Rs cannot overlap Rn in STXP.
>
> Signed-off-by: Richard Henderson
> ---
On Wed, 3 May 2023 at 08:10, Richard Henderson
wrote:
>
> v1:
> https://lore.kernel.org/qemu-devel/20221118094754.242910-1-richard.hender...@linaro.org/
> v2:
> https://lore.kernel.org/qemu-devel/20230216025739.1211680-1-richard.hender...@linaro.org/
> v3:
> https://lore.kernel.org/qemu-devel/2
In spirit, this is a partial revert of commit 9b09503752 ("migration:
run setup callbacks out of big lock"), but only for the snapshot case.
For snapshots, the bdrv_writev_vmstate() function is used during setup
(in QIOChannelBlock backing the QEMUFile), but not holding the BQL
while calling it co
Replaces target_ulong with vaddr for guest virtual addresses in tlb_*()
functions and auxilliary structs.
Signed-off-by: Anton Johansson
---
accel/stubs/tcg-stub.c | 2 +-
accel/tcg/cputlb.c | 177 +--
accel/tcg/tb-maint.c | 2 +-
inclu
Use vaddr for guest virtual address in translator_use_goto_tb() and
translator_loop().
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
---
accel/tcg/translator.c| 10 +-
include/exec/translator.h | 6 +++---
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git
Based-on: 20230503072331.1747057-1-richard.hender...@linaro.org
("[RESEND PATCH 00/84] tcg: Build once for system, once for user")
This is a first patchset in removing target_ulong from non-target/
directories. As use of target_ulong is spread accross the codebase we
are attempting to target as f
Signed-off-by: Anton Johansson
---
accel/tcg/cpu-exec.c | 9 ++---
accel/tcg/translate-all.c | 3 ++-
target/alpha/cpu.h| 4 ++--
target/arm/cpu.h | 4 ++--
target/arm/helper.c | 4 ++--
target/avr/cpu.h | 4 ++--
target/cris/cpu.h | 4 ++--
target
Signed-off-by: Anton Johansson
---
accel/tcg/cputlb.c | 8
include/exec/cpu_ldst.h | 10 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 4807f1836d..38c2edb19a 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cp
Functions for probing memory accesses (and functions that call these)
are updated to take a vaddr for guest virtual addresses over
target_ulong.
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
---
accel/stubs/tcg-stub.c | 4 ++--
accel/tcg/cputlb.c | 12 ++--
accel/
Functions accessing MMULookupPageData are also updated.
Signed-off-by: Anton Johansson
---
accel/tcg/cputlb.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 38c2edb19a..d6f8bed9f0 100644
--- a/acc
Update atomic_mmu_lookup() and cpu_mmu_lookup() to take the guest
virtual address as a vaddr instead of a target_ulong.
Signed-off-by: Anton Johansson
Reviewed-by: Richard Henderson
---
accel/tcg/cputlb.c| 4 ++--
accel/tcg/user-exec.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions
Related functions dealing with the jump cache are also updated.
Signed-off-by: Anton Johansson
---
accel/tcg/cputlb.c | 2 +-
accel/tcg/tb-hash.h | 12 ++--
accel/tcg/tb-jmp-cache.h | 2 +-
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/accel/tcg/cputlb.c b/a
Signed-off-by: Anton Johansson
---
cpu.c | 2 +-
include/exec/exec-all.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/cpu.c b/cpu.c
index 9105c85404..41150a6136 100644
--- a/cpu.c
+++ b/cpu.c
@@ -293,7 +293,7 @@ void list_cpus(void)
}
#if defined(CO
Signed-off-by: Anton Johansson
---
accel/tcg/internal.h | 6 +++---
accel/tcg/translate-all.c | 10 +-
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h
index 8ca24420ea..9b04a33d58 100644
--- a/accel/tcg/internal.h
+++ b/acce
Signed-off-by: Anton Johansson
---
accel/tcg/cpu-exec.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 47fbbcb16d..4c56924711 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@
Use vaddr for guest virtual addresses for functions dealing with page
flags.
Signed-off-by: Anton Johansson
---
accel/tcg/user-exec.c| 44 +---
include/exec/cpu-all.h | 10
include/exec/translate-all.h | 2 +-
3 files changed, 27 insertions
Hi Ayan,
as far as I know, there is no board/SoC that uses the Cortex-R52 in Qemu
right now. If you want, I can try to find the one that I used
during development. I was able to run Zephyr in Qemu with that code.
Best regards,
Tobias
On 05.05.23 14:21, Ayan Kumar Halder wrote:
Hi Tobias/Pete
On Fri, May 05, 2023 at 12:51:45PM +0200, Markus Armbruster wrote:
> migration/rdma.c has
>
> /*
> * Print and error on both the Monitor and the Log file.
> */
> #define ERROR(errp, fmt, ...) \
> do { \
> fprintf(stderr, "RDMA ERROR: " fmt "\n", ## __VA_ARGS__
On Fri, May 5, 2023 at 11:51 AM Hanna Czenczek wrote:
>
> (By the way, thanks for the explanations :))
>
> On 05.05.23 11:03, Hanna Czenczek wrote:
> > On 04.05.23 23:14, Stefan Hajnoczi wrote:
>
> [...]
>
> >> I think it's better to change QEMU's vhost code
> >> to leave stateful devices suspende
On 05/05/2023 14.35, Fabiano Rosas wrote:
On a build configured with: --disable-tcg --enable-xen it is possible
to produce a QEMU binary with no TCG nor KVM support. Skip the test if
that's the case.
Fixes: 0c1ae3ff9d ("tests/qtest: Fix tests when no KVM or TCG are present")
Reviewed-by: Paolo B
On 05.05.23 16:26, Eugenio Perez Martin wrote:
On Fri, May 5, 2023 at 11:51 AM Hanna Czenczek wrote:
(By the way, thanks for the explanations :))
On 05.05.23 11:03, Hanna Czenczek wrote:
On 04.05.23 23:14, Stefan Hajnoczi wrote:
[...]
I think it's better to change QEMU's vhost code
to leav
On 04/05/23 1:46 pm, Daniel P. Berrangé wrote:
> On Wed, May 03, 2023 at 08:31:16PM +, tejus.gk wrote:
>> There are places in the code where the migration is marked failed with
>> MIGRATION_STATUS_FAILED, but the failiure reason is never updated. Hence
>> libvirt doesn't know why the migration
I stumbled over this property, looked closer, and now I'm confused.
Like most QOM properties, x-remote.auto-shutdown is virtually
undocumented. All we have is this comment in vfio-user-obj.c:
/**
* Usage: add options:
* -machine x-remote,vfio-user=on,auto-shutdown=on
*
On 5/4/23 18:17, Matheus Tavares Bernardino wrote:
Currently, the python scripts used for the hexagon building will not
abort the compilation when there is an error parsing a register. Let's
make the compilation properly fail in such cases by rasing an exception
instead of just printing a warni
On Fri, May 05, 2023 at 03:46:52PM +0200, Fiona Ebner wrote:
> To fix it, ensure that the BQL is held during setup. To avoid changing
> the behavior for migration too, introduce conditionals for the setup
> callbacks that need the BQL and only take the lock if it's not already
> held.
The major co
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230505-1
for you to fetch changes up to e1d084a8524a9225a46d485e2d164bb258f326f7:
target/riscv: add Ventana's Veyron V1 CPU (2023-05-05 10:49:50 +1000)
First RI
On 5/4/23 16:01, Cornelia Huck wrote:
I'm wondering whether we should block migration with MTE enabled in
general... OTOH, people probably don't commonly try to migrate with tcg,
unless they are testing something?
Yes, savevm/loadvm is an extremely useful tcg debugging tool.
r~
On 5/4/23 18:17, Matheus K. Ferst wrote:
On 04/05/2023 08:01, Richard Purdie wrote:
The following commits changed the code such that these instructions became
invalid
on pre 3.0 ISAs:
bf8adfd88b547680aa857c46098f3a1e94373160 - target/ppc: Move mffscrn[i] to
decodetree
394c2e2fda70da722f
This adds a new CONFIG_HEKI_TEST option to run tests at boot. Indeed,
because this patch series forbids the loading of kernel modules after
the boot, we need to make built-in tests. Furthermore, because we use
some symbols not exported to modules (e.g., kernel_set_to_readonly) this
could not work
This changes enable to enforce a deny-by-default execution security
policy for guest kernels, leveraged by the Heki implementation.
Create synthetic page faults when an access is denied by Heki. This
kind of kernel page fault needs to be handled by guests, which is not
currently the case, making
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