On 5/5/23 02:01, Alistair Francis wrote:
The following changes since commit f6b761bdbd8ba63cee7428d52fb6b46e4224ddab:
Merge tag 'qga-pull-2023-05-04' ofhttps://github.com/kostyanf14/qemu into
staging (2023-05-04 12:08:00 +0100)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230505-1
for you to fetch changes up to e1d084a8524a9225a46d485e2d164bb258f326f7:
target/riscv: add Ventana's Veyron V1 CPU (2023-05-05 10:49:50 +1000)
----------------------------------------------------------------
First RISC-V PR for 8.1
* CPURISCVState related cleanup and simplification
* Refactor Zicond and reuse in XVentanaCondOps
* Fix invalid riscv,event-to-mhpmcounters entry
* Support subsets of code size reduction extension
* Fix itrigger when icount is used
* Simplification for RVH related check and code style fix
* Add signature dump function for spike to run ACT tests
* Rework MISA writing
* Fix mstatus.MPP related support
* Use check for relationship between Zdinx/Zhinx{min} and Zfinx
* Fix the H extension TVM trap
* A large collection of mstatus sum changes and cleanups
* Zero init APLIC internal state
* Implement query-cpu-definitions
* Restore the predicate() NULL check behavior
* Fix Guest Physical Address Translation
* Make sure an exception is raised if a pte is malformed
* Add Ventana's Veyron V1 CPU
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as
appropriate.
r~
