On 12/04/2023 04.22, Mike Stramba wrote:
I have a CKD file, created with the Hercules dasdinit program.
It's a (hercules) 3350 uncompressed file.
I've put a small "hello world" IPL program on it, and it works fine with
Hercules
When I try to run it with qemu-system-s390x I get :
LOADPARM=[
This v2 contains a change suggested by Peter Maydell in patch v1.
v1 link:https://lore.kernel.org/all/20230403084245.54861-1-zeng...@kylinos.cn/
ChangeLog:
v1->v2:
- Patch 1: No change in patch v1
- Patch 2: Fix the check on the return value of fread() in ct3_load_cdat
Hao Zeng (2):
The bug in this code (CID 1507822) is that the
check on the return value of fread() is wrong. fread()
returns the number of items read or written, so
checking for == 0 only catches "no data read at all",
not "only read half the data".
Signed-off-by: Zeng Hao
Suggested-by: Peter Maydell
---
hw/c
opened file processor not closed,May cause file processor leaks
Fixes:aba578bdace5303a441f8a37aad781b5cb06f38c
Signed-off-by: Zeng Hao
Suggested-by: Xie Ming
---
hw/cxl/cxl-cdat.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/cxl/cxl-cdat.c b/hw/cxl/cxl-cdat.c
index 137abd0992..ba7ed1a
Commit 1b2b12376c8 ("intel-iommu: PASID support") takes PASID into
account when calculating iotlb hash like:
static guint vtd_iotlb_hash(gconstpointer v)
{
const struct vtd_iotlb_key *key = v;
return key->gfn | ((key->sid) << VTD_IOTLB_SID_SHIFT) |
(key->level) << VTD_IOTLB_LVL
On Tue, 11 Apr 2023 18:00:49 +0200
Igor Mammedov wrote:
> On Tue, 28 Mar 2023 11:59:26 -0400
> Eric DeVolder wrote:
>
> > Currently i386 QEMU generates MADT revision 3, and reports
> > MADT revision 1. ACPI 6.3 introduces MADT revision 5.
> >
> > For MADT revision 4, that introduces ARM GIC st
Peter Maydell writes:
> On Tue, 11 Apr 2023 at 15:14, Peter Xu wrote:
>>
>> On Mon, Apr 10, 2023 at 11:32:08AM +0800, Jason Wang wrote:
>> > @@ -222,9 +222,9 @@ static guint vtd_iotlb_hash(gconstpointer v)
>> > {
>> > const struct vtd_iotlb_key *key = v;
>> >
>> > -return key->gfn |
Jason Wang writes:
> Commit 1b2b12376c8 ("intel-iommu: PASID support") takes PASID into
> account when calculating iotlb hash like:
>
> static guint vtd_iotlb_hash(gconstpointer v)
> {
> const struct vtd_iotlb_key *key = v;
>
> return key->gfn | ((key->sid) << VTD_IOTLB_SID_SHIFT) |
>
I see, let me mark it as "expected" regression and hopefully I'll detect the
optimization if they are ever implemented. Thank you for the explanation.
Regards,
Lukáš
Dne 06. 04. 23 v 17:07 Eric Blake napsal(a):
> On Thu, Apr 06, 2023 at 12:55:38PM +0200, Lukáš Doktor wrote:
>> Hello Florian, fol
As per the specification, in 64-bit, if any of the pte reserved bits 60-54
is set, an exception should be triggered (see 4.4.1, "Addressing and Memory
Protection"), so implement this behaviour in the address translation process.
Reported-by: Andrea Parri
Signed-off-by: Alexandre Ghiti
---
targe
On Apr 11 21:04, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Fix two issues reported by Coverity (CID 1507979 and 1508281).
>
> Klaus Jensen (2):
> hw/nvme: fix memory leak in fdp ruhid parsing
> hw/nvme: fix memory leak in nvme_dsm
>
> hw/nvme/ctrl.c | 3 +++
> hw/nvme/ns.c | 3 ++-
>
Hello,
I am interested in adding AVX512 to qemu.
Is anyone currently working on this ?
If yes, when is it expected to be done ?
I was trying to run a C program and failed with the following error at this
instruction:
*62 f2 7d 48 18 0d fa 0c 00 00 vbroadcastss 0xcfa(%rip),%zmm1qemu: uncaugh
On 11/4/23 21:04, Klaus Jensen wrote:
From: Klaus Jensen
Coverity reports a memory leak of memory when parsing ruhids at
namespace initialization. Since this is just working memory, not needed
beyond the scope of the functions, fix this by adding a g_autofree
annotation.
Reported-by: Coverity
On 11/4/23 21:04, Klaus Jensen wrote:
From: Klaus Jensen
The iocb (and the allocated memory to hold LBA ranges) leaks if reading
the LBA ranges fails.
Fix this by adding a free and an unref of the iocb.
Reported-by: Coverity (CID 1508281)
Fixes: d7d1474fd85d ("hw/nvme: reimplement dsm to allo
On 12/4/23 09:16, Hao Zeng wrote:
opened file processor not closed,May cause file processor leaks
Fixes:aba578bdace5303a441f8a37aad781b5cb06f38c
Fixes: aba578bdac ("hw/cxl: CDAT Data Object Exchange implementation")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Zeng Hao
Suggested-by: X
On Wed, Apr 05, 2023 at 09:58:44PM +, Ackerley Tng wrote:
>
> Thanks again for your review!
>
> Christian Brauner writes:
> > On Tue, Apr 04, 2023 at 03:53:13PM +0200, Christian Brauner wrote:
> > > On Fri, Mar 31, 2023 at 11:50:39PM +, Ackerley Tng wrote:
> > > >
> > > > ...
> > > >
> >
On 12/4/23 09:16, Hao Zeng wrote:
The bug in this code (CID 1507822) is that the
check on the return value of fread() is wrong. fread()
returns the number of items read or written, so
checking for == 0 only catches "no data read at all",
not "only read half the data".
Signed-off-by: Zeng Hao
Su
On Apr 12 11:54, Philippe Mathieu-Daudé wrote:
> On 11/4/23 21:04, Klaus Jensen wrote:
> > From: Klaus Jensen
> >
> > The iocb (and the allocated memory to hold LBA ranges) leaks if reading
> > the LBA ranges fails.
> >
> > Fix this by adding a free and an unref of the iocb.
> >
> > Reported-by
From: Klaus Jensen
Coverity reports a memory leak of memory when parsing ruhids at
namespace initialization. Since this is just working memory, not needed
beyond the scope of the functions, fix this by adding a g_autofree
annotation.
Reported-by: Coverity (CID 1507979)
Fixes: 73064edfb864 ("hw/n
From: Klaus Jensen
Hi Peter,
The following changes since commit 6c50845a9183610cfd4cfffd48dfc704cd340882:
hw/i2c/allwinner-i2c: Fix subclassing of TYPE_AW_I2C_SUN6I (2023-04-11
14:13:29 +0100)
are available in the Git repository at:
git://git.infradead.org/qemu-nvme.git tags/coverity-fix
From: Klaus Jensen
The iocb (and the allocated memory to hold LBA ranges) leaks if reading
the LBA ranges fails.
Fix this by adding a free and an unref of the iocb.
Reported-by: Coverity (CID 1508281)
Fixes: d7d1474fd85d ("hw/nvme: reimplement dsm to allow cancellation")
Reviewed-by: Philippe M
On 12/4/23 07:39, Thomas Huth wrote:
On 11/04/2023 23.04, Vikram Garhwal wrote:
Xen is supported for aarch64 via xenpvh machine. disable-tcg option
fails the
build for aarch64 target.
Link for xen on arm patch series:
https://mail.gnu.org/archive/html/qemu-devel/2023-02/msg03979.html
Signed
On 12/4/23 03:04, Wu, Fei wrote:
On 4/11/2023 5:02 PM, Bin Meng wrote:
When reading a non-existent CSR QEMU should raise illegal instruction
exception, but currently it just exits due to the g_assert() check.
I verified that 'csrr t3, 0x4' in user space didn't cause qemu exit but
raised illega
Vikram Garhwal writes:
> Xen is supported for aarch64 via xenpvh machine. disable-tcg option fails the
> build for aarch64 target.
>
> Link for xen on arm patch series:
> https://mail.gnu.org/archive/html/qemu-devel/2023-02/msg03979.html
>
> Signed-off-by: Vikram Garhwal
> ---
> .gitlab-ci.d
On 4/11/23 19:09, Warner Losh wrote:
+++ b/bsd-user/syscallhdr.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+in="$1"
+out="$2"
+bsd="$3"
+
+awk -v bsd="$3" '{sub("SYS_", "TARGET_" bsd "_NR_", $0); print;}' < $in > $out
If the host/guest syscall numbers always match, there's no point in using
TARGET_freebsd
On 4/11/23 20:34, Thomas Huth wrote:
For being able to build universal binaries one day, we need certain
files to be independent from the emulated target. qtest.c is one of
these files. Rework the target specific code in there so we can
finally move it from "specific_ss" to "softmmu_ss".
Thomas
On 4/11/23 20:35, Daniel Henrique Barboza wrote:
This new abstract type will be used to differentiate between static and
non-static CPUs in query-cpu-definitions.
All generic CPUs were changed to be of this type. Named CPUs are kept as
TYPE_RISCV_CPU and will still be considered static.
This is
On 11/4/23 19:30, Michael Tokarev wrote:
11.04.2023 15:09, Peter Maydell wrote:
..
Frankly I would prefer to just say "we don't support x32".
It's a weird non-standard configuration that as far as I'm
aware is very little used. Its stats in the debian
popularity-contest graphs peaked at 18 users
On 4/12/23 04:33, Weiwei Li wrote:
Add trans_* and helper function for Zfbfmin instructions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/fpu_helper.c | 12 +
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode
On 4/12/23 04:33, Weiwei Li wrote:
Add trans_* and helper function for Zvfbfmin instructions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/helper.h | 3 +
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvbf16.
On 4/12/23 04:33, Weiwei Li wrote:
Add trans_* and helper function for Zvfbfwma instructions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvbf16
On 4/11/23 20:34, Thomas Huth wrote:
Ideally, qtest.c should be independent from target specific code, so
we only have to compile it once for all targets. Thus start improving
the situation by moving the pseries related code to hw/ppc/spapr_rtas.c
instead and allow target code to register a callb
On 4/11/23 20:34, Thomas Huth wrote:
The code in this file is not performance critical, so we can use
the target independent endianess functions to only compile this
file once for all targets.
Signed-off-by: Thomas Huth
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
softmmu/qtest.c |
On Wed, Apr 12, 2023 at 12:55 PM Weiwei Li wrote:
>
>
> On 2023/4/12 10:12, Alistair Francis wrote:
> > On Fri, Apr 7, 2023 at 6:23 AM Daniel Henrique Barboza
> > wrote:
> >> Hi,
> >>
> >> This patch is going to break the sifive_u boot if I rebase
> >>
> >> "[PATCH v6 0/9] target/riscv: rework CP
On Mon, Apr 10, 2023 at 10:46 PM Ivan Klokov wrote:
>
> Added QEMU option 'vpu' to log vector extension registers such as gpr\fpu.
>
> Signed-off-by: Ivan Klokov
Reviewed-by: Alistair Francis
Alistair
> ---
> accel/tcg/cpu-exec.c | 3 +++
> include/hw/core/cpu.h | 2 ++
> include/qemu/log.h
On Tue, Apr 11, 2023 at 5:05 PM Hanna Czenczek wrote:
>
> If the back-end supports the VHOST_USER_F_PROTOCOL_FEATURES feature,
> setting the vhost features will set this feature, too. Doing so
> disables all vrings, which may not be intended.
>
> For example, enabling or disabling logging during
On Mon, Apr 10, 2023 at 10:47 PM Ivan Klokov wrote:
>
> Print RvV extesion register to log if VPU option is enabled.
>
> Signed-off-by: Ivan Klokov
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 56 +-
> 1 file changed, 55 inse
Qemu v7.2.1 can be compiled with Xen 4.6, but v8.0.0-rc3 needs now at least Xen
4.7.
Is Xen older than 4.7 still a supported target? There is a lot compat code, and
the meson checks go back to 4.2.
Olaf
FAILED: libcommon.fa.p/hw_xen_xen-operations.c.o
/usr/bin/gcc-7 -m64 -mcx16 -Ilibcommon.f
On 4/11/23 20:34, Thomas Huth wrote:
In some cases of target independent code, it would be useful to have access
to the functions that swap endianess in case it differs between guest and
host. Thus re-implement the tswapXX() functions in a new header that can be
included separately. The check whe
Since the former nfs_get_allocated_file_size is now a coroutine
function, it must suspend rather than poll. Switch BDRV_POLL_WHILE()
to a qemu_coroutine_yield() loop and schedule nfs_co_generic_bh_cb()
in place of the call to bdrv_wakeup().
Fixes: 82618d7bc341 ("block: Convert bdrv_get_allocated_
On 2023/4/12 18:55, Alistair Francis wrote:
On Wed, Apr 12, 2023 at 12:55 PM Weiwei Li wrote:
On 2023/4/12 10:12, Alistair Francis wrote:
On Fri, Apr 7, 2023 at 6:23 AM Daniel Henrique Barboza
wrote:
Hi,
This patch is going to break the sifive_u boot if I rebase
"[PATCH v6 0/9] target/r
On Tue, 11 Apr 2023 at 16:02, Kevin Wolf wrote:
>
> At the first sight, this one probably looks huge for -rc4. But it's
> mainly because Paolo split his fix into many very small patches. As you
> can see in the diffstat below, it's not all that bad (and half of the
> insertions there are for a new
On Wed, 12 Apr 2023 at 02:08, Gavin Shan wrote:
>
> Hi Peter,
>
> On 3/27/23 9:26 PM, Igor Mammedov wrote:
> > On Fri, 17 Mar 2023 14:25:39 +0800
> > Gavin Shan wrote:
> >
> >> For arm64 and riscv architecture, the driver (/base/arch_topology.c) is
> >> used to populate the CPU topology in the Li
v6: 20230325105429.1142530-1-richard.hender...@linaro.org
Changes for v7:
* Rebase on Alistair's riscv-to-apply.next.
* Replace priv_level() with ctx->priv in trans_xthead.c.inc (Zhiwei).
r~
Fei Wu (2):
target/riscv: Separate priv from mmu_idx
target/riscv: Reduce overhead of MSTATUS_S
From: LIU Zhiwei
Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a
normal way.
It will make it hard to change the tb flags layout. And even worse, if we
want to keep tb flags for a same extension togather without a hole.
Reviewed-by: Richard Henderson
Signed-off-by: LIU Z
From: LIU Zhiwei
Virt enabled state is not a constant, so we should put it into tb flags.
Thus we can use it like a constant condition at translation phase.
Reported-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: LIU Zhiwei
Reviewed-by: Weiwei Li
Message-Id: <20230324143
From: LIU Zhiwei
The pointer masking is the only extension that directly use status.
The vector or float extension uses the status in an indirect way.
Replace the pointer masking extension special status fields with
the general status.
Reviewed-by: Richard Henderson
Signed-off-by: LIU Zhiwei
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel Henrique Barboza
Message-Id: <20230325105429.1142530-24-richard.hender...@linaro.org>
---
target/riscv/cpu_helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff -
Move the check from the top of get_physical_address to
the two callers, where passing mmu_idx makes no sense.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel Henrique Barboza
Message-Id: <20230325105429.1142530-19-richard.hender...@linaro
Merge with mstatus_{fs,vs}. We might perform a redundant
assignment to one or the other field, but it's a trivial
and saves 4 bits from TB_FLAGS.
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel Henrique Barboza
M
Implement these instructions via helpers, in expectation
of determining the mmu_idx to use at runtime. This allows
the permission check to also be moved out of line, which
allows HLSX to be removed from TB_FLAGS.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei
Move and rename riscv_cpu_two_stage_lookup, to match
the other mmuidx_* functions.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel Henrique Barboza
Message-Id: <20230325105429.1142530-15-richard.hender...@linaro.org>
---
target/riscv/cpu
In get_physical_address, we should use the setting passed
via mmu_idx rather than checking env->mstatus directly.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel Henrique Barboza
Message-Id: <20230325105429.1142530-13-richard.hender...@li
These values are constant for every level of pte lookup.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel Henrique Barboza
Message-Id: <20230325105429.1142530-20-richard.hender...@linaro.org>
---
target/riscv/cpu_helper.c | 16 ---
From: LIU Zhiwei
Once we mistook the vstart directly from the env->vstart. As env->vstart is not
a constant, we should record it in the tb flags if we want to use
it in translation.
Reported-by: Richard Henderson
Reviewed-by: Richard Henderson
Signed-off-by: LIU Zhiwei
Reviewed-by: Weiwei Li
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too much if tlb_flush() gets called for every SUM change.
This patch creates a separate MMU index for S+SUM, so that it's not
ne
Implement this by adjusting prot, which reduces the set of
checks required. This prevents exec to be set for U pages
in MMUIdx_S_SUM. While it had been technically incorrect,
it did not manifest as a bug, because we will never attempt
to execute from MMUIdx_S_SUM.
Signed-off-by: Richard Henderso
Use the priv level encoded into the mmu_idx, rather than
starting from env->priv. We have already checked MPRV+MPP
in riscv_cpu_mmu_index -- no need to repeat that.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel Henrique Barboza
Message
Move the code that never loops outside of the loop.
Unchain the if-return-else statements.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel Henrique Barboza
Message-Id: <20230325105429.1142530-21-richard.hender...@linaro.org>
---
target/r
The current cpu_mmu_index value is really irrelevant to
the HLV/HSV lookup. Provide the correct priv level directly.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel Henrique Barboza
Message-Id: <20230325105429.1142530-16-richard.hender..
Incorporate the virt_enabled and MPV checks into the cpu_mmu_index
function, so we don't have to keep doing it within tlb_fill and
subroutines. This also elides a flush on changes to MPV.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel He
From: Fei Wu
Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
this assumption won't last as we are about to add more mmu_idx. Here an
individual priv field is added into TB_FLAGS.
Reviewed-by: Richard Henderson
Signed-off-by: Fei Wu
Message-Id: <20230324054154.414846-2-f
If we want to give the debugger a greater view of memory than
the cpu, we should simply disable the access check entirely,
not simply for this one corner case.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel Henrique Barboza
Message-Id: <
The debugger should not modify PTE_A or PTE_D.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel Henrique Barboza
Message-Id: <20230325105429.1142530-22-richard.hender...@linaro.org>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1
At least RISC-V has the need to be able to perform a read
using execute permissions, outside of translation.
Add helpers to facilitate this.
Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel Henrique Barboza
Message-Id: <20230325105429.1142530
Table 9.5 "Effect of MPRV..." specifies that MPV=1 uses VS-level
vsstatus.SUM instead of HS-level sstatus.SUM.
For HLV/HSV instructions, the HS-level register does not apply, but
the VS-level register presumably does, though this is not mentioned
explicitly in the manual. However, it matches the
On Tue, 11 Apr 2023 at 19:12, Bartell, Paul wrote:
> Bug filed at https://gitlab.com/qemu-project/qemu/-/issues/1590 with binary
> attached and some additional logs.
>
> Adding the qemu-stable list since semihosting and gdb debugging for all
> ARMv8M targets is broken in the current stable relea
We will enable more uses of this bit in the future.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel Henrique Barboza
Message-Id: <20230325105429.1142530-12-richard.hender...@linaro.org>
---
target/riscv/internals.h | 6 --
target/ri
Use the new functions to properly check execute permission
for the read rather than read permission.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Weiwei Li
Tested-by: Daniel Henrique Barboza
Message-Id: <20230325105429.1142530-10-richard.hender...@linaro.org>
---
We were effectively computing the protection bits twice,
once while performing access checks and once while returning
the valid bits to the caller. Reorg so we do this once.
Move the computation of mxr close to its single use.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Revi
On 4/11/23 14:12, Philippe Mathieu-Daudé wrote:
On 8/4/23 04:42, Richard Henderson wrote:
There are several places where we already convert back from
bool to type. Clean things up by using type throughout.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 35 +
On 05.04.23 18:31, Paolo Bonzini wrote:
Request queuing prevents new requests from being submitted to the
BlockDriverState, not allowing them to start instead of just letting
them complete before bdrv_drained_begin() returns.
The reason for this was to ensure progress and avoid a livelock
in blk
On Wed, Apr 12, 2023 at 1:54 PM Hanna Czenczek wrote:
> On 05.04.23 18:31, Paolo Bonzini wrote:
> > +if (busy || blk->in_flight) {
> > +return true;
> > +}
> > +
> > +if (qatomic_read(&blk->request_queuing) == BLK_QUEUE_READY) {
> > +qatomic_set(&blk->request_queuing, B
Hello,
It seems the current source fails to compile with up to date msys2.
Source is configured with:
./configure --target-list="ppc-softmmu" --enable-gtk --enable-sdl
--enable-slirp
FAILED: qga/vss-win32/qga-vss.dll.p/install.cpp.obj
"c++" "-m64" "-mcx16" "-Iqga/vss-win32/qga-vss.dll.p" "-Iqga/
Olaf Hering writes:
> [[PGP Signed Part:Undecided]]
> Qemu v7.2.1 can be compiled with Xen 4.6, but v8.0.0-rc3 needs now at
> least Xen 4.7.
Was this caused by the addition of the KVM Xen target support or some
other churn since?
>
> Is Xen older than 4.7 still a supported target? There is a
On Wed, 12 Apr 2023 at 13:05, Howard Spoelstra wrote:
>
> Hello,
>
> It seems the current source fails to compile with up to date msys2.
>
> Source is configured with:
> ./configure --target-list="ppc-softmmu" --enable-gtk --enable-sdl
> --enable-slirp
Are you using a not-up-to-date version of t
On Wed, 12 Apr 2023, Howard Spoelstra wrote:
It seems the current source fails to compile with up to date msys2.
See here: https://qemu.weilnetz.de/
I think there are some patches there that aren't upstream. I don't know
why and also don't know why those binaries are not built from QEMU master
Walid Ghandour writes:
> Hello,
>
> I am interested in adding AVX512 to qemu.
(add x86 TCG maintainers to CC)
> Is anyone currently working on this ?
>
> If yes, when is it expected to be done ?
I don't think there is currently any active effort to add AVX512
support. There have been various
On 12.04.23 12:55, German Maglione wrote:
On Tue, Apr 11, 2023 at 5:05 PM Hanna Czenczek wrote:
If the back-end supports the VHOST_USER_F_PROTOCOL_FEATURES feature,
setting the vhost features will set this feature, too. Doing so
disables all vrings, which may not be intended.
For example, ena
On Thu, 30 Mar 2023 13:58:22 +0200
Fiona Ebner wrote:
> Am 30.03.23 um 10:22 schrieb Igor Mammedov:
> > On Tue, 28 Mar 2023 14:58:21 +0200
> > Fiona Ebner wrote:
> >
> >> Am 10.06.22 um 09:57 schrieb Michael S. Tsirkin:
> >>> From: Igor Mammedov
> >>>
> >>> replaces ad-hoc build_isa_device
We're about to move the TCG-only -cpu max configuration code under
CONFIG_TCG. To be able to do that we need to make sure the qtests
still have some cpu configured even when no other accelerator is
available.
Delineate now what is used with TCG-only and what is also used with
qtests to make the su
From: Claudio Fontana
move the module containing cpu models definitions
for 32bit TCG-only CPUs to tcg/ and rename it for clarity.
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Acked-by: Thomas Huth
---
hw/arm/virt.c | 2
Introduce aarch64_max_tcg_initfn that contains the TCG-only part of
-cpu max configuration. We'll need that to be able to restrict this
code to a TCG-only config in the next patches.
Signed-off-by: Fabiano Rosas
---
target/arm/cpu64.c | 32 ++--
1 file changed, 18 ins
The sve-max-vq property has been removed from the -cpu max used with
KVM, so code under kvm_enabled in cpu_max_set_sve_max_vq is not
reachable.
Fixes: 0baa21be49 ("target/arm: Make KVM -cpu max exactly like -cpu host")
Signed-off-by: Fabiano Rosas
---
target/arm/cpu64.c | 6 --
1 file change
Rebased on master, moved the neoverse-n1 regs into tcg/cpu64.c and
extracted three new patches from the cpu64 move:
- patch 2: remove dead code from cpu_max_get_sve_max_vq
- patch 3: move TCG -cpu max code into it's own function
- patch 4: add the tcg_enabled || qtest_enabled logic
CI run: https:
Move all the CONFIG_FOO=y from default.mak into "default y if TCG"
statements in Kconfig. That way they won't be selected when
CONFIG_TCG=n.
I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to
keep the two default.mak files not empty and keep aarch64-default.mak
including arm-defaul
The migration tests are currently broken for an aarch64 host because
the tests pass no 'machine' and 'cpu' options on the QEMU command
line.
Add a separate class to each architecture so that we can specify
'machine' and 'cpu' options instead of relying on defaults.
Add a skip decorator to keep th
It is possible to have a build with both TCG and KVM disabled due to
Xen requiring the i386 and x86_64 binaries to be present in an aarch64
host.
If we build with --disable-tcg on the aarch64 host, we will end-up
with a QEMU binary (x86) that does not support TCG nor KVM.
Skip tests that crash or
The file cpu_tcg.c is about to be moved into the tcg/ directory, so
move the register definitions into a new file.
Also move the function declaration to the more appropriate cpregs.h.
Reviewed-by: Richard Henderson
Signed-off-by: Fabiano Rosas
---
target/arm/cortex-regs.c | 69
We are about to enable the build without TCG, so CONFIG_SEMIHOSTING
and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in
default.mak anymore. So reflect the change in a Kconfig.
Instead of using semihosting/Kconfig, use a target-specific file, so
that the change doesn't affect ot
From: Philippe Mathieu-Daudé
Add a manual new job to cross-build the aarch64 target with
only the KVM accelerator enabled (in particular, no TCG).
Re-enable running the similar job on the project Aarch64
custom runner.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Fabiano Rosas
Reviewe
Move the 64-bit CPUs that are TCG-only:
- cortex-a35
- cortex-a55
- cortex-a72
- cortex-a76
- a64fx
- neoverse-n1
Keep the CPUs that can be used with KVM:
- cortex-a57
- cortex-a53
- max
- host
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
hw/arm/virt.c | 6 +-
Wed, 12 Apr 2023 12:46:23 +0100 Alex Bennée :
> Olaf Hering writes:
> > Qemu v7.2.1 can be compiled with Xen 4.6, but v8.0.0-rc3 needs now at least
> > Xen 4.7.
> Was this caused by the addition of the KVM Xen target support or some other
> churn since?
I did not bisect this failure, just ch
Am 12.04.23 um 14:12 schrieb BALATON Zoltan:
On Wed, 12 Apr 2023, Howard Spoelstra wrote:
It seems the current source fails to compile with up to date msys2.
See here: https://qemu.weilnetz.de/
I think there are some patches there that aren't upstream. I don't
know why and also don't know wh
On 4/11/2023 3:27 PM, Alex Bennée wrote:
>
> "Wu, Fei" writes:
>
>> On 4/10/2023 6:36 PM, Alex Bennée wrote:
>>>
>>> Richard Henderson writes:
>>>
On 4/6/23 00:46, Alex Bennée wrote:
> If your aim is to examine JIT efficiency what is wrong with the current
> "info jit" that you can
Alex Bennée writes:
> Vikram Garhwal writes:
>
>> Xen is supported for aarch64 via xenpvh machine. disable-tcg option fails the
>> build for aarch64 target.
>>
>> Link for xen on arm patch series:
>> https://mail.gnu.org/archive/html/qemu-devel/2023-02/msg03979.html
>>
>> Signed-off-by: Vikram
On Wed, 12 Apr 2023 12:02:47 +0200
Philippe Mathieu-Daudé wrote:
> On 12/4/23 09:16, Hao Zeng wrote:
> > The bug in this code (CID 1507822) is that the
> > check on the return value of fread() is wrong. fread()
> > returns the number of items read or written, so
> > checking for == 0 only catches
On 4/7/23 00:30, Weiwei Li wrote:
Using implicitly enabled extensions such as Zca/Zcf/Zcd instead of their
super extensions can simplify the extension related check. However, they
may have higher priv version than their super extensions. So we should mask
them in the isa_string based on priv v
On 4/12/23 00:06, Weiwei Li wrote:
Even though Zca/Zcf/Zcd can be included by C/F/D, however, their priv
version is higher than the priv version of C/F/D. So if we use check
for them instead of check for C/F/D totally, it will trigger new
problem when we try to disable the extensions based on
On Tue, 11 Apr 2023 16:52:58 +0100
Peter Maydell wrote:
> On Mon, 7 Nov 2022 at 22:49, Michael S. Tsirkin wrote:
> >
> > From: Huai-Cheng Kuo
> >
> > The Data Object Exchange implementation of CXL Coherent Device Attribute
> > Table (CDAT). This implementation is referring to "Coherent Device
>
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