On 12/4/23 03:04, Wu, Fei wrote:
On 4/11/2023 5:02 PM, Bin Meng wrote:
When reading a non-existent CSR QEMU should raise illegal instruction
exception, but currently it just exits due to the g_assert() check.
I verified that 'csrr t3, 0x4' in user space didn't cause qemu exit but
raised illegal instruction after applying this patch.
Good candidate to add in tests/tcg/riscv64/ :)
This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617,
Some comments are also added to indicate that predicate() must be
provided for an implemented CSR.
Reported-by: Fei Wu <fei2...@intel.com>
Signed-off-by: Bin Meng <bm...@tinylab.org>
---
target/riscv/csr.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
