When TCG is disabled this part of the code should not be reachable, so
wrap it with an ifdef for now.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Tested-by: Philippe Mathieu-Daudé
---
target/arm/ptw.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/arm/ptw.c b/ta
The migration tests are currently broken for an aarch64 host because
the tests pass no 'machine' and 'cpu' options on the QEMU command
line.
Add a separate class to each architecture so that we can specify
'machine' and 'cpu' options instead of relying on defaults.
Add a skip decorator to keep th
Il ven 17 feb 2023, 19:47 Thomas Huth ha scritto:
> On 17/02/2023 16.59, Daniel P. Berrangé wrote:
> > On Fri, Feb 17, 2023 at 04:55:49PM +0100, Markus Armbruster wrote:
>
> > The cost/benefit tradeoff of dropping the platforms entirely
> > is not obviously favourable when we don't have clea
Move the 64-bit CPUs that are TCG-only:
- cortex-a35
- cortex-a55
- cortex-a72
- cortex-a76
- a64fx
- neoverse-n1
Keep the CPUs that can be used with KVM:
- cortex-a57
- cortex-a53
- max
- host
For the special case "max" CPU, there's a nuance that while KVM/HVF
use the "host" model instead, we st
From: Christoph Muellner
The RISC-V base cache management operation (CBO) ISA extension has been
ratified. It defines three extensions: Cache-Block Management, Cache-Block
Prefetch and Cache-Block Zero. More information about the spec can be
found at [1].
Let's start by implementing the Cache-Bl
From: Christoph Muellner
Zicbom is the Cache-Block Management extension defined in the already
ratified RISC-V Base Cache Management Operation (CBO) ISA extension [1].
The extension contains three instructions: cbo.clean, cbo.flush and
cbo.inval. All of them must be implemented in the same group
From: Christoph Muellner
The existing probe_access* functions do not allow to specify the
access size and a non-faulting behavior at the same time.
This is resolved by adding a generalization of probe_access_flags()
that takes an additional size parameter.
The semantics is basically the same as
From: Christoph Muellner
The cmo.prefetch instructions are nops for QEMU (no emulation of the
memory hierarchy, no illegal instructions, no permission faults, no
traps).
Add a comment noting where they would be decoded in case cbo.prefetch
instructions become relevant in the future.
Co-develope
Hi,
This new version contains a change in patch 2 based on Richard's
feedback in v5 [1].
Changes from v5:
- patch 2:
- check if 'mem' is mapped into RAM with 'tlb_vaddr_to_host' before
zeroing it.
- v5 link: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg04414.html
[1] https://li
QEMU configure script goes into an infinite error printing loop
when in read only directory due to 'build' dir never being created.
Checking if 'mkdir dir' succeeds prevents this error.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/321
Signed-off-by: Dinah Baum
---
Changes since v2:
Up
On Thu, Feb 16, 2023 at 5:58 AM Thomas Huth wrote:
>
> On 15/02/2023 20.05, Markus Armbruster wrote:
> > The discussion under PATCH 6 makes me think there's a bit of confusion
> > about the actual impact of dropping support for Python 3.6. Possibly
> > because it's spelled out in the commit messa
On 17/2/23 19:52, Thomas Huth wrote:
On 17/02/2023 15.18, Philippe Mathieu-Daudé wrote:
"hw/ptimer.h" API is mostly used by timer / watchdog device
models. Since the SoC / machines only access the ptimer via
reference, they don't need its definition: the declartion is
enough.
On order to reduce
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
This register in AER should be both writeable and should
have a default value with a couple of the errors masked
including the Uncorrectable Internal Error used by CXL for
it's error reporting.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave J
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
PCIe r6.0 Figure 6-3 "Pseudo Logic Diagram for Selected Error Message Control
and Status Bits" includes a right hand branch under "All PCI Express devices"
that allows for messages to be generated or sent onwards without SERR#
being set as long as t
I think it's guest memory again. IMHO It's a part of a memory pool and
not real IO data (unless this was pagefile data).
The first 16 bytes look like POOL_HEADER structure.
The first dump contained signature from FilterManager and the latest
contains two structures from Ntfs.
It's not clear to me w
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 in
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci-bridge/cxl_root_port.c | 61 +
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
This enables AER error injection to function as expected.
It is intended as a building block in enabling CXL RAS error injection
in the following patches.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/mem/cxl_type3.c | 13 +
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
This infrastructure will be reused for CXL RAS error injection
in patches that follow.
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci/pci-internal.h | 1 -
include/hw/pci/pcie_aer.h | 1 +
2 files changed, 1 insert
Remove a pointless cast in ptimer_tick() and rename 'ptimer_state'
as 'PTimer' to follow the Structure naming convention.
See docs/devel/style.rst:
Variables are lower_case_with_underscores; easy to type and
read. Structured type names are in CamelCase; harder to type
but standing out. En
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
As these are about to be modified, fix the endian handle for
this set of registers rather than making it worse.
Note that CXL is currently only supported in QEMU on
x86 (arm64 patches out of tree) so we aren't going to yet hit
an problems with big
On 2/17/23 10:29 AM, Jonathan Cameron wrote:
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to r
On Tue, Feb 14, 2023 at 12:26 PM Kevin Wolf wrote:
>
> Am 14.02.2023 um 15:03 hat Paolo Bonzini geschrieben:
> > In the case of Python the issue is not the interpreter per se, though
> > there are a couple new feature in Python 3.7 that are quite nice (for
> > example improved data classes[1] or c
Hello,
This patchset builds upon the memfd_restricted() system call that has
been discussed in the ‘KVM: mm: fd-based approach for supporting KVM’
patch series, at
https://lore.kernel.org/lkml/20221202061347.1070246-1-chao.p.p...@linux.intel.com/T/#m7e944d7892afdd1d62a03a287bd488c56e377b0c
The tr
Allow userspace to hint the kernel to use Transparent HugePages to
back restricted memory on a per-file basis.
Signed-off-by: Ackerley Tng
---
include/uapi/linux/restrictedmem.h | 1 +
mm/restrictedmem.c | 27 +--
2 files changed, 18 insertions(+), 10 del
Tests that when RMFD_HUGEPAGE is specified, restrictedmem will be
backed by Transparent HugePages.
Signed-off-by: Ackerley Tng
---
.../restrictedmem_hugepage_test.c | 25 +++
1 file changed, 25 insertions(+)
diff --git
a/tools/testing/selftests/restrictedmem/restric
Am 17. Februar 2023 14:18:31 UTC schrieb "Philippe Mathieu-Daudé"
:
>Following the recommendation added in commit a98c370c46
>("typedefs: (Re-)sort entries alphabetically"), and similarly
>to commit 64baadc272 ("Sort include/qemu/typedefs.h"), sort
>again the type definitions (in case-insensiti
ping. Is there anything I can do to help this get merged?
Best regards,
John Berberian, Jr.
在 2023/2/18 0:54, Strahinja Jankovic 写道:
Hi,
I tried running Avocado tests for cubieboard with following command:
ARMBIAN_ARTIFACTS_CACHED=yes AVOCADO_ALLOW_LARGE_STORAGE=yes avocado
--show=app,console run-t machine:cubieboard
tests/avocado/boot_linux_console.py
Without this patch all
Thanks to everyone.
Ok , so I need to run QEMU in Full System Emulation mode to run the
Solaris binary.
Is the *qemu-kvm* , the only package required to be installed ( on RHEL
machine) to launch QEMU or there are some packages also.
Also I would need the Solars OS image, right?
Regards,
Ginu
On 2/17/23 10:34, Daniel Henrique Barboza wrote:
+void helper_cbo_zero(CPURISCVState *env, target_ulong address)
+{
+RISCVCPU *cpu = env_archcpu(env);
+uintptr_t ra = GETPC();
+uint16_t cbozlen;
+void *mem;
+
+check_zicbo_envcfg(env, MENVCFG_CBZE, ra);
+
+/* Get the size o
On 2/17/23 10:34, Daniel Henrique Barboza wrote:
+/*
+ * Section 2.5.2 of cmobase v1.0.1:
+ *
+ * "A cache-block management instruction is permitted to
+ * access the specified cache block whenever a load instruction
+ * or store instruction is permitted to access the corr
On 2/17/23 10:11, Fabiano Rosas wrote:
This is in preparation for restricting compilation of some parts of
debug_helper.c to TCG only.
Signed-off-by: Fabiano Rosas
---
Dropped r-bs because I added a few more ifs in debug_helper.c
---
target/arm/cpu.c | 6 --
target/arm/debug_hel
On 2/17/23 10:11, Fabiano Rosas wrote:
The next few patches will move helpers under CONFIG_TCG. We'd prefer
to keep the debug helpers and debug registers close together, so
rearrange the file a bit to be able to wrap the helpers with a TCG
ifdef.
Signed-off-by: Fabiano Rosas
---
target/arm/deb
On 2/17/23 10:11, Fabiano Rosas wrote:
diff --git a/target/arm/meson.build b/target/arm/meson.build
index a5191b57e1..b0bc8a3cea 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -1,6 +1,7 @@
arm_ss = ss.source_set()
arm_ss.add(files(
'cpu.c',
+ 'cpu64.c',
'debug_he
ping
On Tue, Jan 31, 2023 at 2:30 PM wlfightup wrote:
>
> When vfio-pci devices are attached to the downstream, pcie acs
> capability may be needed, Consistent with physical machine.
>
> It has been tested in our environment, and pcie acs capability
> is required in some scenarios.
>
> Claim ACS
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