On 2/17/23 10:34, Daniel Henrique Barboza wrote:
+ /*
+ * Section 2.5.2 of cmobase v1.0.1:
+ *
+ * "A cache-block management instruction is permitted to
+ * access the specified cache block whenever a load instruction
+ * or store instruction is permitted to access the corresponding
+ * physical addresses. If neither a load instruction nor store
+ * instruction is permitted to access the physical addresses,
+ * but an instruction fetch is permitted to access the physical
+ * addresses, whether a cache-block management instruction is
+ * permitted to access the cache block is UNSPECIFIED.
+ *
+ * This means we have to make a choice of whether checking
+ * MMU_INST_FETCH is worth it or not. We'll go the easier
+ * route and check MMU_DATA_LOAD and MMU_DATA_STORE only.
+ */
+ ret = probe_access_range_flags(env, address, cbomlen,
+ MMU_DATA_LOAD,
+ mmu_idx, true, &phost, ra);
+
+ if (ret == TLB_INVALID_MASK) {
+ probe_access_range_flags(env, address, cbomlen,
+ MMU_DATA_STORE,
+ mmu_idx, true, &phost, ra);
+ }
Not correct, at minimum for discarding the result of the second call. But I suggested a
different ordering of operations which avoid a third probe.
r~
