Re: [PATCH v4 3/8] hw/pci-bridge/cxl_root_port: Wire up AER

[Dave Jiang]

On 2/17/23 10:29 AM, Jonathan Cameron wrote:

We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c

Signed-off-by: Jonathan Cameron <jonathan.came...@huawei.com>

Reviewed-by: Dave Jiang <dave.ji...@intel.com>

---
  hw/pci-bridge/cxl_root_port.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
index 6664783974..00195257f7 100644
--- a/hw/pci-bridge/cxl_root_port.c
+++ b/hw/pci-bridge/cxl_root_port.c
@@ -187,12 +187,15 @@ static void cxl_rp_write_config(PCIDevice *d, uint32_t 
address, uint32_t val,
                                  int len)
  {
      uint16_t slt_ctl, slt_sta;
+    uint32_t root_cmd =
+        pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);

pcie_cap_slot_get(d, &slt_ctl, &slt_sta);

      pci_bridge_write_config(d, address, val, len);
      pcie_cap_flr_write_config(d, address, val, len);
      pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
      pcie_aer_write_config(d, address, val, len);
+    pcie_aer_root_write_config(d, address, val, len, root_cmd);

cxl_rp_dvsec_write_config(d, address, val, len);

  }