Expose the ethernet header so that igb can utilize it to perform the
internal routing among its SR-IOV functions.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
---
hw/net/net_tx_pkt.c | 6 ++
hw/net/net_tx_pkt.h | 8
2 files changed, 14 ins
This automates ethtool tests for igb registers, interrupts, etc.
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 1 +
.../org.centos/stream/8/x86_64/test-avocado | 1 +
tests/avocado/igb.py | 38 +++
3 files changed, 4
Based-on: <20230130134715.76604-1-akihiko.od...@daynix.com>
([PATCH v4 00/28] e1000x cleanups (preliminary for IGB))
igb is a family of Intel's gigabit ethernet controllers. This series implements
82576 emulation in particular. You can see the last patch for the documentation.
Note that there is
This change is derived from qtest for e1000e device.
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 2 +
tests/qtest/fuzz/generic_fuzz_configs.h | 5 +
tests/qtest/igb-test.c | 243
tests/qtest/libqos/igb.c
Some definitions in the header files are invalid for igb so extract
them to new header files to keep igb from referring to them.
Signed-off-by: Gal Hammer
Signed-off-by: Marcel Apfelbaum
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
---
hw/net/e1000.c | 1 +
hw/ne
Markus Armbruster wrote:
> The script drops #include "qemu/osdep.h" from headers. Mention it in
> the commit message it uses for --git.
>
> Signed-off-by: Markus Armbruster
> ---
> scripts/clean-includes | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/scripts/clean-
On 2023/01/30 22:22, Sriram Yagnaraman wrote:
Use PFRSTD to reset RSTI bit for VFs, and raise VFLRE interrupt when VF
is reset.
Signed-off-by: Sriram Yagnaraman
---
hw/net/e1000x_regs.h | 1 +
hw/net/igb_core.c| 33 +
hw/net/trace-events | 2 ++
3 fil
On 2023/01/30 22:22, Sriram Yagnaraman wrote:
Also add checks for RXDCTL/TXDCTL queue enable bits
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 41 ++---
hw/net/igb_regs.h | 4 +++-
2 files changed, 33 insertions(+), 12 deletions(-)
diff --gi
On 2023/01/30 23:19, Akihiko Odaki wrote:
On 2023/01/30 22:22, Sriram Yagnaraman wrote:
Also add checks for RXDCTL/TXDCTL queue enable bits
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 41 ++---
hw/net/igb_regs.h | 4 +++-
2 files changed, 3
On 2023/01/30 22:23, Sriram Yagnaraman wrote:
Signed-off-by: Sriram Yagnaraman
---
hw/net/igb_core.c | 48 +++
1 file changed, 40 insertions(+), 8 deletions(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index cea7c036f0..89650fcfd4 100644
-
On 12/01/2023 16.20, Ilya Leoshkevich wrote:
Add libdw-based functions for loading and querying debuginfo. Load
debuginfo from the system and the linux-user loaders.
This is useful for the upcoming perf support, which can then put
human-readable guest symbols instead of raw guest PCs into perfma
V3: Thanks to Michael Tsirkin
- Update tests/data/acpi/q35/DSDT.cxl to reflect dropping of the duplicate
_UID.
Usual dance with marking table to be ignored by test then making change and
finally
updating the table with the new version and dropping the entry preventing
the tests
from ru
msix_init_exclusive_bar() can fail, so if it does cleanup the address space.
Reviewed-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index dae4fd89ca..
Fix capitalization difference between struct name and typedef.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_downstream.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw
From: Gregory Price
Current code sets to STORAGE_EXPRESS and then overrides it.
Reviewed-by: Davidlohr Bueso
Reviewed-by: Ira Weiny
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/me
On 2023/01/29 5:57, Sriram Yagnaraman wrote:
-Original Message-
From: Akihiko Odaki
Sent: Thursday, 26 January 2023 12:32
To: Sriram Yagnaraman ; Jason Wang
Cc: Dmitry Fleytman ; Michael S. Tsirkin
; Marcel Apfelbaum ;
Alex Bennée ; Philippe Mathieu-Daudé
; Thomas Huth ; Wainer dos Sant
From: Gregory Price
Remove usage of magic numbers when accessing capacity fields and replace
with CXL_CAPACITY_MULTIPLIER, matching the kernel definition.
Signed-off-by: Gregory Price
Reviewed-by: Davidlohr Bueso
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Jonathan Cameron
---
v2:
Ch
Next patch will drop duplicate _UID entry so allow update.
Signed-off-by: Jonathan Cameron
---
v3: New patch
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
Noticed as this prevents iASL disasembling the DSDT table.
Reviewed-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
hw/i386/acpi-build.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 127c4e2d50..a584b62ae2 100644
--- a/hw/i386/acpi-build.
Dropping the ID effects this table in trivial fashion.
Signed-off-by: Jonathan Cameron
---
v3: New patch to update the table.
tests/data/acpi/q35/DSDT.cxl| Bin 9636 -> 9622 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 files changed, 1 deletion(-)
diff --git a/t
From: Ira Weiny
Gcc requires constant versions of cpu_to_le* calls.
Add a 64 bit version.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
v2: Update comment (Philippe)
---
include/qemu/bswap.h | 12 +++-
1
From: Ira Weiny
UUID's are defined as network byte order fields. No static initializer
was available for UUID's in their standard big endian format.
Define a big endian initializer for UUIDs.
Signed-off-by: Ira Weiny
Signed-off-by: Jonathan Cameron
---
include/qemu/uuid.h | 12
From: Ira Weiny
The cel_uuid was programatically generated previously because there was
no static initializer for network order UUIDs.
Use the new network order initializer for cel_uuid. Adjust
cxl_initialize_mailbox() because it can't fail now.
Update specification reference.
Reviewed-by: Ph
On 2023/01/29 14:33, Alexander Bulekov wrote:
Signed-off-by: Alexander Bulekov
---
Hi Akihiko,
Thank you for adding a fuzzer config for this device. The fuzzer found
some crashes. Many of these are probably duplicates - the crash
deduplication script has limitations. Also some of these might not
On Mon, 2023-01-30 at 15:33 +0100, Thomas Huth wrote:
> On 12/01/2023 16.20, Ilya Leoshkevich wrote:
> > Add libdw-based functions for loading and querying debuginfo. Load
> > debuginfo from the system and the linux-user loaders.
> >
> > This is useful for the upcoming perf support, which can then
Igor Mammedov 于2023年1月24日周二 18:30写道：
>
> On Tue, 17 Jan 2023 19:15:21 +0800
> Sun Feng wrote:
>
> > Migrate from aarch64 host with PAGE_SIZE 64k to 4k failed with following
> > errors:
> >
> > qmp_cmd_name: migrate-incoming, arguments: {"uri": "tcp:[::]:49152"}
> > {"timestamp": {"seconds": 1673
On Fri, Jan 27, 2023 at 03:26:15PM -0600, Eric Blake wrote:
> In https://bugzilla.redhat.com/show_bug.cgi?id=2055229, the question
> was raised on how to make qemu-storage-daemon sufficiently powerful to
> be a full-blown replacement to qemu-nbd. One of the features still
> lacking is the ability
On Mon, Jan 30, 2023 at 10:47:25PM +0800, Feng Sun wrote:
> Igor Mammedov 于2023年1月24日周二 18:30写道：
> >
> > On Tue, 17 Jan 2023 19:15:21 +0800
> > Sun Feng wrote:
> >
> > > Migrate from aarch64 host with PAGE_SIZE 64k to 4k failed with following
> > > errors:
> > >
> > > qmp_cmd_name: migrate-incom
On Mon, Jan 30, 2023 at 10:50:01PM +0900, Akihiko Odaki wrote:
> The expiration time provided for timer_mod() can overflow if a
> ridiculously large value is set to the comparator register. The
> resulting value can represent a past time after rounded, forcing the
> timer to fire immediately. If th
On Mon, Jan 30, 2023 at 10:47:07PM +0900, Akihiko Odaki wrote:
> filter-dump specifiees Ethernet as PCAP LinkType, which does not expect
> virtio-net header. Having virtio-net header in such PCAP file breaks
> PCAP unconsumable. Unfortunately currently there is no LinkType for
> virtio-net so for n
On Mon, 30 Jan 2023 at 07:33, Daniel P. Berrangé wrote:
>
> On Sun, Jan 29, 2023 at 06:39:49PM +0800, Sam Li wrote:
> > This patch extends virtio-blk emulation to handle zoned device commands
> > by calling the new block layer APIs to perform zoned device I/O on
> > behalf of the guest. It support
On 2023/01/31 0:12, Michael S. Tsirkin wrote:
On Mon, Jan 30, 2023 at 10:47:07PM +0900, Akihiko Odaki wrote:
filter-dump specifiees Ethernet as PCAP LinkType, which does not expect
virtio-net header. Having virtio-net header in such PCAP file breaks
PCAP unconsumable. Unfortunately currently the
On Mon, Jan 30, 2023 at 02:58:01PM +, Daniel P. Berrangé wrote:
> Obviously at startup QEMU can trivially inherit the FDs from whatever
> spawned it. The only task is to identify the FDs that are passed into,
> and systemd defined a mechanism for this using LISTEN_FDNAMES. IOW the
> socket acti
On Tue, Jan 31, 2023 at 12:36:38AM +0900, Akihiko Odaki wrote:
> On 2023/01/31 0:12, Michael S. Tsirkin wrote:
> > On Mon, Jan 30, 2023 at 10:47:07PM +0900, Akihiko Odaki wrote:
> > > filter-dump specifiees Ethernet as PCAP LinkType, which does not expect
> > > virtio-net header. Having virtio-net
Antonio Caggiano writes:
> Implement get_egl_display callback for virglrenderer.
>
> Signed-off-by: Antonio Caggiano
> ---
> hw/display/virtio-gpu-virgl.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-vir
On Mon, Jan 30, 2023 at 03:44:48PM +, Richard W.M. Jones wrote:
> On Mon, Jan 30, 2023 at 02:58:01PM +, Daniel P. Berrangé wrote:
> > Obviously at startup QEMU can trivially inherit the FDs from whatever
> > spawned it. The only task is to identify the FDs that are passed into,
> > and syst
v3: New patch fixing related endian issues + endian fixes in the injection
code (thanks for feedback off list)
Dropped header logging for correctable errors as there is no such
logging in the specification.
v2: Thanks to Mike Maslenkin for review.
- Fix wrong parameter type to ct3d_qmp
This register in AER should be both writeable and should
have a default value with a couple of the errors masked
including the Uncorrectable Internal Error used by CXL for
it's error reporting.
Signed-off-by: Jonathan Cameron
---
hw/pci/pcie_aer.c | 4
include/hw/pci/pcie_regs.h |
PCIe r6.0 Figure 6-3 "Pseudo Logic Diagram for Selected Error Message Control
and Status Bits" includes a right hand branch under "All PCI Express devices"
that allows for messages to be generated or sent onwards without SERR#
being set as long as the appropriate per error class bit in the PCIe
Dev
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c | 61 +++
1 file changed, 61 insertions(+)
diff --git a/h
This enables AER error injection to function as expected.
It is intended as a building block in enabling CXL RAS error injection
in the following patches.
Signed-off-by: Jonathan Cameron
---
hw/mem/cxl_type3.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/mem/cxl_type3.c
As these are about to be modified, fix the endian handle for
this set of registers rather than making it worse.
Note that CXL is currently only supported in QEMU on
x86 (arm64 patches out of tree) so we aren't going to yet hit
an problems with big endian. However it is good to avoid making
things
This infrastructure will be reused for CXL RAS error injection
in patches that follow.
Signed-off-by: Jonathan Cameron
---
hw/pci/pci-internal.h | 1 -
include/hw/pci/pcie_aer.h | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci/pci-internal.h b/hw/pci/pci-internal.h
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in an
Antonio Caggiano writes:
> Request Venus when initializing VirGL.
>
> Signed-off-by: Antonio Caggiano
> ---
> hw/display/virtio-gpu-virgl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-virgl.c
> index 16f600adbb
On Mon, 30 Jan 2023 at 09:03, Akihiko Odaki wrote:
>
> vhost_dev_cleanup() clears vhost_dev so back up its vqs member to free
> the memory pointed by the member.
>
> Fixes: 98fc1ada4c ("virtio: add vhost-user-fs base device")
> Signed-off-by: Akihiko Odaki
> ---
> hw/virtio/vhost-user-fs.c | 4 +
On Mon, 30 Jan 2023 at 07:48, Alex Bennée wrote:
>
> While ioeventfds are needed for good performance with KVM guests it
> should not be a gating requirement. We can run vhost-user backends using
> simulated ioeventfds or inband signalling.
>
> With this change I can run:
>
> $QEMU $OPTS \
>
Antonio Caggiano writes:
> From: Gerd Hoffmann
>
> Use VIRTIO_GPU_SHM_ID_HOST_VISIBLE as id for virtio-gpu.
>
> Signed-off-by: Antonio Caggiano
> Acked-by: Michael S. Tsirkin
> ---
> v3: Formatting fixes
>
> hw/display/virtio-gpu-pci.c| 15 +++
> hw/display/virtio-gpu.c
Antonio Caggiano writes:
> Support BLOB resources creation, mapping and unmapping by calling the
> new stable virglrenderer 0.10 interface. Only enabled when available and
> via the blob config. E.g. -device virtio-vga-gl,blob=true
>
> Signed-off-by: Antonio Caggiano
> Signed-off-by: Dmitry Os
On 1/28/23 2:14 PM, Michael S. Tsirkin wrote:
> On Sat, Jan 28, 2023 at 08:20:55AM -0500, Chuck Zmudzinski wrote:
> > On 1/28/23 5:26 AM, Michael S. Tsirkin wrote:
> > > On Fri, Jan 27, 2023 at 10:39:28PM -0500, Chuck Zmudzinski wrote:
> > >> On 1/27/2023 8:28 AM, Michael S. Tsirkin wrote:
> > >> >
On Mon, Jan 30, 2023 at 10:51:52PM +0900, Akihiko Odaki wrote:
> We found a case where the source passed to flatview_write_continue() may
> overlap with the destination when fuzzing igb, a new proposed network
> device with sanitizers.
>
> igb uses pci_dma_map() to get Tx packet, and pci_dma_write
On Mon, 30 Jan 2023 11:45:45 +0100
Maxime Coquelin wrote:
> This series continues the work done to get rid of harmful
> language in the Vhost-user specification.
>
> While the spec texts were changed to replace slave with
> backend, the protocol features and messages names hadn't
> been changed.
On Mon, Jan 30, 2023 at 02:58:01PM +, Daniel P. Berrangé wrote:
> > I'm at a point where I can take a shot at implementing this, but want
> > some feedback on whether it is better to try to shoehorn a generic
> > solution into the existing @fd member of the SocketAddressType union,
> > or wheth
On Mon, Jan 30, 2023 at 04:45:08PM +, Daniel P. Berrangé wrote:
> which is LISTEN_FDS=2, LISTEN_FDNAMES=control,vnc
Colon for separating the elements not comma.
Rich.
--
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
Read my programming and virtualization blog
Am 26. Januar 2023 21:17:36 UTC schrieb Bernhard Beschow :
>These legacy ISA IRQs allow the PIIX IDE functions to be wired up in
>their south bridges and the VIA IDE functions to disuse
>PCI_INTERRUPT_LINE as outlined in https://lists.nongnu.org/archive/html/
>qemu-devel/2020-03/msg01707.html .
Antonio Caggiano writes:
> This series of patches enables support for the Venus VirtIO-GPU Vulkan
> driver by adding some features required by the driver:
>
> - CONTEXT_INIT
> - HOSTMEM
> - RESOURCE_UUID
> - BLOB_RESOURCES
>
> In addition to these features, Venus capset support was required
> t
+ Mark whom I've discussed "multiple ISA buses" before
Am 26. Januar 2023 21:17:30 UTC schrieb Bernhard Beschow :
>This series resolves the global "isabus" variable and is basically a v2 of [1].
>
>Note that the majority of the work consists of fixing ISA API calls in PIIX IDE
>
>which implicitly
On Mon, Jan 30, 2023 at 01:11:50PM +, Jonathan Cameron wrote:
> On Thu, 5 Jan 2023 14:38:07 +
> Jonathan Cameron wrote:
>
> > On Mon, 28 Nov 2022 10:01:56 -0500
> > Gregory Price wrote:
> >
> > > Defines are starting to exceed line length limits, align them for
> > > cleanliness before
On 1/29/23 02:45, Bin Meng wrote:
On Thu, Jan 26, 2023 at 9:54 PM Daniel Henrique Barboza
wrote:
As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a
mem_size (which is defaulted to MachineState::ram_size in all boards)
and the FDT pointer. And it makes a very important assump
On Mon, Jan 30, 2023 at 01:24:51PM +, Jonathan Cameron wrote:
>
> > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
> > index e59ba22387..6893f54e28 100644
> > --- a/tests/qtest/cxl-test.c
> > +++ b/tests/qtest/cxl-test.c
> > @@ -40,32 +40,46 @@
> >"-device cxl-rp,id=rp2,bus=c
Tested and reviewed this series (except my own patches, obviously).
Reviewed-by: Gregory Price
Tested-by: Gregory Price
On Mon, Jan 30, 2023 at 02:36:55PM +, Jonathan Cameron wrote:
> V3: Thanks to Michael Tsirkin
> - Update tests/data/acpi/q35/DSDT.cxl to reflect dropping of the duplica
Thomas Huth writes:
> There is only one job depending on the build-gprof-gcov job, so
> there is no real need for keeping this separate. It likely only
> has been split since the complete runtime is more than 60 minutes,
> but that can be better handled with a proper timeout setting instead.
>
Thomas Huth writes:
> Let's safe some CI minutes by merging these two jobs. We can now
> also drop "--disable-capstone" since the capstone submodule has
> been removed a while ago. We should rather tes --disable-fdt now
> to test a compilation without the "dtc" submodule (for this we
> have to
On 1/30/23 14:16, Daniel Henrique Barboza wrote:
On 1/29/23 02:45, Bin Meng wrote:
On Thu, Jan 26, 2023 at 9:54 PM Daniel Henrique Barboza
wrote:
As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a
mem_size (which is defaulted to MachineState::ram_size in all boards)
and t
CC: maintainers and qemu-devel
Use ./scripts/get_maintainer.pl to have the list of the maintainers.
Always send your patches to qemu-devel&nongnu.org
Thanks,
Laurent
Le 30/01/2023 à 18:54, ~vlaomao a écrit :
A bug was found with the vmxnet3 driver, after changing the MAC address
and rebooting
Le 30/01/2023 à 18:28, ~vlaomao a écrit :
From: VlaoMao
Changing the address with a subsequent reboot makes this address permanent
until the vm is turned off
Missing Signed-off-by.
See https://www.qemu.org/docs/master/devel/submitting-a-patch.html
---
hw/net/vmxnet3.c | 2 ++
1 file ch
This series implements the FEAT_FGT fine-grained traps architectural
feature. The bulk of this is new system registers HFGRTR_EL2, HFGWTR_EL2,
HFGITR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, which have bits that enable
trapping of system register and system instruction accesses on a
fine-grained basis (typic
We added the CPAccessResult values CP_ACCESS_TRAP_UNCATEGORIZED_EL2
and CP_ACCESS_TRAP_UNCATEGORIZED_EL3 purely in order to use them in
the ats_access() function, but doing so was incorrect (a bug fixed in
a previous commit). There aren't any cases where we want an access
function to be able to re
The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT
S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name
them AT S1E1R and AT S1E1W (which are entirely different
instructions). Fix the names.
(This has no guest-visible effect as the names are for debug purposes
only.)
S
Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 0..11.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230127175507.2895013-11-peter.mayd...@linaro.org
---
target/arm/cpregs.h | 14 ++
target/arm/helper.c | 17
The semantics of HSTR_EL2 require that it traps cpreg accesses
to EL2 for:
* EL1 accesses
* EL0 accesses, if the access is not UNDEFINED when the
trap bit is 0
(You can see this in the I_ZFGJP priority ordering, where HSTR_EL2
traps from EL1 to EL2 are priority 12, UNDEFs are priority 13, and
Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 36..63.
Of these, some correspond to RAS registers which we implement as
always-UNDEF: these don't need any extra handling for FGT because the
UNDEF-to-EL1 always takes priority over any theoretical
FGT-trap-to-EL2.
Bi
Implement the machinery for fine-grained traps on normal sysregs.
Any sysreg with a fine-grained trap will set the new field to
indicate which FGT register bit it should trap on.
FGT traps only happen when an AArch64 EL2 enables them for
an AArch64 EL1. They therefore are only relevant for AArch32
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 12..17. These bits cover AT address
translation instructions.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230127175507.2895013-18-peter.mayd...@linaro.org
---
target/arm/cpregs.h | 6
Implement the HFGITR_EL2.ERET fine-grained trap. This traps
execution from AArch64 EL1 of ERET, ERETAA and ERETAB. The trap is
reported with a syndrome value of 0x1a.
The trap must take precedence over a possible pointer-authentication
trap for ERETAA and ERETAB.
Signed-off-by: Peter Maydell
R
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 48..63.
Some of these bits are for trapping instructions which are
not in the system instruction encoding (i.e. which are
not handled by the ARMCPRegInfo mechanism):
* ERET, ERETAA, ERETAB
* SVC
We will have to ha
The AArch32 ATS12NSO* address translation operations are supposed to
trap to either EL2 or EL3 if they're executed at Secure EL1 (which
can only happen if EL3 is AArch64). We implement this, but we got
the syndrome value wrong: like other traps to EL2 or EL3 on an
AArch32 cpreg access, they should
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 0..11. These bits cover various
cache maintenance operations.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230127175507.2895013-17-peter.mayd...@linaro.org
---
target/arm/cpregs.h | 14
Implement the HFGITR_EL2.SVC_EL0 and SVC_EL1 fine-grained traps.
These trap execution of the SVC instruction from AArch32 and AArch64.
(As usual, AArch32 can only trap from EL0, as fine grained traps are
disabled with an AArch32 EL1.)
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
M
Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 24..35.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230127175507.2895013-13-peter.mayd...@linaro.org
---
target/arm/cpregs.h | 12
target/arm/helper.c | 14 ++
2
FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and
MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug
Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0,
MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their
AArch32 equivalents). This trapping is in
Update the ID registers for TCG's '-cpu max' to report the
presence of FEAT_FGT Fine-Grained Traps support.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230127175507.2895013-24-peter.mayd...@linaro.org
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c
Mark up the sysreg definitons for the registers trapped
by HDFGRTR/HDFGWTR bits 0..11. These cover various debug
related registers.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230127175507.2895013-15-peter.mayd...@linaro.org
---
target/arm/cpregs.h | 12 +
The HSTR_EL2 register has a collection of trap bits which allow
trapping to EL2 for AArch32 EL0 or EL1 accesses to coprocessor
registers. The specification of these bits is that when the bit is
set we should trap
* EL1 accesses
* EL0 accesses, if the access is not UNDEFINED when the
trap bit
Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 12..23.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230127175507.2895013-12-peter.mayd...@linaro.org
---
target/arm/cpregs.h | 12
target/arm/helper.c | 12
2 f
Mark up the sysreg definitions for the registers trapped
by HDFGRTR/HDFGWTR bits 12..x.
Bits 12..22 and bit 58 are for PMU registers.
The remaining bits in HDFGRTR/HDFGWTR are for traps on
registers that are part of features we don't implement:
Bits 23..32 and 63 : FEAT_SPE
Bits 33..48 : FEAT_ET
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 18..47. These bits cover TLBI
TLB maintenance instructions.
(If we implemented FEAT_XS we would need to trap some of the
instructions added by that feature using these bits; but we don't
yet, so will need to add the
Define the system registers which are provided by the
FEAT_FGT fine-grained trap architectural feature:
HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2
All these registers are a set of bit fields, where each bit is set
for a trap and clear to not trap on a particular system register
Rearrange the code in do_coproc_insn() so that we calculate the
syndrome value for a potential trap early; we're about to add a
second check that wants this value earlier than where it is currently
determined.
(Specifically, a trap to EL2 because of HSTR_EL2 should take
priority over an UNDEF to E
The HSTR_EL2 register is not supposed to have an effect unless EL2 is
enabled in the current security state. We weren't checking for this,
which meant that if the guest set up the HSTR_EL2 register we would
incorrectly trap even for accesses from Secure EL0 and EL1.
Add the missing checks. (Other
On Mon, Jan 30, 2023 at 10:17:48AM -0500, Stefan Hajnoczi wrote:
> On Mon, 30 Jan 2023 at 07:33, Daniel P. Berrangé wrote:
> >
> > On Sun, Jan 29, 2023 at 06:39:49PM +0800, Sam Li wrote:
> > > This patch extends virtio-blk emulation to handle zoned device commands
> > > by calling the new block la
Antonio Caggiano writes:
> Implement an unrealize function for virtio gpu device.
>
> Signed-off-by: Antonio Caggiano
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
The dcblc instruction is used by u-boot in mpc85xx/start.S. Without it,
an illegal istruction exception is generated very early in the boot
process where the processor is not yet able to handle exceptions. See:
https://github.com/u-boot/u-boot/blob/v2023.01/arch/powerpc/cpu/mpc85xx/start.S#L1840
On 1/29/23 22:41, LIU Zhiwei wrote:
On 2023/1/30 13:43, Richard Henderson wrote:
On 1/29/23 16:03, LIU Zhiwei wrote:
Thanks. It's a bug. We should load all memory addresses to local TCG temps
first.
Do you think we should probe all the memory addresses for the store pair instructions?
If s
On 1/29/23 23:27, Daniel P. Berrangé wrote:
On Sun, Jan 29, 2023 at 05:38:08PM -0500, Emilio Cota wrote:
Since this is a correctness issue, I think we should ship with qtree
and use it when configuring with glib <2.76.0. For later glib versions
we would just use gtree, e.g. via typedef + inline
On Mon, Jan 30, 2023 at 11:02:25PM +0900, Akihiko Odaki wrote:
> vhost_dev_cleanup() clears vhost_dev so back up its vqs member to free
> the memory pointed by the member.
>
> Fixes: 98fc1ada4c ("virtio: add vhost-user-fs base device")
> Signed-off-by: Akihiko Odaki
Reviewed-by: Michael S. Tsirk
On 1/30/23 00:07, Sergey Matyukevich wrote:
From: Sergey Matyukevich
According to priviledged spec, if [sm]tval is written with a nonzero
value when a breakpoint exception occurs, then [sm]tval will contain
the faulting virtual address. Set tval to hit address when breakpoint
exception is trigge
On 1/30/23 02:01, Daniel P. Berrangé wrote:
I vaguely recall someone mentioned problems with atomic ops in the past,
or was it 128-bit ints, caused implications for the codebase ?
TCG_OVERSIZED_GUEST, where 32-bit host running 64-bit guest cannot run the guest except in
round-robin mode. It's
On 1/30/23 03:12, fa...@mail.ustc.edu.cn wrote:
1. "The memcpy is definitely wrong, because you're casting a guest address into a
host address, which is incorrect. You have to use g2h()."
There is no need to use g2h(), Because there are both guest address whether source or
dest memory. refer t
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